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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
wdenk9c53f402003-10-15 23:53:47 +00002/*
3 * MPC85xx Internal Memory Map
4 *
Prabhakar Kushwahabeebb882012-04-24 20:16:49 +00005 * Copyright 2007-2012 Freescale Semiconductor, Inc.
Ed Swarthout52b98522007-07-27 01:50:51 -05006 *
wdenk9c53f402003-10-15 23:53:47 +00007 * Copyright(c) 2002,2003 Motorola Inc.
8 * Xianghua Xiao (x.xiao@motorola.com)
wdenk9c53f402003-10-15 23:53:47 +00009 */
10
11#ifndef __IMMAP_85xx__
12#define __IMMAP_85xx__
13
Jon Loeliger3ec4c082006-10-20 17:16:35 -050014#include <asm/types.h>
Peter Tyser4c82e722009-05-21 12:09:59 -050015#include <asm/fsl_dma.h>
Jon Loeliger3ec4c082006-10-20 17:16:35 -050016#include <asm/fsl_i2c.h>
York Sun37562f62013-10-22 12:39:02 -070017#include <fsl_ifc.h>
Ruchika Guptae24fde92014-09-09 11:50:30 +053018#include <fsl_sec.h>
gaurav rana9d171da2015-02-27 09:43:49 +053019#include <fsl_sfp.h>
Haiying Wang4f84bbd2008-10-29 11:05:55 -040020#include <asm/fsl_lbc.h>
Shaohui Xie513eaf22015-10-26 19:47:47 +080021#include <fsl_fman.h>
York Suna21803d2013-11-18 10:29:32 -080022#include <fsl_immap.h>
Jon Loeliger3ec4c082006-10-20 17:16:35 -050023
Kumar Galad5740162009-09-16 09:43:12 -050024typedef struct ccsr_local {
Kumar Gala3d8d9132009-09-28 21:38:00 -050025 u32 ccsrbarh; /* CCSR Base Addr High */
26 u32 ccsrbarl; /* CCSR Base Addr Low */
27 u32 ccsrar; /* CCSR Attr */
Kumar Galad5740162009-09-16 09:43:12 -050028#define CCSRAR_C 0x80000000 /* Commit */
29 u8 res1[4];
Kumar Gala3d8d9132009-09-28 21:38:00 -050030 u32 altcbarh; /* Alternate Configuration Base Addr High */
31 u32 altcbarl; /* Alternate Configuration Base Addr Low */
32 u32 altcar; /* Alternate Configuration Attr */
Kumar Galad5740162009-09-16 09:43:12 -050033 u8 res2[4];
Kumar Gala3d8d9132009-09-28 21:38:00 -050034 u32 bstrh; /* Boot space translation high */
35 u32 bstrl; /* Boot space translation Low */
36 u32 bstrar; /* Boot space translation attributes */
Kumar Galad5740162009-09-16 09:43:12 -050037 u8 res3[0xbd4];
38 struct {
Kumar Gala3d8d9132009-09-28 21:38:00 -050039 u32 lawbarh; /* LAWn base addr high */
40 u32 lawbarl; /* LAWn base addr low */
41 u32 lawar; /* LAWn attributes */
Kumar Galad5740162009-09-16 09:43:12 -050042 u8 res4[4];
43 } law[32];
44 u8 res35[0x204];
45} ccsr_local_t;
46
Kumar Gala3d8d9132009-09-28 21:38:00 -050047/* Local-Access Registers & ECM Registers */
wdenk9c53f402003-10-15 23:53:47 +000048typedef struct ccsr_local_ecm {
Kumar Gala3d8d9132009-09-28 21:38:00 -050049 u32 ccsrbar; /* CCSR Base Addr */
50 u8 res1[4];
51 u32 altcbar; /* Alternate Configuration Base Addr */
52 u8 res2[4];
53 u32 altcar; /* Alternate Configuration Attr */
54 u8 res3[12];
55 u32 bptr; /* Boot Page Translation */
56 u8 res4[3044];
57 u32 lawbar0; /* Local Access Window 0 Base Addr */
58 u8 res5[4];
59 u32 lawar0; /* Local Access Window 0 Attrs */
60 u8 res6[20];
61 u32 lawbar1; /* Local Access Window 1 Base Addr */
62 u8 res7[4];
63 u32 lawar1; /* Local Access Window 1 Attrs */
64 u8 res8[20];
65 u32 lawbar2; /* Local Access Window 2 Base Addr */
66 u8 res9[4];
67 u32 lawar2; /* Local Access Window 2 Attrs */
68 u8 res10[20];
69 u32 lawbar3; /* Local Access Window 3 Base Addr */
70 u8 res11[4];
71 u32 lawar3; /* Local Access Window 3 Attrs */
72 u8 res12[20];
73 u32 lawbar4; /* Local Access Window 4 Base Addr */
74 u8 res13[4];
75 u32 lawar4; /* Local Access Window 4 Attrs */
76 u8 res14[20];
77 u32 lawbar5; /* Local Access Window 5 Base Addr */
78 u8 res15[4];
79 u32 lawar5; /* Local Access Window 5 Attrs */
80 u8 res16[20];
81 u32 lawbar6; /* Local Access Window 6 Base Addr */
82 u8 res17[4];
83 u32 lawar6; /* Local Access Window 6 Attrs */
84 u8 res18[20];
85 u32 lawbar7; /* Local Access Window 7 Base Addr */
86 u8 res19[4];
87 u32 lawar7; /* Local Access Window 7 Attrs */
88 u8 res19_8a[20];
89 u32 lawbar8; /* Local Access Window 8 Base Addr */
90 u8 res19_8b[4];
91 u32 lawar8; /* Local Access Window 8 Attrs */
92 u8 res19_9a[20];
93 u32 lawbar9; /* Local Access Window 9 Base Addr */
94 u8 res19_9b[4];
95 u32 lawar9; /* Local Access Window 9 Attrs */
96 u8 res19_10a[20];
97 u32 lawbar10; /* Local Access Window 10 Base Addr */
98 u8 res19_10b[4];
99 u32 lawar10; /* Local Access Window 10 Attrs */
100 u8 res19_11a[20];
101 u32 lawbar11; /* Local Access Window 11 Base Addr */
102 u8 res19_11b[4];
103 u32 lawar11; /* Local Access Window 11 Attrs */
104 u8 res20[652];
105 u32 eebacr; /* ECM CCB Addr Configuration */
106 u8 res21[12];
107 u32 eebpcr; /* ECM CCB Port Configuration */
108 u8 res22[3564];
109 u32 eedr; /* ECM Error Detect */
110 u8 res23[4];
111 u32 eeer; /* ECM Error Enable */
112 u32 eeatr; /* ECM Error Attrs Capture */
113 u32 eeadr; /* ECM Error Addr Capture */
114 u8 res24[492];
wdenk9c53f402003-10-15 23:53:47 +0000115} ccsr_local_ecm_t;
116
Kumar Gala74e78b62010-04-28 04:02:21 -0500117#define DDR_EOR_RD_BDW_OPT_DIS 0x80000000 /* Read BDW Opt. disable */
118#define DDR_EOR_ADDR_HASH_EN 0x40000000 /* Address hash enabled */
119
Kumar Gala3d8d9132009-09-28 21:38:00 -0500120/* I2C Registers */
wdenk9c53f402003-10-15 23:53:47 +0000121typedef struct ccsr_i2c {
mario.six@gdsys.cc7d43b4e2016-04-25 08:31:01 +0200122 struct fsl_i2c_base i2c[1];
123 u8 res[4096 - 1 * sizeof(struct fsl_i2c_base)];
wdenk9c53f402003-10-15 23:53:47 +0000124} ccsr_i2c_t;
125
York Sun5ddce892016-11-16 11:13:06 -0800126#if defined(CONFIG_ARCH_MPC8540) || \
Tom Rini0b730a02021-05-14 21:34:21 -0400127 defined(CONFIG_ARCH_MPC8548)
Kumar Gala3d8d9132009-09-28 21:38:00 -0500128/* DUART Registers */
wdenk9c53f402003-10-15 23:53:47 +0000129typedef struct ccsr_duart {
Kumar Gala3d8d9132009-09-28 21:38:00 -0500130 u8 res1[1280];
131/* URBR1, UTHR1, UDLB1 with the same addr */
132 u8 urbr1_uthr1_udlb1;
133/* UIER1, UDMB1 with the same addr01 */
134 u8 uier1_udmb1;
135/* UIIR1, UFCR1, UAFR1 with the same addr */
136 u8 uiir1_ufcr1_uafr1;
137 u8 ulcr1; /* UART1 Line Control */
138 u8 umcr1; /* UART1 Modem Control */
139 u8 ulsr1; /* UART1 Line Status */
140 u8 umsr1; /* UART1 Modem Status */
141 u8 uscr1; /* UART1 Scratch */
142 u8 res2[8];
143 u8 udsr1; /* UART1 DMA Status */
144 u8 res3[239];
145/* URBR2, UTHR2, UDLB2 with the same addr */
146 u8 urbr2_uthr2_udlb2;
147/* UIER2, UDMB2 with the same addr */
148 u8 uier2_udmb2;
149/* UIIR2, UFCR2, UAFR2 with the same addr */
150 u8 uiir2_ufcr2_uafr2;
151 u8 ulcr2; /* UART2 Line Control */
152 u8 umcr2; /* UART2 Modem Control */
153 u8 ulsr2; /* UART2 Line Status */
154 u8 umsr2; /* UART2 Modem Status */
155 u8 uscr2; /* UART2 Scratch */
156 u8 res4[8];
157 u8 udsr2; /* UART2 DMA Status */
158 u8 res5[2543];
wdenk9c53f402003-10-15 23:53:47 +0000159} ccsr_duart_t;
160#else /* MPC8560 uses UART on its CPM */
161typedef struct ccsr_duart {
Kumar Gala3d8d9132009-09-28 21:38:00 -0500162 u8 res[4096];
wdenk9c53f402003-10-15 23:53:47 +0000163} ccsr_duart_t;
164#endif
165
Kumar Gala3d8d9132009-09-28 21:38:00 -0500166/* eSPI Registers */
Mingkai Hu946d52b2009-03-31 14:09:40 +0800167typedef struct ccsr_espi {
Kumar Gala3d8d9132009-09-28 21:38:00 -0500168 u32 mode; /* eSPI mode */
169 u32 event; /* eSPI event */
170 u32 mask; /* eSPI mask */
171 u32 com; /* eSPI command */
172 u32 tx; /* eSPI transmit FIFO access */
173 u32 rx; /* eSPI receive FIFO access */
174 u8 res1[8]; /* reserved */
175 u32 csmode[4]; /* 0x2c: sSPI CS0/1/2/3 mode */
176 u8 res2[4048]; /* fill up to 0x1000 */
Mingkai Hu946d52b2009-03-31 14:09:40 +0800177} ccsr_espi_t;
178
Kumar Gala3d8d9132009-09-28 21:38:00 -0500179/* PCI Registers */
wdenk9c53f402003-10-15 23:53:47 +0000180typedef struct ccsr_pcix {
Kumar Gala3d8d9132009-09-28 21:38:00 -0500181 u32 cfg_addr; /* PCIX Configuration Addr */
182 u32 cfg_data; /* PCIX Configuration Data */
183 u32 int_ack; /* PCIX IRQ Acknowledge */
Laurentiu Tudorb173eaf2012-10-05 09:48:51 +0000184 u8 res000c[52];
185 u32 liodn_base; /* PCIX LIODN base register */
Laurentiu TUDOR8bd733b2013-10-23 15:20:27 +0300186 u8 res0044[2996];
187 u32 ipver1; /* PCIX IP block revision register 1 */
188 u32 ipver2; /* PCIX IP block revision register 2 */
Kumar Gala3d8d9132009-09-28 21:38:00 -0500189 u32 potar0; /* PCIX Outbound Transaction Addr 0 */
190 u32 potear0; /* PCIX Outbound Translation Extended Addr 0 */
191 u32 powbar0; /* PCIX Outbound Window Base Addr 0 */
192 u32 powbear0; /* PCIX Outbound Window Base Extended Addr 0 */
193 u32 powar0; /* PCIX Outbound Window Attrs 0 */
194 u8 res2[12];
195 u32 potar1; /* PCIX Outbound Transaction Addr 1 */
196 u32 potear1; /* PCIX Outbound Translation Extended Addr 1 */
197 u32 powbar1; /* PCIX Outbound Window Base Addr 1 */
198 u32 powbear1; /* PCIX Outbound Window Base Extended Addr 1 */
199 u32 powar1; /* PCIX Outbound Window Attrs 1 */
200 u8 res3[12];
201 u32 potar2; /* PCIX Outbound Transaction Addr 2 */
202 u32 potear2; /* PCIX Outbound Translation Extended Addr 2 */
203 u32 powbar2; /* PCIX Outbound Window Base Addr 2 */
204 u32 powbear2; /* PCIX Outbound Window Base Extended Addr 2 */
205 u32 powar2; /* PCIX Outbound Window Attrs 2 */
206 u8 res4[12];
207 u32 potar3; /* PCIX Outbound Transaction Addr 3 */
208 u32 potear3; /* PCIX Outbound Translation Extended Addr 3 */
209 u32 powbar3; /* PCIX Outbound Window Base Addr 3 */
210 u32 powbear3; /* PCIX Outbound Window Base Extended Addr 3 */
211 u32 powar3; /* PCIX Outbound Window Attrs 3 */
212 u8 res5[12];
213 u32 potar4; /* PCIX Outbound Transaction Addr 4 */
214 u32 potear4; /* PCIX Outbound Translation Extended Addr 4 */
215 u32 powbar4; /* PCIX Outbound Window Base Addr 4 */
216 u32 powbear4; /* PCIX Outbound Window Base Extended Addr 4 */
217 u32 powar4; /* PCIX Outbound Window Attrs 4 */
218 u8 res6[268];
219 u32 pitar3; /* PCIX Inbound Translation Addr 3 */
220 u32 pitear3; /* PCIX Inbound Translation Extended Addr 3 */
221 u32 piwbar3; /* PCIX Inbound Window Base Addr 3 */
222 u32 piwbear3; /* PCIX Inbound Window Base Extended Addr 3 */
223 u32 piwar3; /* PCIX Inbound Window Attrs 3 */
224 u8 res7[12];
225 u32 pitar2; /* PCIX Inbound Translation Addr 2 */
226 u32 pitear2; /* PCIX Inbound Translation Extended Addr 2 */
227 u32 piwbar2; /* PCIX Inbound Window Base Addr 2 */
228 u32 piwbear2; /* PCIX Inbound Window Base Extended Addr 2 */
229 u32 piwar2; /* PCIX Inbound Window Attrs 2 */
230 u8 res8[12];
231 u32 pitar1; /* PCIX Inbound Translation Addr 1 */
232 u32 pitear1; /* PCIX Inbound Translation Extended Addr 1 */
233 u32 piwbar1; /* PCIX Inbound Window Base Addr 1 */
234 u8 res9[4];
235 u32 piwar1; /* PCIX Inbound Window Attrs 1 */
236 u8 res10[12];
237 u32 pedr; /* PCIX Error Detect */
238 u32 pecdr; /* PCIX Error Capture Disable */
239 u32 peer; /* PCIX Error Enable */
240 u32 peattrcr; /* PCIX Error Attrs Capture */
241 u32 peaddrcr; /* PCIX Error Addr Capture */
242 u32 peextaddrcr; /* PCIX Error Extended Addr Capture */
243 u32 pedlcr; /* PCIX Error Data Low Capture */
244 u32 pedhcr; /* PCIX Error Error Data High Capture */
245 u32 gas_timr; /* PCIX Gasket Timer */
246 u8 res11[476];
wdenk9c53f402003-10-15 23:53:47 +0000247} ccsr_pcix_t;
248
Matthew McClintock31db9c32006-06-28 10:45:17 -0500249#define PCIX_COMMAND 0x62
250#define POWAR_EN 0x80000000
251#define POWAR_IO_READ 0x00080000
252#define POWAR_MEM_READ 0x00040000
253#define POWAR_IO_WRITE 0x00008000
254#define POWAR_MEM_WRITE 0x00004000
255#define POWAR_MEM_512M 0x0000001c
256#define POWAR_IO_1M 0x00000013
257
258#define PIWAR_EN 0x80000000
259#define PIWAR_PF 0x20000000
260#define PIWAR_LOCAL 0x00f00000
261#define PIWAR_READ_SNOOP 0x00050000
262#define PIWAR_WRITE_SNOOP 0x00005000
263#define PIWAR_MEM_2G 0x0000001e
264
mario.six@gdsys.cc5b59a352016-05-25 15:15:20 +0200265#ifndef CONFIG_MPC85XX_GPIO
Kumar Gala3d8d9132009-09-28 21:38:00 -0500266typedef struct ccsr_gpio {
267 u32 gpdir;
268 u32 gpodr;
269 u32 gpdat;
270 u32 gpier;
271 u32 gpimr;
272 u32 gpicr;
Bin Mengda047f52021-02-25 17:22:49 +0800273 u32 gpibe;
Kumar Gala3d8d9132009-09-28 21:38:00 -0500274} ccsr_gpio_t;
mario.six@gdsys.cc5b59a352016-05-25 15:15:20 +0200275#endif
Matthew McClintock31db9c32006-06-28 10:45:17 -0500276
Kumar Gala3d8d9132009-09-28 21:38:00 -0500277/* L2 Cache Registers */
wdenk9c53f402003-10-15 23:53:47 +0000278typedef struct ccsr_l2cache {
Kumar Gala3d8d9132009-09-28 21:38:00 -0500279 u32 l2ctl; /* L2 configuration 0 */
280 u8 res1[12];
281 u32 l2cewar0; /* L2 cache external write addr 0 */
282 u8 res2[4];
283 u32 l2cewcr0; /* L2 cache external write control 0 */
284 u8 res3[4];
285 u32 l2cewar1; /* L2 cache external write addr 1 */
286 u8 res4[4];
287 u32 l2cewcr1; /* L2 cache external write control 1 */
288 u8 res5[4];
289 u32 l2cewar2; /* L2 cache external write addr 2 */
290 u8 res6[4];
291 u32 l2cewcr2; /* L2 cache external write control 2 */
292 u8 res7[4];
293 u32 l2cewar3; /* L2 cache external write addr 3 */
294 u8 res8[4];
295 u32 l2cewcr3; /* L2 cache external write control 3 */
296 u8 res9[180];
297 u32 l2srbar0; /* L2 memory-mapped SRAM base addr 0 */
298 u8 res10[4];
299 u32 l2srbar1; /* L2 memory-mapped SRAM base addr 1 */
300 u8 res11[3316];
301 u32 l2errinjhi; /* L2 error injection mask high */
302 u32 l2errinjlo; /* L2 error injection mask low */
303 u32 l2errinjctl; /* L2 error injection tag/ECC control */
304 u8 res12[20];
305 u32 l2captdatahi; /* L2 error data high capture */
306 u32 l2captdatalo; /* L2 error data low capture */
307 u32 l2captecc; /* L2 error ECC capture */
308 u8 res13[20];
309 u32 l2errdet; /* L2 error detect */
310 u32 l2errdis; /* L2 error disable */
311 u32 l2errinten; /* L2 error interrupt enable */
312 u32 l2errattr; /* L2 error attributes capture */
313 u32 l2erraddr; /* L2 error addr capture */
314 u8 res14[4];
315 u32 l2errctl; /* L2 error control */
316 u8 res15[420];
wdenk9c53f402003-10-15 23:53:47 +0000317} ccsr_l2cache_t;
318
Mingkai Hud2088e02009-08-18 15:37:15 +0800319#define MPC85xx_L2CTL_L2E 0x80000000
320#define MPC85xx_L2CTL_L2SRAM_ENTIRE 0x00010000
321#define MPC85xx_L2ERRDIS_MBECC 0x00000008
322#define MPC85xx_L2ERRDIS_SBECC 0x00000004
323
Kumar Gala3d8d9132009-09-28 21:38:00 -0500324/* DMA Registers */
wdenk9c53f402003-10-15 23:53:47 +0000325typedef struct ccsr_dma {
Kumar Gala3d8d9132009-09-28 21:38:00 -0500326 u8 res1[256];
Peter Tyser4c82e722009-05-21 12:09:59 -0500327 struct fsl_dma dma[4];
Kumar Gala3d8d9132009-09-28 21:38:00 -0500328 u32 dgsr; /* DMA General Status */
329 u8 res2[11516];
wdenk9c53f402003-10-15 23:53:47 +0000330} ccsr_dma_t;
331
Kumar Gala3d8d9132009-09-28 21:38:00 -0500332/* tsec */
wdenk9c53f402003-10-15 23:53:47 +0000333typedef struct ccsr_tsec {
Kumar Gala3d8d9132009-09-28 21:38:00 -0500334 u8 res1[16];
335 u32 ievent; /* IRQ Event */
336 u32 imask; /* IRQ Mask */
337 u32 edis; /* Error Disabled */
338 u8 res2[4];
339 u32 ecntrl; /* Ethernet Control */
340 u32 minflr; /* Minimum Frame Len */
341 u32 ptv; /* Pause Time Value */
342 u32 dmactrl; /* DMA Control */
343 u32 tbipa; /* TBI PHY Addr */
344 u8 res3[88];
345 u32 fifo_tx_thr; /* FIFO transmit threshold */
346 u8 res4[8];
347 u32 fifo_tx_starve; /* FIFO transmit starve */
348 u32 fifo_tx_starve_shutoff; /* FIFO transmit starve shutoff */
349 u8 res5[96];
350 u32 tctrl; /* TX Control */
351 u32 tstat; /* TX Status */
352 u8 res6[4];
353 u32 tbdlen; /* TX Buffer Desc Data Len */
354 u8 res7[16];
355 u32 ctbptrh; /* Current TX Buffer Desc Ptr High */
356 u32 ctbptr; /* Current TX Buffer Desc Ptr */
357 u8 res8[88];
358 u32 tbptrh; /* TX Buffer Desc Ptr High */
359 u32 tbptr; /* TX Buffer Desc Ptr Low */
360 u8 res9[120];
361 u32 tbaseh; /* TX Desc Base Addr High */
362 u32 tbase; /* TX Desc Base Addr */
363 u8 res10[168];
364 u32 ostbd; /* Out-of-Sequence(OOS) TX Buffer Desc */
365 u32 ostbdp; /* OOS TX Data Buffer Ptr */
366 u32 os32tbdp; /* OOS 32 Bytes TX Data Buffer Ptr Low */
367 u32 os32iptrh; /* OOS 32 Bytes TX Insert Ptr High */
368 u32 os32iptrl; /* OOS 32 Bytes TX Insert Ptr Low */
369 u32 os32tbdr; /* OOS 32 Bytes TX Reserved */
370 u32 os32iil; /* OOS 32 Bytes TX Insert Idx/Len */
371 u8 res11[52];
372 u32 rctrl; /* RX Control */
373 u32 rstat; /* RX Status */
374 u8 res12[4];
375 u32 rbdlen; /* RxBD Data Len */
376 u8 res13[16];
377 u32 crbptrh; /* Current RX Buffer Desc Ptr High */
378 u32 crbptr; /* Current RX Buffer Desc Ptr */
379 u8 res14[24];
380 u32 mrblr; /* Maximum RX Buffer Len */
381 u32 mrblr2r3; /* Maximum RX Buffer Len R2R3 */
382 u8 res15[56];
383 u32 rbptrh; /* RX Buffer Desc Ptr High 0 */
384 u32 rbptr; /* RX Buffer Desc Ptr */
385 u32 rbptrh1; /* RX Buffer Desc Ptr High 1 */
386 u32 rbptrl1; /* RX Buffer Desc Ptr Low 1 */
387 u32 rbptrh2; /* RX Buffer Desc Ptr High 2 */
388 u32 rbptrl2; /* RX Buffer Desc Ptr Low 2 */
389 u32 rbptrh3; /* RX Buffer Desc Ptr High 3 */
390 u32 rbptrl3; /* RX Buffer Desc Ptr Low 3 */
391 u8 res16[96];
392 u32 rbaseh; /* RX Desc Base Addr High 0 */
393 u32 rbase; /* RX Desc Base Addr */
394 u32 rbaseh1; /* RX Desc Base Addr High 1 */
395 u32 rbasel1; /* RX Desc Base Addr Low 1 */
396 u32 rbaseh2; /* RX Desc Base Addr High 2 */
397 u32 rbasel2; /* RX Desc Base Addr Low 2 */
398 u32 rbaseh3; /* RX Desc Base Addr High 3 */
399 u32 rbasel3; /* RX Desc Base Addr Low 3 */
400 u8 res17[224];
401 u32 maccfg1; /* MAC Configuration 1 */
402 u32 maccfg2; /* MAC Configuration 2 */
403 u32 ipgifg; /* Inter Packet Gap/Inter Frame Gap */
404 u32 hafdup; /* Half Duplex */
405 u32 maxfrm; /* Maximum Frame Len */
406 u8 res18[12];
407 u32 miimcfg; /* MII Management Configuration */
408 u32 miimcom; /* MII Management Cmd */
409 u32 miimadd; /* MII Management Addr */
410 u32 miimcon; /* MII Management Control */
411 u32 miimstat; /* MII Management Status */
412 u32 miimind; /* MII Management Indicator */
413 u8 res19[4];
414 u32 ifstat; /* Interface Status */
415 u32 macstnaddr1; /* Station Addr Part 1 */
416 u32 macstnaddr2; /* Station Addr Part 2 */
417 u8 res20[312];
418 u32 tr64; /* TX & RX 64-byte Frame Counter */
419 u32 tr127; /* TX & RX 65-127 byte Frame Counter */
420 u32 tr255; /* TX & RX 128-255 byte Frame Counter */
421 u32 tr511; /* TX & RX 256-511 byte Frame Counter */
422 u32 tr1k; /* TX & RX 512-1023 byte Frame Counter */
423 u32 trmax; /* TX & RX 1024-1518 byte Frame Counter */
424 u32 trmgv; /* TX & RX 1519-1522 byte Good VLAN Frame */
425 u32 rbyt; /* RX Byte Counter */
426 u32 rpkt; /* RX Packet Counter */
427 u32 rfcs; /* RX FCS Error Counter */
428 u32 rmca; /* RX Multicast Packet Counter */
429 u32 rbca; /* RX Broadcast Packet Counter */
430 u32 rxcf; /* RX Control Frame Packet Counter */
431 u32 rxpf; /* RX Pause Frame Packet Counter */
432 u32 rxuo; /* RX Unknown OP Code Counter */
433 u32 raln; /* RX Alignment Error Counter */
434 u32 rflr; /* RX Frame Len Error Counter */
435 u32 rcde; /* RX Code Error Counter */
436 u32 rcse; /* RX Carrier Sense Error Counter */
437 u32 rund; /* RX Undersize Packet Counter */
438 u32 rovr; /* RX Oversize Packet Counter */
439 u32 rfrg; /* RX Fragments Counter */
440 u32 rjbr; /* RX Jabber Counter */
441 u32 rdrp; /* RX Drop Counter */
442 u32 tbyt; /* TX Byte Counter Counter */
443 u32 tpkt; /* TX Packet Counter */
444 u32 tmca; /* TX Multicast Packet Counter */
445 u32 tbca; /* TX Broadcast Packet Counter */
446 u32 txpf; /* TX Pause Control Frame Counter */
447 u32 tdfr; /* TX Deferral Packet Counter */
448 u32 tedf; /* TX Excessive Deferral Packet Counter */
449 u32 tscl; /* TX Single Collision Packet Counter */
450 u32 tmcl; /* TX Multiple Collision Packet Counter */
451 u32 tlcl; /* TX Late Collision Packet Counter */
452 u32 txcl; /* TX Excessive Collision Packet Counter */
453 u32 tncl; /* TX Total Collision Counter */
454 u8 res21[4];
455 u32 tdrp; /* TX Drop Frame Counter */
456 u32 tjbr; /* TX Jabber Frame Counter */
457 u32 tfcs; /* TX FCS Error Counter */
458 u32 txcf; /* TX Control Frame Counter */
459 u32 tovr; /* TX Oversize Frame Counter */
460 u32 tund; /* TX Undersize Frame Counter */
461 u32 tfrg; /* TX Fragments Frame Counter */
462 u32 car1; /* Carry One */
463 u32 car2; /* Carry Two */
464 u32 cam1; /* Carry Mask One */
465 u32 cam2; /* Carry Mask Two */
466 u8 res22[192];
467 u32 iaddr0; /* Indivdual addr 0 */
468 u32 iaddr1; /* Indivdual addr 1 */
469 u32 iaddr2; /* Indivdual addr 2 */
470 u32 iaddr3; /* Indivdual addr 3 */
471 u32 iaddr4; /* Indivdual addr 4 */
472 u32 iaddr5; /* Indivdual addr 5 */
473 u32 iaddr6; /* Indivdual addr 6 */
474 u32 iaddr7; /* Indivdual addr 7 */
475 u8 res23[96];
476 u32 gaddr0; /* Global addr 0 */
477 u32 gaddr1; /* Global addr 1 */
478 u32 gaddr2; /* Global addr 2 */
479 u32 gaddr3; /* Global addr 3 */
480 u32 gaddr4; /* Global addr 4 */
481 u32 gaddr5; /* Global addr 5 */
482 u32 gaddr6; /* Global addr 6 */
483 u32 gaddr7; /* Global addr 7 */
484 u8 res24[96];
485 u32 pmd0; /* Pattern Match Data */
486 u8 res25[4];
487 u32 pmask0; /* Pattern Mask */
488 u8 res26[4];
489 u32 pcntrl0; /* Pattern Match Control */
490 u8 res27[4];
491 u32 pattrb0; /* Pattern Match Attrs */
492 u32 pattrbeli0; /* Pattern Match Attrs Extract Len & Idx */
493 u32 pmd1; /* Pattern Match Data */
494 u8 res28[4];
495 u32 pmask1; /* Pattern Mask */
496 u8 res29[4];
497 u32 pcntrl1; /* Pattern Match Control */
498 u8 res30[4];
499 u32 pattrb1; /* Pattern Match Attrs */
500 u32 pattrbeli1; /* Pattern Match Attrs Extract Len & Idx */
501 u32 pmd2; /* Pattern Match Data */
502 u8 res31[4];
503 u32 pmask2; /* Pattern Mask */
504 u8 res32[4];
505 u32 pcntrl2; /* Pattern Match Control */
506 u8 res33[4];
507 u32 pattrb2; /* Pattern Match Attrs */
508 u32 pattrbeli2; /* Pattern Match Attrs Extract Len & Idx */
509 u32 pmd3; /* Pattern Match Data */
510 u8 res34[4];
511 u32 pmask3; /* Pattern Mask */
512 u8 res35[4];
513 u32 pcntrl3; /* Pattern Match Control */
514 u8 res36[4];
515 u32 pattrb3; /* Pattern Match Attrs */
516 u32 pattrbeli3; /* Pattern Match Attrs Extract Len & Idx */
517 u32 pmd4; /* Pattern Match Data */
518 u8 res37[4];
519 u32 pmask4; /* Pattern Mask */
520 u8 res38[4];
521 u32 pcntrl4; /* Pattern Match Control */
522 u8 res39[4];
523 u32 pattrb4; /* Pattern Match Attrs */
524 u32 pattrbeli4; /* Pattern Match Attrs Extract Len & Idx */
525 u32 pmd5; /* Pattern Match Data */
526 u8 res40[4];
527 u32 pmask5; /* Pattern Mask */
528 u8 res41[4];
529 u32 pcntrl5; /* Pattern Match Control */
530 u8 res42[4];
531 u32 pattrb5; /* Pattern Match Attrs */
532 u32 pattrbeli5; /* Pattern Match Attrs Extract Len & Idx */
533 u32 pmd6; /* Pattern Match Data */
534 u8 res43[4];
535 u32 pmask6; /* Pattern Mask */
536 u8 res44[4];
537 u32 pcntrl6; /* Pattern Match Control */
538 u8 res45[4];
539 u32 pattrb6; /* Pattern Match Attrs */
540 u32 pattrbeli6; /* Pattern Match Attrs Extract Len & Idx */
541 u32 pmd7; /* Pattern Match Data */
542 u8 res46[4];
543 u32 pmask7; /* Pattern Mask */
544 u8 res47[4];
545 u32 pcntrl7; /* Pattern Match Control */
546 u8 res48[4];
547 u32 pattrb7; /* Pattern Match Attrs */
548 u32 pattrbeli7; /* Pattern Match Attrs Extract Len & Idx */
549 u32 pmd8; /* Pattern Match Data */
550 u8 res49[4];
551 u32 pmask8; /* Pattern Mask */
552 u8 res50[4];
553 u32 pcntrl8; /* Pattern Match Control */
554 u8 res51[4];
555 u32 pattrb8; /* Pattern Match Attrs */
556 u32 pattrbeli8; /* Pattern Match Attrs Extract Len & Idx */
557 u32 pmd9; /* Pattern Match Data */
558 u8 res52[4];
559 u32 pmask9; /* Pattern Mask */
560 u8 res53[4];
561 u32 pcntrl9; /* Pattern Match Control */
562 u8 res54[4];
563 u32 pattrb9; /* Pattern Match Attrs */
564 u32 pattrbeli9; /* Pattern Match Attrs Extract Len & Idx */
565 u32 pmd10; /* Pattern Match Data */
566 u8 res55[4];
567 u32 pmask10; /* Pattern Mask */
568 u8 res56[4];
569 u32 pcntrl10; /* Pattern Match Control */
570 u8 res57[4];
571 u32 pattrb10; /* Pattern Match Attrs */
572 u32 pattrbeli10; /* Pattern Match Attrs Extract Len & Idx */
573 u32 pmd11; /* Pattern Match Data */
574 u8 res58[4];
575 u32 pmask11; /* Pattern Mask */
576 u8 res59[4];
577 u32 pcntrl11; /* Pattern Match Control */
578 u8 res60[4];
579 u32 pattrb11; /* Pattern Match Attrs */
580 u32 pattrbeli11; /* Pattern Match Attrs Extract Len & Idx */
581 u32 pmd12; /* Pattern Match Data */
582 u8 res61[4];
583 u32 pmask12; /* Pattern Mask */
584 u8 res62[4];
585 u32 pcntrl12; /* Pattern Match Control */
586 u8 res63[4];
587 u32 pattrb12; /* Pattern Match Attrs */
588 u32 pattrbeli12; /* Pattern Match Attrs Extract Len & Idx */
589 u32 pmd13; /* Pattern Match Data */
590 u8 res64[4];
591 u32 pmask13; /* Pattern Mask */
592 u8 res65[4];
593 u32 pcntrl13; /* Pattern Match Control */
594 u8 res66[4];
595 u32 pattrb13; /* Pattern Match Attrs */
596 u32 pattrbeli13; /* Pattern Match Attrs Extract Len & Idx */
597 u32 pmd14; /* Pattern Match Data */
598 u8 res67[4];
599 u32 pmask14; /* Pattern Mask */
600 u8 res68[4];
601 u32 pcntrl14; /* Pattern Match Control */
602 u8 res69[4];
603 u32 pattrb14; /* Pattern Match Attrs */
604 u32 pattrbeli14; /* Pattern Match Attrs Extract Len & Idx */
605 u32 pmd15; /* Pattern Match Data */
606 u8 res70[4];
607 u32 pmask15; /* Pattern Mask */
608 u8 res71[4];
609 u32 pcntrl15; /* Pattern Match Control */
610 u8 res72[4];
611 u32 pattrb15; /* Pattern Match Attrs */
612 u32 pattrbeli15; /* Pattern Match Attrs Extract Len & Idx */
613 u8 res73[248];
614 u32 attr; /* Attrs */
615 u32 attreli; /* Attrs Extract Len & Idx */
616 u8 res74[1024];
wdenk9c53f402003-10-15 23:53:47 +0000617} ccsr_tsec_t;
618
Kumar Gala3d8d9132009-09-28 21:38:00 -0500619/* PIC Registers */
wdenk9c53f402003-10-15 23:53:47 +0000620typedef struct ccsr_pic {
Kumar Gala3d8d9132009-09-28 21:38:00 -0500621 u8 res1[64];
622 u32 ipidr0; /* Interprocessor IRQ Dispatch 0 */
623 u8 res2[12];
624 u32 ipidr1; /* Interprocessor IRQ Dispatch 1 */
625 u8 res3[12];
626 u32 ipidr2; /* Interprocessor IRQ Dispatch 2 */
627 u8 res4[12];
628 u32 ipidr3; /* Interprocessor IRQ Dispatch 3 */
629 u8 res5[12];
630 u32 ctpr; /* Current Task Priority */
631 u8 res6[12];
632 u32 whoami; /* Who Am I */
633 u8 res7[12];
634 u32 iack; /* IRQ Acknowledge */
635 u8 res8[12];
636 u32 eoi; /* End Of IRQ */
637 u8 res9[3916];
638 u32 frr; /* Feature Reporting */
639 u8 res10[28];
640 u32 gcr; /* Global Configuration */
641#define MPC85xx_PICGCR_RST 0x80000000
642#define MPC85xx_PICGCR_M 0x20000000
643 u8 res11[92];
644 u32 vir; /* Vendor Identification */
645 u8 res12[12];
646 u32 pir; /* Processor Initialization */
647 u8 res13[12];
648 u32 ipivpr0; /* IPI Vector/Priority 0 */
649 u8 res14[12];
650 u32 ipivpr1; /* IPI Vector/Priority 1 */
651 u8 res15[12];
652 u32 ipivpr2; /* IPI Vector/Priority 2 */
653 u8 res16[12];
654 u32 ipivpr3; /* IPI Vector/Priority 3 */
655 u8 res17[12];
656 u32 svr; /* Spurious Vector */
657 u8 res18[12];
658 u32 tfrr; /* Timer Frequency Reporting */
659 u8 res19[12];
660 u32 gtccr0; /* Global Timer Current Count 0 */
661 u8 res20[12];
662 u32 gtbcr0; /* Global Timer Base Count 0 */
663 u8 res21[12];
664 u32 gtvpr0; /* Global Timer Vector/Priority 0 */
665 u8 res22[12];
666 u32 gtdr0; /* Global Timer Destination 0 */
667 u8 res23[12];
668 u32 gtccr1; /* Global Timer Current Count 1 */
669 u8 res24[12];
670 u32 gtbcr1; /* Global Timer Base Count 1 */
671 u8 res25[12];
672 u32 gtvpr1; /* Global Timer Vector/Priority 1 */
673 u8 res26[12];
674 u32 gtdr1; /* Global Timer Destination 1 */
675 u8 res27[12];
676 u32 gtccr2; /* Global Timer Current Count 2 */
677 u8 res28[12];
678 u32 gtbcr2; /* Global Timer Base Count 2 */
679 u8 res29[12];
680 u32 gtvpr2; /* Global Timer Vector/Priority 2 */
681 u8 res30[12];
682 u32 gtdr2; /* Global Timer Destination 2 */
683 u8 res31[12];
684 u32 gtccr3; /* Global Timer Current Count 3 */
685 u8 res32[12];
686 u32 gtbcr3; /* Global Timer Base Count 3 */
687 u8 res33[12];
688 u32 gtvpr3; /* Global Timer Vector/Priority 3 */
689 u8 res34[12];
690 u32 gtdr3; /* Global Timer Destination 3 */
691 u8 res35[268];
692 u32 tcr; /* Timer Control */
693 u8 res36[12];
694 u32 irqsr0; /* IRQ_OUT Summary 0 */
695 u8 res37[12];
696 u32 irqsr1; /* IRQ_OUT Summary 1 */
697 u8 res38[12];
698 u32 cisr0; /* Critical IRQ Summary 0 */
699 u8 res39[12];
700 u32 cisr1; /* Critical IRQ Summary 1 */
701 u8 res40[188];
702 u32 msgr0; /* Message 0 */
703 u8 res41[12];
704 u32 msgr1; /* Message 1 */
705 u8 res42[12];
706 u32 msgr2; /* Message 2 */
707 u8 res43[12];
708 u32 msgr3; /* Message 3 */
709 u8 res44[204];
710 u32 mer; /* Message Enable */
711 u8 res45[12];
712 u32 msr; /* Message Status */
713 u8 res46[60140];
714 u32 eivpr0; /* External IRQ Vector/Priority 0 */
715 u8 res47[12];
716 u32 eidr0; /* External IRQ Destination 0 */
717 u8 res48[12];
718 u32 eivpr1; /* External IRQ Vector/Priority 1 */
719 u8 res49[12];
720 u32 eidr1; /* External IRQ Destination 1 */
721 u8 res50[12];
722 u32 eivpr2; /* External IRQ Vector/Priority 2 */
723 u8 res51[12];
724 u32 eidr2; /* External IRQ Destination 2 */
725 u8 res52[12];
726 u32 eivpr3; /* External IRQ Vector/Priority 3 */
727 u8 res53[12];
728 u32 eidr3; /* External IRQ Destination 3 */
729 u8 res54[12];
730 u32 eivpr4; /* External IRQ Vector/Priority 4 */
731 u8 res55[12];
732 u32 eidr4; /* External IRQ Destination 4 */
733 u8 res56[12];
734 u32 eivpr5; /* External IRQ Vector/Priority 5 */
735 u8 res57[12];
736 u32 eidr5; /* External IRQ Destination 5 */
737 u8 res58[12];
738 u32 eivpr6; /* External IRQ Vector/Priority 6 */
739 u8 res59[12];
740 u32 eidr6; /* External IRQ Destination 6 */
741 u8 res60[12];
742 u32 eivpr7; /* External IRQ Vector/Priority 7 */
743 u8 res61[12];
744 u32 eidr7; /* External IRQ Destination 7 */
745 u8 res62[12];
746 u32 eivpr8; /* External IRQ Vector/Priority 8 */
747 u8 res63[12];
748 u32 eidr8; /* External IRQ Destination 8 */
749 u8 res64[12];
750 u32 eivpr9; /* External IRQ Vector/Priority 9 */
751 u8 res65[12];
752 u32 eidr9; /* External IRQ Destination 9 */
753 u8 res66[12];
754 u32 eivpr10; /* External IRQ Vector/Priority 10 */
755 u8 res67[12];
756 u32 eidr10; /* External IRQ Destination 10 */
757 u8 res68[12];
758 u32 eivpr11; /* External IRQ Vector/Priority 11 */
759 u8 res69[12];
760 u32 eidr11; /* External IRQ Destination 11 */
761 u8 res70[140];
762 u32 iivpr0; /* Internal IRQ Vector/Priority 0 */
763 u8 res71[12];
764 u32 iidr0; /* Internal IRQ Destination 0 */
765 u8 res72[12];
766 u32 iivpr1; /* Internal IRQ Vector/Priority 1 */
767 u8 res73[12];
768 u32 iidr1; /* Internal IRQ Destination 1 */
769 u8 res74[12];
770 u32 iivpr2; /* Internal IRQ Vector/Priority 2 */
771 u8 res75[12];
772 u32 iidr2; /* Internal IRQ Destination 2 */
773 u8 res76[12];
774 u32 iivpr3; /* Internal IRQ Vector/Priority 3 */
775 u8 res77[12];
776 u32 iidr3; /* Internal IRQ Destination 3 */
777 u8 res78[12];
778 u32 iivpr4; /* Internal IRQ Vector/Priority 4 */
779 u8 res79[12];
780 u32 iidr4; /* Internal IRQ Destination 4 */
781 u8 res80[12];
782 u32 iivpr5; /* Internal IRQ Vector/Priority 5 */
783 u8 res81[12];
784 u32 iidr5; /* Internal IRQ Destination 5 */
785 u8 res82[12];
786 u32 iivpr6; /* Internal IRQ Vector/Priority 6 */
787 u8 res83[12];
788 u32 iidr6; /* Internal IRQ Destination 6 */
789 u8 res84[12];
790 u32 iivpr7; /* Internal IRQ Vector/Priority 7 */
791 u8 res85[12];
792 u32 iidr7; /* Internal IRQ Destination 7 */
793 u8 res86[12];
794 u32 iivpr8; /* Internal IRQ Vector/Priority 8 */
795 u8 res87[12];
796 u32 iidr8; /* Internal IRQ Destination 8 */
797 u8 res88[12];
798 u32 iivpr9; /* Internal IRQ Vector/Priority 9 */
799 u8 res89[12];
800 u32 iidr9; /* Internal IRQ Destination 9 */
801 u8 res90[12];
802 u32 iivpr10; /* Internal IRQ Vector/Priority 10 */
803 u8 res91[12];
804 u32 iidr10; /* Internal IRQ Destination 10 */
805 u8 res92[12];
806 u32 iivpr11; /* Internal IRQ Vector/Priority 11 */
807 u8 res93[12];
808 u32 iidr11; /* Internal IRQ Destination 11 */
809 u8 res94[12];
810 u32 iivpr12; /* Internal IRQ Vector/Priority 12 */
811 u8 res95[12];
812 u32 iidr12; /* Internal IRQ Destination 12 */
813 u8 res96[12];
814 u32 iivpr13; /* Internal IRQ Vector/Priority 13 */
815 u8 res97[12];
816 u32 iidr13; /* Internal IRQ Destination 13 */
817 u8 res98[12];
818 u32 iivpr14; /* Internal IRQ Vector/Priority 14 */
819 u8 res99[12];
820 u32 iidr14; /* Internal IRQ Destination 14 */
821 u8 res100[12];
822 u32 iivpr15; /* Internal IRQ Vector/Priority 15 */
823 u8 res101[12];
824 u32 iidr15; /* Internal IRQ Destination 15 */
825 u8 res102[12];
826 u32 iivpr16; /* Internal IRQ Vector/Priority 16 */
827 u8 res103[12];
828 u32 iidr16; /* Internal IRQ Destination 16 */
829 u8 res104[12];
830 u32 iivpr17; /* Internal IRQ Vector/Priority 17 */
831 u8 res105[12];
832 u32 iidr17; /* Internal IRQ Destination 17 */
833 u8 res106[12];
834 u32 iivpr18; /* Internal IRQ Vector/Priority 18 */
835 u8 res107[12];
836 u32 iidr18; /* Internal IRQ Destination 18 */
837 u8 res108[12];
838 u32 iivpr19; /* Internal IRQ Vector/Priority 19 */
839 u8 res109[12];
840 u32 iidr19; /* Internal IRQ Destination 19 */
841 u8 res110[12];
842 u32 iivpr20; /* Internal IRQ Vector/Priority 20 */
843 u8 res111[12];
844 u32 iidr20; /* Internal IRQ Destination 20 */
845 u8 res112[12];
846 u32 iivpr21; /* Internal IRQ Vector/Priority 21 */
847 u8 res113[12];
848 u32 iidr21; /* Internal IRQ Destination 21 */
849 u8 res114[12];
850 u32 iivpr22; /* Internal IRQ Vector/Priority 22 */
851 u8 res115[12];
852 u32 iidr22; /* Internal IRQ Destination 22 */
853 u8 res116[12];
854 u32 iivpr23; /* Internal IRQ Vector/Priority 23 */
855 u8 res117[12];
856 u32 iidr23; /* Internal IRQ Destination 23 */
857 u8 res118[12];
858 u32 iivpr24; /* Internal IRQ Vector/Priority 24 */
859 u8 res119[12];
860 u32 iidr24; /* Internal IRQ Destination 24 */
861 u8 res120[12];
862 u32 iivpr25; /* Internal IRQ Vector/Priority 25 */
863 u8 res121[12];
864 u32 iidr25; /* Internal IRQ Destination 25 */
865 u8 res122[12];
866 u32 iivpr26; /* Internal IRQ Vector/Priority 26 */
867 u8 res123[12];
868 u32 iidr26; /* Internal IRQ Destination 26 */
869 u8 res124[12];
870 u32 iivpr27; /* Internal IRQ Vector/Priority 27 */
871 u8 res125[12];
872 u32 iidr27; /* Internal IRQ Destination 27 */
873 u8 res126[12];
874 u32 iivpr28; /* Internal IRQ Vector/Priority 28 */
875 u8 res127[12];
876 u32 iidr28; /* Internal IRQ Destination 28 */
877 u8 res128[12];
878 u32 iivpr29; /* Internal IRQ Vector/Priority 29 */
879 u8 res129[12];
880 u32 iidr29; /* Internal IRQ Destination 29 */
881 u8 res130[12];
882 u32 iivpr30; /* Internal IRQ Vector/Priority 30 */
883 u8 res131[12];
884 u32 iidr30; /* Internal IRQ Destination 30 */
885 u8 res132[12];
886 u32 iivpr31; /* Internal IRQ Vector/Priority 31 */
887 u8 res133[12];
888 u32 iidr31; /* Internal IRQ Destination 31 */
889 u8 res134[4108];
890 u32 mivpr0; /* Messaging IRQ Vector/Priority 0 */
891 u8 res135[12];
892 u32 midr0; /* Messaging IRQ Destination 0 */
893 u8 res136[12];
894 u32 mivpr1; /* Messaging IRQ Vector/Priority 1 */
895 u8 res137[12];
896 u32 midr1; /* Messaging IRQ Destination 1 */
897 u8 res138[12];
898 u32 mivpr2; /* Messaging IRQ Vector/Priority 2 */
899 u8 res139[12];
900 u32 midr2; /* Messaging IRQ Destination 2 */
901 u8 res140[12];
902 u32 mivpr3; /* Messaging IRQ Vector/Priority 3 */
903 u8 res141[12];
904 u32 midr3; /* Messaging IRQ Destination 3 */
905 u8 res142[59852];
906 u32 ipi0dr0; /* Processor 0 Interprocessor IRQ Dispatch 0 */
907 u8 res143[12];
908 u32 ipi0dr1; /* Processor 0 Interprocessor IRQ Dispatch 1 */
909 u8 res144[12];
910 u32 ipi0dr2; /* Processor 0 Interprocessor IRQ Dispatch 2 */
911 u8 res145[12];
912 u32 ipi0dr3; /* Processor 0 Interprocessor IRQ Dispatch 3 */
913 u8 res146[12];
914 u32 ctpr0; /* Current Task Priority for Processor 0 */
915 u8 res147[12];
916 u32 whoami0; /* Who Am I for Processor 0 */
917 u8 res148[12];
918 u32 iack0; /* IRQ Acknowledge for Processor 0 */
919 u8 res149[12];
920 u32 eoi0; /* End Of IRQ for Processor 0 */
921 u8 res150[130892];
wdenk9c53f402003-10-15 23:53:47 +0000922} ccsr_pic_t;
923
Liu Gang78deaa12012-03-08 00:33:14 +0000924#ifdef CONFIG_SYS_SRIO
925/* Architectural regsiters */
926struct rio_arch {
927 u32 didcar; /* Device Identity CAR */
928 u32 dicar; /* Device Information CAR */
929 u32 aidcar; /* Assembly Identity CAR */
930 u32 aicar; /* Assembly Information CAR */
931 u32 pefcar; /* Processing Element Features CAR */
932 u8 res0[4];
933 u32 socar; /* Source Operations CAR */
934 u32 docar; /* Destination Operations CAR */
Kumar Gala3d8d9132009-09-28 21:38:00 -0500935 u8 res1[32];
Liu Gang78deaa12012-03-08 00:33:14 +0000936 u32 mcsr; /* Mailbox CSR */
937 u32 pwdcsr; /* Port-Write and Doorbell CSR */
Kumar Gala3d8d9132009-09-28 21:38:00 -0500938 u8 res2[4];
939 u32 pellccsr; /* Processing Element Logic Layer CCSR */
940 u8 res3[12];
Liu Gang78deaa12012-03-08 00:33:14 +0000941 u32 lcsbacsr; /* Local Configuration Space BACSR */
942 u32 bdidcsr; /* Base Device ID CSR */
Kumar Gala3d8d9132009-09-28 21:38:00 -0500943 u8 res4[4];
Liu Gang78deaa12012-03-08 00:33:14 +0000944 u32 hbdidlcsr; /* Host Base Device ID Lock CSR */
945 u32 ctcsr; /* Component Tag CSR */
946};
947
948/* Extended Features Space: 1x/4x LP-Serial Port registers */
949struct rio_lp_serial_port {
950 u32 plmreqcsr; /* Port Link Maintenance Request CSR */
951 u32 plmrespcsr; /* Port Link Maintenance Response CS */
952 u32 plascsr; /* Port Local Ackid Status CSR */
953 u8 res0[12];
954 u32 pescsr; /* Port Error and Status CSR */
955 u32 pccsr; /* Port Control CSR */
956};
957
958/* Extended Features Space: 1x/4x LP-Serial registers */
959struct rio_lp_serial {
960 u32 pmbh0csr; /* Port Maintenance Block Header 0 CSR */
961 u8 res0[28];
962 u32 pltoccsr; /* Port Link Time-out CCSR */
963 u32 prtoccsr; /* Port Response Time-out CCSR */
964 u8 res1[20];
965 u32 pgccsr; /* Port General CSR */
966 struct rio_lp_serial_port port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
967};
968
969/* Logical error reporting registers */
970struct rio_logical_err {
971 u32 erbh; /* Error Reporting Block Header Register */
972 u8 res0[4];
973 u32 ltledcsr; /* Logical/Transport layer error DCSR */
974 u32 ltleecsr; /* Logical/Transport layer error ECSR */
975 u8 res1[4];
976 u32 ltlaccsr; /* Logical/Transport layer ACCSR */
977 u32 ltldidccsr; /* Logical/Transport layer DID CCSR */
978 u32 ltlcccsr; /* Logical/Transport layer control CCSR */
979};
980
981/* Physical error reporting port registers */
982struct rio_phys_err_port {
983 u32 edcsr; /* Port error detect CSR */
984 u32 erecsr; /* Port error rate enable CSR */
985 u32 ecacsr; /* Port error capture attributes CSR */
986 u32 pcseccsr0; /* Port packet/control symbol ECCSR 0 */
987 u32 peccsr[3]; /* Port error capture CSR */
988 u8 res0[12];
989 u32 ercsr; /* Port error rate CSR */
990 u32 ertcsr; /* Port error rate threshold CSR */
991 u8 res1[16];
992};
993
994/* Physical error reporting registers */
995struct rio_phys_err {
996 struct rio_phys_err_port port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
997};
998
999/* Implementation Space: General Port-Common */
1000struct rio_impl_common {
1001 u8 res0[4];
1002 u32 llcr; /* Logical Layer Configuration Register */
1003 u8 res1[8];
1004 u32 epwisr; /* Error / Port-Write Interrupt SR */
1005 u8 res2[12];
1006 u32 lretcr; /* Logical Retry Error Threshold CR */
1007 u8 res3[92];
1008 u32 pretcr; /* Physical Retry Erorr Threshold CR */
1009 u8 res4[124];
1010};
1011
1012/* Implementation Space: Port Specific */
1013struct rio_impl_port_spec {
1014 u32 adidcsr; /* Port Alt. Device ID CSR */
1015 u8 res0[28];
1016 u32 ptaacr; /* Port Pass-Through/Accept-All CR */
1017 u32 lopttlcr;
1018 u8 res1[8];
1019 u32 iecsr; /* Port Implementation Error CSR */
1020 u8 res2[12];
1021 u32 pcr; /* Port Phsyical Configuration Register */
1022 u8 res3[20];
1023 u32 slcsr; /* Port Serial Link CSR */
1024 u8 res4[4];
1025 u32 sleicr; /* Port Serial Link Error Injection */
1026 u32 a0txcr; /* Port Arbitration 0 Tx CR */
1027 u32 a1txcr; /* Port Arbitration 1 Tx CR */
1028 u32 a2txcr; /* Port Arbitration 2 Tx CR */
1029 u32 mreqtxbacr[3]; /* Port Request Tx Buffer ACR */
1030 u32 mrspfctxbacr; /* Port Response/Flow Control Tx Buffer ACR */
1031};
1032
1033/* Implementation Space: register */
1034struct rio_implement {
1035 struct rio_impl_common com;
1036 struct rio_impl_port_spec port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
1037};
1038
1039/* Revision Control Register */
1040struct rio_rev_ctrl {
1041 u32 ipbrr[2]; /* IP Block Revision Register */
1042};
1043
1044struct rio_atmu_row {
1045 u32 rowtar; /* RapidIO Outbound Window TAR */
1046 u32 rowtear; /* RapidIO Outbound Window TEAR */
1047 u32 rowbar;
1048 u8 res0[4];
1049 u32 rowar; /* RapidIO Outbound Attributes Register */
1050 u32 rowsr[3]; /* Port RapidIO outbound window segment register */
1051};
1052
1053struct rio_atmu_riw {
1054 u32 riwtar; /* RapidIO Inbound Window Translation AR */
1055 u8 res0[4];
1056 u32 riwbar; /* RapidIO Inbound Window Base AR */
1057 u8 res1[4];
1058 u32 riwar; /* RapidIO Inbound Attributes Register */
1059 u8 res2[12];
1060};
1061
1062/* ATMU window registers */
1063struct rio_atmu_win {
1064 struct rio_atmu_row outbw[CONFIG_SYS_FSL_SRIO_OB_WIN_NUM];
1065 u8 res0[64];
1066 struct rio_atmu_riw inbw[CONFIG_SYS_FSL_SRIO_IB_WIN_NUM];
1067};
1068
1069struct rio_atmu {
1070 struct rio_atmu_win port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
1071};
1072
1073#ifdef CONFIG_SYS_FSL_RMU
1074struct rio_msg {
1075 u32 omr; /* Outbound Mode Register */
1076 u32 osr; /* Outbound Status Register */
1077 u32 eodqdpar; /* Extended Outbound DQ DPAR */
1078 u32 odqdpar; /* Outbound Descriptor Queue DPAR */
1079 u32 eosar; /* Extended Outbound Unit Source AR */
1080 u32 osar; /* Outbound Unit Source AR */
1081 u32 odpr; /* Outbound Destination Port Register */
1082 u32 odatr; /* Outbound Destination Attributes Register */
1083 u32 odcr; /* Outbound Doubleword Count Register */
1084 u32 eodqepar; /* Extended Outbound DQ EPAR */
1085 u32 odqepar; /* Outbound Descriptor Queue EPAR */
1086 u32 oretr; /* Outbound Retry Error Threshold Register */
1087 u32 omgr; /* Outbound Multicast Group Register */
1088 u32 omlr; /* Outbound Multicast List Register */
1089 u8 res0[40];
1090 u32 imr; /* Outbound Mode Register */
1091 u32 isr; /* Inbound Status Register */
1092 u32 eidqdpar; /* Extended Inbound Descriptor Queue DPAR */
1093 u32 idqdpar; /* Inbound Descriptor Queue DPAR */
1094 u32 eifqepar; /* Extended Inbound Frame Queue EPAR */
1095 u32 ifqepar; /* Inbound Frame Queue EPAR */
1096 u32 imirir; /* Inbound Maximum Interrutp RIR */
1097 u8 res1[4];
1098 u32 eihqepar; /* Extended inbound message header queue EPAR */
1099 u32 ihqepar; /* Inbound message header queue EPAR */
1100 u8 res2[120];
1101};
1102
1103struct rio_dbell {
1104 u32 odmr; /* Outbound Doorbell Mode Register */
1105 u32 odsr; /* Outbound Doorbell Status Register */
1106 u8 res0[16];
1107 u32 oddpr; /* Outbound Doorbell Destination Port */
1108 u32 oddatr; /* Outbound Doorbell Destination AR */
1109 u8 res1[12];
1110 u32 oddretr; /* Outbound Doorbell Retry Threshold CR */
1111 u8 res2[48];
1112 u32 idmr; /* Inbound Doorbell Mode Register */
1113 u32 idsr; /* Inbound Doorbell Status Register */
1114 u32 iedqdpar; /* Extended Inbound Doorbell Queue DPAR */
1115 u32 iqdpar; /* Inbound Doorbell Queue DPAR */
1116 u32 iedqepar; /* Extended Inbound Doorbell Queue EPAR */
1117 u32 idqepar; /* Inbound Doorbell Queue EPAR */
1118 u32 idmirir; /* Inbound Doorbell Max Interrupt RIR */
1119};
1120
1121struct rio_pw {
1122 u32 pwmr; /* Port-Write Mode Register */
1123 u32 pwsr; /* Port-Write Status Register */
1124 u32 epwqbar; /* Extended Port-Write Queue BAR */
1125 u32 pwqbar; /* Port-Write Queue Base Address Register */
1126};
1127#endif
1128
Liu Gang1d5284b2013-06-25 18:12:12 +08001129#ifdef CONFIG_SYS_FSL_SRIO_LIODN
1130struct rio_liodn {
1131 u32 plbr;
1132 u8 res0[28];
1133 u32 plaor;
1134 u8 res1[12];
1135 u32 pludr;
1136 u32 plldr;
1137 u8 res2[456];
1138};
1139#endif
1140
Liu Gang78deaa12012-03-08 00:33:14 +00001141/* RapidIO Registers */
1142struct ccsr_rio {
1143 struct rio_arch arch;
1144 u8 res0[144];
1145 struct rio_lp_serial lp_serial;
1146 u8 res1[1152];
1147 struct rio_logical_err logical_err;
1148 u8 res2[32];
1149 struct rio_phys_err phys_err;
1150 u8 res3[63808];
1151 struct rio_implement impl;
1152 u8 res4[2552];
1153 struct rio_rev_ctrl rev;
1154 struct rio_atmu atmu;
1155#ifdef CONFIG_SYS_FSL_RMU
1156 u8 res5[8192];
1157 struct rio_msg msg[CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM];
1158 u8 res6[512];
1159 struct rio_dbell dbell;
1160 u8 res7[100];
1161 struct rio_pw pw;
1162#endif
Liu Gang1d5284b2013-06-25 18:12:12 +08001163#ifdef CONFIG_SYS_FSL_SRIO_LIODN
1164 u8 res5[8192];
1165 struct rio_liodn liodn[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
1166#endif
Liu Gang78deaa12012-03-08 00:33:14 +00001167};
1168#endif
wdenk9c53f402003-10-15 23:53:47 +00001169
Kumar Gala3d8d9132009-09-28 21:38:00 -05001170/* Quick Engine Block Pin Muxing Registers */
Haiying Wangc4fc8832007-06-19 14:18:34 -04001171typedef struct par_io {
Kumar Gala3d8d9132009-09-28 21:38:00 -05001172 u32 cpodr;
1173 u32 cpdat;
1174 u32 cpdir1;
1175 u32 cpdir2;
1176 u32 cppar1;
1177 u32 cppar2;
1178 u8 res[8];
1179} par_io_t;
Haiying Wangc4fc8832007-06-19 14:18:34 -04001180
Becky Bruce475c2f92009-11-17 21:10:21 -06001181#ifdef CONFIG_SYS_FSL_CPC
1182/*
1183 * Define a single offset that is the start of all the CPC register
1184 * blocks - if there is more than one CPC, we expect these to be
1185 * contiguous 4k regions
1186 */
1187
1188typedef struct cpc_corenet {
Wolfgang Denk62fb2b42021-09-27 17:42:39 +02001189 u32 cpccsr0; /* Config/status reg */
Becky Bruce475c2f92009-11-17 21:10:21 -06001190 u32 res1;
1191 u32 cpccfg0; /* Configuration register */
1192 u32 res2;
1193 u32 cpcewcr0; /* External Write reg 0 */
1194 u32 cpcewabr0; /* External write base reg 0 */
1195 u32 res3[2];
1196 u32 cpcewcr1; /* External Write reg 1 */
1197 u32 cpcewabr1; /* External write base reg 1 */
1198 u32 res4[54];
1199 u32 cpcsrcr1; /* SRAM control reg 1 */
1200 u32 cpcsrcr0; /* SRAM control reg 0 */
1201 u32 res5[62];
1202 struct {
1203 u32 id; /* partition ID */
1204 u32 res;
1205 u32 alloc; /* partition allocation */
1206 u32 way; /* partition way */
1207 } partition_regs[16];
1208 u32 res6[704];
1209 u32 cpcerrinjhi; /* Error injection high */
1210 u32 cpcerrinjlo; /* Error injection lo */
1211 u32 cpcerrinjctl; /* Error injection control */
1212 u32 res7[5];
1213 u32 cpccaptdatahi; /* capture data high */
1214 u32 cpccaptdatalo; /* capture data low */
1215 u32 cpcaptecc; /* capture ECC */
1216 u32 res8[5];
1217 u32 cpcerrdet; /* error detect */
1218 u32 cpcerrdis; /* error disable */
1219 u32 cpcerrinten; /* errir interrupt enable */
1220 u32 cpcerrattr; /* error attribute */
1221 u32 cpcerreaddr; /* error extended address */
1222 u32 cpcerraddr; /* error address */
1223 u32 cpcerrctl; /* error control */
Kumar Galaa9d1f9c2010-09-23 14:50:37 -05001224 u32 res9[41]; /* pad out to 4k */
1225 u32 cpchdbcr0; /* hardware debug control register 0 */
1226 u32 res10[63]; /* pad out to 4k */
Becky Bruce475c2f92009-11-17 21:10:21 -06001227} cpc_corenet_t;
1228
1229#define CPC_CSR0_CE 0x80000000 /* Cache Enable */
1230#define CPC_CSR0_PE 0x40000000 /* Enable ECC */
1231#define CPC_CSR0_FI 0x00200000 /* Cache Flash Invalidate */
1232#define CPC_CSR0_WT 0x00080000 /* Write-through mode */
1233#define CPC_CSR0_FL 0x00000800 /* Hardware cache flush */
1234#define CPC_CSR0_LFC 0x00000400 /* Cache Lock Flash Clear */
1235#define CPC_CFG0_SZ_MASK 0x00003fff
1236#define CPC_CFG0_SZ_K(x) ((x & CPC_CFG0_SZ_MASK) << 6)
1237#define CPC_CFG0_NUM_WAYS(x) (((x >> 14) & 0x1f) + 1)
1238#define CPC_CFG0_LINE_SZ(x) ((((x >> 23) & 0x3) + 1) * 32)
1239#define CPC_SRCR1_SRBARU_MASK 0x0000ffff
1240#define CPC_SRCR1_SRBARU(x) (((unsigned long long)x >> 32) \
1241 & CPC_SRCR1_SRBARU_MASK)
1242#define CPC_SRCR0_SRBARL_MASK 0xffff8000
1243#define CPC_SRCR0_SRBARL(x) (x & CPC_SRCR0_SRBARL_MASK)
1244#define CPC_SRCR0_INTLVEN 0x00000100
1245#define CPC_SRCR0_SRAMSZ_1_WAY 0x00000000
1246#define CPC_SRCR0_SRAMSZ_2_WAY 0x00000002
1247#define CPC_SRCR0_SRAMSZ_4_WAY 0x00000004
1248#define CPC_SRCR0_SRAMSZ_8_WAY 0x00000006
1249#define CPC_SRCR0_SRAMSZ_16_WAY 0x00000008
1250#define CPC_SRCR0_SRAMSZ_32_WAY 0x0000000a
1251#define CPC_SRCR0_SRAMEN 0x00000001
Wolfgang Denk62fb2b42021-09-27 17:42:39 +02001252#define CPC_ERRDIS_TMHITDIS 0x00000080 /* multi-way hit disable */
Kumar Galaa9d1f9c2010-09-23 14:50:37 -05001253#define CPC_HDBCR0_CDQ_SPEC_DIS 0x08000000
Kumar Gala9780b592011-01-13 01:54:01 -06001254#define CPC_HDBCR0_TAG_ECC_SCRUB_DIS 0x01000000
Kumar Gala887c0e12011-01-13 01:56:18 -06001255#define CPC_HDBCR0_DATA_ECC_SCRUB_DIS 0x00400000
York Suna3e6fd82016-08-01 09:00:13 -07001256#define CPC_HDBCR0_SPLRU_LEVEL_EN 0x001e0000
Becky Bruce475c2f92009-11-17 21:10:21 -06001257#endif /* CONFIG_SYS_FSL_CPC */
1258
Kumar Gala3d8d9132009-09-28 21:38:00 -05001259/* Global Utilities Block */
Kumar Galad5740162009-09-16 09:43:12 -05001260#ifdef CONFIG_FSL_CORENET
1261typedef struct ccsr_gur {
York Sun76c630c2013-03-25 07:33:12 +00001262 u32 porsr1; /* POR status 1 */
1263 u32 porsr2; /* POR status 2 */
vijay raid84fd502014-04-15 11:34:12 +05301264#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
1265#define FSL_DCFG_PORSR1_SYSCLK_SHIFT 15
1266#define FSL_DCFG_PORSR1_SYSCLK_MASK 0x1
1267#define FSL_DCFG_PORSR1_SYSCLK_SINGLE_ENDED 0x1
1268#define FSL_DCFG_PORSR1_SYSCLK_DIFF 0x0
1269#endif
York Sun76c630c2013-03-25 07:33:12 +00001270 u8 res_008[0x20-0x8];
Kumar Gala3d8d9132009-09-28 21:38:00 -05001271 u32 gpporcr1; /* General-purpose POR configuration */
York Sun76c630c2013-03-25 07:33:12 +00001272 u32 gpporcr2; /* General-purpose POR configuration 2 */
1273 u32 dcfg_fusesr; /* Fuse status register */
1274#define FSL_CORENET_DCFG_FUSESR_VID_SHIFT 25
1275#define FSL_CORENET_DCFG_FUSESR_VID_MASK 0x1F
1276#define FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT 20
1277#define FSL_CORENET_DCFG_FUSESR_ALTVID_MASK 0x1F
1278 u8 res_02c[0x70-0x2c];
Kumar Gala3d8d9132009-09-28 21:38:00 -05001279 u32 devdisr; /* Device disable control */
York Sun9941a222012-10-08 07:44:19 +00001280 u32 devdisr2; /* Device disable control 2 */
1281 u32 devdisr3; /* Device disable control 3 */
1282 u32 devdisr4; /* Device disable control 4 */
1283#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
1284 u32 devdisr5; /* Device disable control 5 */
1285#define FSL_CORENET_DEVDISR_PBL 0x80000000
1286#define FSL_CORENET_DEVDISR_PMAN 0x40000000
1287#define FSL_CORENET_DEVDISR_ESDHC 0x20000000
1288#define FSL_CORENET_DEVDISR_DMA1 0x00800000
1289#define FSL_CORENET_DEVDISR_DMA2 0x00400000
1290#define FSL_CORENET_DEVDISR_USB1 0x00080000
1291#define FSL_CORENET_DEVDISR_USB2 0x00040000
1292#define FSL_CORENET_DEVDISR_SATA1 0x00008000
1293#define FSL_CORENET_DEVDISR_SATA2 0x00004000
1294#define FSL_CORENET_DEVDISR_PME 0x00000800
1295#define FSL_CORENET_DEVDISR_SEC 0x00000200
1296#define FSL_CORENET_DEVDISR_RMU 0x00000080
1297#define FSL_CORENET_DEVDISR_DCE 0x00000040
1298#define FSL_CORENET_DEVDISR2_DTSEC1_1 0x80000000
1299#define FSL_CORENET_DEVDISR2_DTSEC1_2 0x40000000
1300#define FSL_CORENET_DEVDISR2_DTSEC1_3 0x20000000
1301#define FSL_CORENET_DEVDISR2_DTSEC1_4 0x10000000
1302#define FSL_CORENET_DEVDISR2_DTSEC1_5 0x08000000
1303#define FSL_CORENET_DEVDISR2_DTSEC1_6 0x04000000
1304#define FSL_CORENET_DEVDISR2_DTSEC1_9 0x00800000
1305#define FSL_CORENET_DEVDISR2_DTSEC1_10 0x00400000
Shengzhou Liua1ccdff2014-11-24 17:11:57 +08001306#ifdef CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
1307#define FSL_CORENET_DEVDISR2_10GEC1_1 0x80000000
1308#define FSL_CORENET_DEVDISR2_10GEC1_2 0x40000000
1309#else
York Sun9941a222012-10-08 07:44:19 +00001310#define FSL_CORENET_DEVDISR2_10GEC1_1 0x00800000
1311#define FSL_CORENET_DEVDISR2_10GEC1_2 0x00400000
Shengzhou Liu4227e492013-11-22 17:39:09 +08001312#define FSL_CORENET_DEVDISR2_10GEC1_3 0x80000000
1313#define FSL_CORENET_DEVDISR2_10GEC1_4 0x40000000
Shengzhou Liua1ccdff2014-11-24 17:11:57 +08001314#endif
York Sun9941a222012-10-08 07:44:19 +00001315#define FSL_CORENET_DEVDISR2_DTSEC2_1 0x00080000
1316#define FSL_CORENET_DEVDISR2_DTSEC2_2 0x00040000
1317#define FSL_CORENET_DEVDISR2_DTSEC2_3 0x00020000
1318#define FSL_CORENET_DEVDISR2_DTSEC2_4 0x00010000
1319#define FSL_CORENET_DEVDISR2_DTSEC2_5 0x00008000
1320#define FSL_CORENET_DEVDISR2_DTSEC2_6 0x00004000
1321#define FSL_CORENET_DEVDISR2_DTSEC2_9 0x00000800
1322#define FSL_CORENET_DEVDISR2_DTSEC2_10 0x00000400
1323#define FSL_CORENET_DEVDISR2_10GEC2_1 0x00000800
1324#define FSL_CORENET_DEVDISR2_10GEC2_2 0x00000400
1325#define FSL_CORENET_DEVDISR2_FM1 0x00000080
1326#define FSL_CORENET_DEVDISR2_FM2 0x00000040
York Sunbcf7b3d2012-10-08 07:44:20 +00001327#define FSL_CORENET_DEVDISR2_CPRI 0x00000008
York Sun9941a222012-10-08 07:44:19 +00001328#define FSL_CORENET_DEVDISR3_PCIE1 0x80000000
1329#define FSL_CORENET_DEVDISR3_PCIE2 0x40000000
1330#define FSL_CORENET_DEVDISR3_PCIE3 0x20000000
1331#define FSL_CORENET_DEVDISR3_PCIE4 0x10000000
1332#define FSL_CORENET_DEVDISR3_SRIO1 0x08000000
1333#define FSL_CORENET_DEVDISR3_SRIO2 0x04000000
1334#define FSL_CORENET_DEVDISR3_QMAN 0x00080000
1335#define FSL_CORENET_DEVDISR3_BMAN 0x00040000
1336#define FSL_CORENET_DEVDISR3_LA1 0x00008000
York Sunbcf7b3d2012-10-08 07:44:20 +00001337#define FSL_CORENET_DEVDISR3_MAPLE1 0x00000800
1338#define FSL_CORENET_DEVDISR3_MAPLE2 0x00000400
1339#define FSL_CORENET_DEVDISR3_MAPLE3 0x00000200
York Sun9941a222012-10-08 07:44:19 +00001340#define FSL_CORENET_DEVDISR4_I2C1 0x80000000
1341#define FSL_CORENET_DEVDISR4_I2C2 0x40000000
1342#define FSL_CORENET_DEVDISR4_DUART1 0x20000000
1343#define FSL_CORENET_DEVDISR4_DUART2 0x10000000
1344#define FSL_CORENET_DEVDISR4_ESPI 0x08000000
1345#define FSL_CORENET_DEVDISR5_DDR1 0x80000000
1346#define FSL_CORENET_DEVDISR5_DDR2 0x40000000
1347#define FSL_CORENET_DEVDISR5_DDR3 0x20000000
1348#define FSL_CORENET_DEVDISR5_CPC1 0x08000000
1349#define FSL_CORENET_DEVDISR5_CPC2 0x04000000
1350#define FSL_CORENET_DEVDISR5_CPC3 0x02000000
1351#define FSL_CORENET_DEVDISR5_IFC 0x00800000
1352#define FSL_CORENET_DEVDISR5_GPIO 0x00400000
1353#define FSL_CORENET_DEVDISR5_DBG 0x00200000
1354#define FSL_CORENET_DEVDISR5_NAL 0x00100000
York Sunbcf7b3d2012-10-08 07:44:20 +00001355#define FSL_CORENET_DEVDISR5_TIMERS 0x00020000
York Sun9941a222012-10-08 07:44:19 +00001356#define FSL_CORENET_NUM_DEVDISR 5
1357#else
Kumar Galad5740162009-09-16 09:43:12 -05001358#define FSL_CORENET_DEVDISR_PCIE1 0x80000000
1359#define FSL_CORENET_DEVDISR_PCIE2 0x40000000
1360#define FSL_CORENET_DEVDISR_PCIE3 0x20000000
Kumar Gala74e78b62010-04-28 04:02:21 -05001361#define FSL_CORENET_DEVDISR_PCIE4 0x10000000
Kumar Galad5740162009-09-16 09:43:12 -05001362#define FSL_CORENET_DEVDISR_RMU 0x08000000
1363#define FSL_CORENET_DEVDISR_SRIO1 0x04000000
1364#define FSL_CORENET_DEVDISR_SRIO2 0x02000000
1365#define FSL_CORENET_DEVDISR_DMA1 0x00400000
1366#define FSL_CORENET_DEVDISR_DMA2 0x00200000
1367#define FSL_CORENET_DEVDISR_DDR1 0x00100000
1368#define FSL_CORENET_DEVDISR_DDR2 0x00080000
1369#define FSL_CORENET_DEVDISR_DBG 0x00010000
1370#define FSL_CORENET_DEVDISR_NAL 0x00008000
Kumar Gala74e78b62010-04-28 04:02:21 -05001371#define FSL_CORENET_DEVDISR_SATA1 0x00004000
1372#define FSL_CORENET_DEVDISR_SATA2 0x00002000
Kumar Galad5740162009-09-16 09:43:12 -05001373#define FSL_CORENET_DEVDISR_ELBC 0x00001000
1374#define FSL_CORENET_DEVDISR_USB1 0x00000800
1375#define FSL_CORENET_DEVDISR_USB2 0x00000400
1376#define FSL_CORENET_DEVDISR_ESDHC 0x00000100
1377#define FSL_CORENET_DEVDISR_GPIO 0x00000080
1378#define FSL_CORENET_DEVDISR_ESPI 0x00000040
1379#define FSL_CORENET_DEVDISR_I2C1 0x00000020
1380#define FSL_CORENET_DEVDISR_I2C2 0x00000010
1381#define FSL_CORENET_DEVDISR_DUART1 0x00000002
1382#define FSL_CORENET_DEVDISR_DUART2 0x00000001
Kumar Gala13d1fe12010-04-07 10:39:46 -05001383#define FSL_CORENET_DEVDISR2_PME 0x80000000
1384#define FSL_CORENET_DEVDISR2_SEC 0x40000000
1385#define FSL_CORENET_DEVDISR2_QMBM 0x08000000
1386#define FSL_CORENET_DEVDISR2_FM1 0x02000000
1387#define FSL_CORENET_DEVDISR2_10GEC1 0x01000000
1388#define FSL_CORENET_DEVDISR2_DTSEC1_1 0x00800000
1389#define FSL_CORENET_DEVDISR2_DTSEC1_2 0x00400000
1390#define FSL_CORENET_DEVDISR2_DTSEC1_3 0x00200000
1391#define FSL_CORENET_DEVDISR2_DTSEC1_4 0x00100000
Kumar Gala74e78b62010-04-28 04:02:21 -05001392#define FSL_CORENET_DEVDISR2_DTSEC1_5 0x00080000
Kumar Gala13d1fe12010-04-07 10:39:46 -05001393#define FSL_CORENET_DEVDISR2_FM2 0x00020000
1394#define FSL_CORENET_DEVDISR2_10GEC2 0x00010000
1395#define FSL_CORENET_DEVDISR2_DTSEC2_1 0x00008000
1396#define FSL_CORENET_DEVDISR2_DTSEC2_2 0x00004000
1397#define FSL_CORENET_DEVDISR2_DTSEC2_3 0x00002000
1398#define FSL_CORENET_DEVDISR2_DTSEC2_4 0x00001000
Timur Tabi7920fb12012-08-14 06:47:21 +00001399#define FSL_CORENET_DEVDISR2_DTSEC2_5 0x00000800
Kumar Gala74e78b62010-04-28 04:02:21 -05001400#define FSL_CORENET_NUM_DEVDISR 2
Kumar Gala3d8d9132009-09-28 21:38:00 -05001401 u32 powmgtcsr; /* Power management status & control */
York Sun9941a222012-10-08 07:44:19 +00001402#endif
Kumar Galad5740162009-09-16 09:43:12 -05001403 u8 res8[12];
Kumar Gala3d8d9132009-09-28 21:38:00 -05001404 u32 coredisru; /* uppper portion for support of 64 cores */
1405 u32 coredisrl; /* lower portion for support of 64 cores */
Kumar Galad5740162009-09-16 09:43:12 -05001406 u8 res9[8];
Kumar Gala3d8d9132009-09-28 21:38:00 -05001407 u32 pvr; /* Processor version */
1408 u32 svr; /* System version */
Kumar Galad5740162009-09-16 09:43:12 -05001409 u8 res10[8];
Kumar Gala3d8d9132009-09-28 21:38:00 -05001410 u32 rstcr; /* Reset control */
1411 u32 rstrqpblsr; /* Reset request preboot loader status */
Kumar Galad5740162009-09-16 09:43:12 -05001412 u8 res11[8];
Kumar Gala3d8d9132009-09-28 21:38:00 -05001413 u32 rstrqmr1; /* Reset request mask */
Shaveta Leekha2145a3e2014-02-26 16:06:56 +05301414#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
1415#define FSL_CORENET_RSTRQMR1_SRDS_RST_MSK 0x00000800
1416#endif
Kumar Gala3d8d9132009-09-28 21:38:00 -05001417 u8 res12[4];
1418 u32 rstrqsr1; /* Reset request status */
1419 u8 res13[4];
1420 u8 res14[4];
1421 u32 rstrqwdtmrl; /* Reset request WDT mask */
1422 u8 res15[4];
1423 u32 rstrqwdtsrl; /* Reset request WDT status */
1424 u8 res16[4];
1425 u32 brrl; /* Boot release */
Kumar Galad5740162009-09-16 09:43:12 -05001426 u8 res17[24];
Kumar Gala3d8d9132009-09-28 21:38:00 -05001427 u32 rcwsr[16]; /* Reset control word status */
Aneesh Bansalc4713ec2016-01-22 16:37:25 +05301428#define RCW_SB_EN_REG_INDEX 7
1429#define RCW_SB_EN_MASK 0x00200000
York Sun9650b632012-10-08 07:44:14 +00001430
1431#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
York Sunb8a076b2012-10-08 07:44:09 +00001432#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 16
York Sun7b083df2014-03-28 15:07:27 -07001433/* use reserved bits 18~23 as scratch space to host DDR PLL ratio */
1434#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT 8
York Sunb8a076b2012-10-08 07:44:09 +00001435#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x3f
Tom Rinia7ffa3d2021-05-23 10:58:05 -04001436#if defined(CONFIG_ARCH_T4240)
York Sun9650b632012-10-08 07:44:14 +00001437#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfc000000
1438#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 26
1439#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000
1440#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 17
1441#define FSL_CORENET2_RCWSR4_SRDS3_PRTCL 0x0000f800
1442#define FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT 11
1443#define FSL_CORENET2_RCWSR4_SRDS4_PRTCL 0x000000f8
1444#define FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT 3
Liu Gang50082f02013-05-07 16:30:50 +08001445#define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
York Sunfda566d2016-11-18 11:56:57 -08001446#elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420)
York Sunbcf7b3d2012-10-08 07:44:20 +00001447#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfe000000
1448#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 25
1449#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000
1450#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 16
Liu Gang0ff15f92013-05-07 16:30:48 +08001451#define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
York Sund7dd06c2016-12-28 08:43:32 -08001452#elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042)
York Sun46571362013-03-25 07:40:06 +00001453#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000
1454#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24
1455#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000
1456#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 17
Prabhakar Kushwahae70cd8d2014-01-27 15:55:20 +05301457#define FSL_CORENET_RCWSR13_EC1 0x30000000 /* bits 418..419 */
1458#define FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_RGMII 0x00000000
1459#define FSL_CORENET_RCWSR13_EC1_FM1_GPIO 0x10000000
1460#define FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII 0x20000000
1461#define FSL_CORENET_RCWSR13_EC2 0x0c000000 /* bits 420..421 */
1462#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII 0x00000000
Bin Mengf02840b2018-10-08 06:55:57 -07001463#define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x04000000
Prabhakar Kushwahae70cd8d2014-01-27 15:55:20 +05301464#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL 0x00000080
1465#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_L2_SWITCH 0x00000000
Bin Mengab4d5ee2018-10-08 06:55:56 -07001466#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT 0x00000080
Priyanka Jain794c1c72014-01-30 15:39:58 +05301467#define PXCKEN_MASK 0x80000000
1468#define PXCK_MASK 0x00FF0000
1469#define PXCK_BITS_START 16
Tom Rinib4e60262021-05-14 21:34:22 -04001470#elif defined(CONFIG_ARCH_T1024)
Shengzhou Liue6fb7702014-11-24 17:11:54 +08001471#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff800000
1472#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 23
1473#define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
1474#define FSL_CORENET_RCWSR13_EC1 0x30000000 /* bits 418..419 */
1475#define FSL_CORENET_RCWSR13_EC1_RGMII 0x00000000
1476#define FSL_CORENET_RCWSR13_EC1_GPIO 0x10000000
1477#define FSL_CORENET_RCWSR13_EC2 0x0c000000
1478#define FSL_CORENET_RCWSR13_EC2_RGMII 0x08000000
Shengzhou Liue6fb7702014-11-24 17:11:54 +08001479#define PXCKEN_MASK 0x80000000
1480#define PXCK_MASK 0x00FF0000
1481#define PXCK_BITS_START 16
Tom Rini3ec582b2021-02-20 20:06:21 -05001482#elif defined(CONFIG_ARCH_T2080)
Shengzhou Liuf305cd22013-11-22 17:39:10 +08001483#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000
1484#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24
1485#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000
1486#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 16
1487#define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
York Sun9941a222012-10-08 07:44:19 +00001488#endif
York Sun9650b632012-10-08 07:44:14 +00001489#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL1 0x00800000
1490#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL2 0x00400000
1491#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S2_PLL1 0x00200000
1492#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S2_PLL2 0x00100000
1493#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S3_PLL1 0x00080000
1494#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S3_PLL2 0x00040000
1495#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL1 0x00020000
1496#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL2 0x00010000
Priyanka Jaine9dcaa82013-12-17 14:25:52 +05301497#define FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT 4
1498#define FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK 0x00000011
1499#define FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK 1
York Sun9650b632012-10-08 07:44:14 +00001500
1501#else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
1502#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 17
1503#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x1f
Kumar Galad5740162009-09-16 09:43:12 -05001504#define FSL_CORENET_RCWSR4_SRDS_PRTCL 0xfc000000
Srikanth Srinivasanf58c2a42010-02-10 17:32:43 +08001505#define FSL_CORENET_RCWSR5_DDR_SYNC 0x00000080
1506#define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT 7
Kumar Gala13d1fe12010-04-07 10:39:46 -05001507#define FSL_CORENET_RCWSR5_SRDS_EN 0x00002000
Timur Tabid5e13882012-10-05 11:09:19 +00001508#define FSL_CORENET_RCWSR5_SRDS2_EN 0x00001000
Liu Gange86e1a32012-08-09 05:10:00 +00001509#define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
Kumar Gala74e78b62010-04-28 04:02:21 -05001510#define FSL_CORENET_RCWSRn_SRDS_LPD_B2 0x3c000000 /* bits 162..165 */
1511#define FSL_CORENET_RCWSRn_SRDS_LPD_B3 0x003c0000 /* bits 170..173 */
York Sun9650b632012-10-08 07:44:14 +00001512#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
1513
Kumar Galad5740162009-09-16 09:43:12 -05001514#define FSL_CORENET_RCWSR7_MCK_TO_PLAT_RAT 0x00400000
1515#define FSL_CORENET_RCWSR8_HOST_AGT_B1 0x00e00000
1516#define FSL_CORENET_RCWSR8_HOST_AGT_B2 0x00100000
Kumar Gala74e78b62010-04-28 04:02:21 -05001517#define FSL_CORENET_RCWSR11_EC1 0x00c00000 /* bits 360..361 */
York Sun84be8a92016-11-18 11:24:40 -08001518#ifdef CONFIG_ARCH_P4080
Kumar Gala2683c532011-04-13 08:37:44 -05001519#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1 0x00000000
1520#define FSL_CORENET_RCWSR11_EC1_FM1_USB1 0x00800000
Kumar Gala74e78b62010-04-28 04:02:21 -05001521#define FSL_CORENET_RCWSR11_EC2 0x001c0000 /* bits 363..365 */
Kumar Gala2683c532011-04-13 08:37:44 -05001522#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1 0x00000000
1523#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2 0x00080000
1524#define FSL_CORENET_RCWSR11_EC2_USB2 0x00100000
1525#endif
York Sundf70d062016-11-18 11:20:40 -08001526#if defined(CONFIG_ARCH_P2041) || \
Tom Rini30900822021-02-20 20:06:30 -05001527 defined(CONFIG_ARCH_P3041)
Kumar Gala2683c532011-04-13 08:37:44 -05001528#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_RGMII 0x00000000
1529#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_MII 0x00800000
1530#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_NONE 0x00c00000
1531#define FSL_CORENET_RCWSR11_EC2 0x00180000 /* bits 363..364 */
1532#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_RGMII 0x00000000
1533#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_MII 0x00100000
1534#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_NONE 0x00180000
1535#endif
York Suna3c5b662016-11-18 11:39:36 -08001536#if defined(CONFIG_ARCH_P5040)
Timur Tabid5e13882012-10-05 11:09:19 +00001537#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_RGMII 0x00000000
1538#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_MII 0x00800000
1539#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_NONE 0x00c00000
1540#define FSL_CORENET_RCWSR11_EC2 0x00180000 /* bits 363..364 */
1541#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_RGMII 0x00000000
1542#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII 0x00100000
1543#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_NONE 0x00180000
1544#endif
Tom Rinia7ffa3d2021-05-23 10:58:05 -04001545#if defined(CONFIG_ARCH_T4240)
York Sun9941a222012-10-08 07:44:19 +00001546#define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */
1547#define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII 0x00000000
1548#define FSL_CORENET_RCWSR13_EC1_FM2_GPIO 0x40000000
1549#define FSL_CORENET_RCWSR13_EC2 0x18000000 /* bits 419..420 */
1550#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII 0x00000000
1551#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC6_RGMII 0x08000000
1552#define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x10000000
1553#endif
Tom Rini3ec582b2021-02-20 20:06:21 -05001554#if defined(CONFIG_ARCH_T2080)
Shengzhou Liuf305cd22013-11-22 17:39:10 +08001555#define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */
1556#define FSL_CORENET_RCWSR13_EC1_DTSEC3_RGMII 0x00000000
1557#define FSL_CORENET_RCWSR13_EC1_GPIO 0x40000000
1558#define FSL_CORENET_RCWSR13_EC2 0x18000000 /* bits 419..420 */
1559#define FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII 0x00000000
1560#define FSL_CORENET_RCWSR13_EC2_DTSEC10_RGMII 0x08000000
1561#define FSL_CORENET_RCWSR13_EC2_GPIO 0x10000000
1562#endif
Kumar Gala3d8d9132009-09-28 21:38:00 -05001563 u8 res18[192];
1564 u32 scratchrw[4]; /* Scratch Read/Write */
1565 u8 res19[240];
1566 u32 scratchw1r[4]; /* Scratch Read (Write once) */
1567 u8 res20[240];
1568 u32 scrtsr[8]; /* Core reset status */
1569 u8 res21[224];
1570 u32 pex1liodnr; /* PCI Express 1 LIODN */
1571 u32 pex2liodnr; /* PCI Express 2 LIODN */
1572 u32 pex3liodnr; /* PCI Express 3 LIODN */
1573 u32 pex4liodnr; /* PCI Express 4 LIODN */
1574 u32 rio1liodnr; /* RIO 1 LIODN */
1575 u32 rio2liodnr; /* RIO 2 LIODN */
1576 u32 rio3liodnr; /* RIO 3 LIODN */
1577 u32 rio4liodnr; /* RIO 4 LIODN */
1578 u32 usb1liodnr; /* USB 1 LIODN */
1579 u32 usb2liodnr; /* USB 2 LIODN */
1580 u32 usb3liodnr; /* USB 3 LIODN */
1581 u32 usb4liodnr; /* USB 4 LIODN */
1582 u32 sdmmc1liodnr; /* SD/MMC 1 LIODN */
1583 u32 sdmmc2liodnr; /* SD/MMC 2 LIODN */
1584 u32 sdmmc3liodnr; /* SD/MMC 3 LIODN */
1585 u32 sdmmc4liodnr; /* SD/MMC 4 LIODN */
Kumar Gala74e78b62010-04-28 04:02:21 -05001586 u32 rio1maintliodnr;/* RIO 1 Maintenance LIODN */
1587 u32 rio2maintliodnr;/* RIO 2 Maintenance LIODN */
1588 u32 rio3maintliodnr;/* RIO 3 Maintenance LIODN */
1589 u32 rio4maintliodnr;/* RIO 4 Maintenance LIODN */
1590 u32 sata1liodnr; /* SATA 1 LIODN */
1591 u32 sata2liodnr; /* SATA 2 LIODN */
1592 u32 sata3liodnr; /* SATA 3 LIODN */
1593 u32 sata4liodnr; /* SATA 4 LIODN */
Sandeep Singh4fb16a12014-06-05 18:49:57 +05301594 u8 res22[20];
1595 u32 tdmliodnr; /* TDM LIODN */
Zhao Qiangb818ba22014-03-21 16:21:45 +08001596 u32 qeliodnr; /* QE LIODN */
1597 u8 res_57c[4];
Kumar Gala3d8d9132009-09-28 21:38:00 -05001598 u32 dma1liodnr; /* DMA 1 LIODN */
1599 u32 dma2liodnr; /* DMA 2 LIODN */
1600 u32 dma3liodnr; /* DMA 3 LIODN */
1601 u32 dma4liodnr; /* DMA 4 LIODN */
1602 u8 res23[48];
1603 u8 res24[64];
1604 u32 pblsr; /* Preboot loader status */
1605 u32 pamubypenr; /* PAMU bypass enable */
1606 u32 dmacr1; /* DMA control */
1607 u8 res25[4];
1608 u32 gensr1; /* General status */
1609 u8 res26[12];
1610 u32 gencr1; /* General control */
1611 u8 res27[12];
1612 u8 res28[4];
1613 u32 cgensrl; /* Core general status */
1614 u8 res29[8];
1615 u8 res30[4];
1616 u32 cgencrl; /* Core general control */
1617 u8 res31[184];
1618 u32 sriopstecr; /* SRIO prescaler timer enable control */
Stephen George5bbf29c2011-07-20 09:47:26 -05001619 u32 dcsrcr; /* DCSR Control register */
York Sunbfb29a22012-08-17 08:20:21 +00001620 u8 res31a[56];
1621 u32 tp_ityp[64]; /* Topology Initiator Type Register */
1622 struct {
1623 u32 upper;
1624 u32 lower;
1625 } tp_cluster[16]; /* Core Cluster n Topology Register */
1626 u8 res32[1344];
Dave Liu838dec12010-03-05 12:23:00 +08001627 u32 pmuxcr; /* Pin multiplexing control */
1628 u8 res33[60];
1629 u32 iovselsr; /* I/O voltage selection status */
1630 u8 res34[28];
1631 u32 ddrclkdr; /* DDR clock disable */
1632 u8 res35;
1633 u32 elbcclkdr; /* eLBC clock disable */
1634 u8 res36[20];
1635 u32 sdhcpcr; /* eSDHC polarity configuration */
1636 u8 res37[380];
Kumar Galad5740162009-09-16 09:43:12 -05001637} ccsr_gur_t;
1638
York Sunbfb29a22012-08-17 08:20:21 +00001639#define TP_ITYP_AV 0x00000001 /* Initiator available */
1640#define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */
1641#define TP_ITYP_TYPE_OTHER 0x0
1642#define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */
1643#define TP_ITYP_TYPE_SC 0x2 /* StarCore DSP */
1644#define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */
1645#define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */
1646#define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */
1647
1648#define TP_CLUSTER_EOC 0x80000000 /* end of clusters */
1649#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */
York Sunaa150bb2013-03-25 07:40:07 +00001650#define TP_INIT_PER_CLUSTER 4
York Sunbfb29a22012-08-17 08:20:21 +00001651
Stephen George5bbf29c2011-07-20 09:47:26 -05001652#define FSL_CORENET_DCSR_SZ_MASK 0x00000003
1653#define FSL_CORENET_DCSR_SZ_4M 0x0
1654#define FSL_CORENET_DCSR_SZ_1G 0x3
1655
Kumar Gala74e78b62010-04-28 04:02:21 -05001656/*
1657 * On p4080 we have an LIODN for msg unit (rmu) but not maintenance
1658 * everything after has RMan thus msg unit LIODN is used for maintenance
1659 */
1660#define rmuliodnr rio1maintliodnr
1661
Kumar Galad5740162009-09-16 09:43:12 -05001662typedef struct ccsr_clk {
York Sunaa150bb2013-03-25 07:40:07 +00001663 struct {
1664 u32 clkcncsr; /* core cluster n clock control status */
1665 u8 res_004[0x0c];
1666 u32 clkcgnhwacsr;/* clock generator n hardware accelerator */
1667 u8 res_014[0x0c];
Prabhakar Kushwaha7e8382f2013-09-03 11:20:15 +05301668 } clkcsr[12];
1669 u8 res_100[0x680]; /* 0x100 */
1670 struct {
1671 u32 pllcngsr;
1672 u8 res10[0x1c];
1673 } pllcgsr[12];
1674 u8 res21[0x280];
York Sund7778f72012-10-08 07:44:11 +00001675 u32 pllpgsr; /* 0xc00 Platform PLL General Status */
1676 u8 res16[0x1c];
1677 u32 plldgsr; /* 0xc20 DDR PLL General Status */
1678 u8 res17[0x3dc];
Kumar Galad5740162009-09-16 09:43:12 -05001679} ccsr_clk_t;
1680
York Sunbfb29a22012-08-17 08:20:21 +00001681#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
1682typedef struct ccsr_rcpm {
1683 u8 res_00[12];
1684 u32 tph10sr0; /* Thread PH10 Status Register */
1685 u8 res_10[12];
1686 u32 tph10setr0; /* Thread PH10 Set Control Register */
1687 u8 res_20[12];
1688 u32 tph10clrr0; /* Thread PH10 Clear Control Register */
1689 u8 res_30[12];
1690 u32 tph10psr0; /* Thread PH10 Previous Status Register */
1691 u8 res_40[12];
1692 u32 twaitsr0; /* Thread Wait Status Register */
1693 u8 res_50[96];
1694 u32 pcph15sr; /* Physical Core PH15 Status Register */
1695 u32 pcph15setr; /* Physical Core PH15 Set Control Register */
1696 u32 pcph15clrr; /* Physical Core PH15 Clear Control Register */
1697 u32 pcph15psr; /* Physical Core PH15 Prev Status Register */
1698 u8 res_c0[16];
1699 u32 pcph20sr; /* Physical Core PH20 Status Register */
1700 u32 pcph20setr; /* Physical Core PH20 Set Control Register */
1701 u32 pcph20clrr; /* Physical Core PH20 Clear Control Register */
1702 u32 pcph20psr; /* Physical Core PH20 Prev Status Register */
1703 u32 pcpw20sr; /* Physical Core PW20 Status Register */
1704 u8 res_e0[12];
1705 u32 pcph30sr; /* Physical Core PH30 Status Register */
1706 u32 pcph30setr; /* Physical Core PH30 Set Control Register */
1707 u32 pcph30clrr; /* Physical Core PH30 Clear Control Register */
1708 u32 pcph30psr; /* Physical Core PH30 Prev Status Register */
1709 u8 res_100[32];
1710 u32 ippwrgatecr; /* IP Power Gating Control Register */
1711 u8 res_124[12];
1712 u32 powmgtcsr; /* Power Management Control & Status Reg */
1713 u8 res_134[12];
1714 u32 ippdexpcr[4]; /* IP Powerdown Exception Control Reg */
1715 u8 res_150[12];
1716 u32 tpmimr0; /* Thread PM Interrupt Mask Reg */
1717 u8 res_160[12];
1718 u32 tpmcimr0; /* Thread PM Crit Interrupt Mask Reg */
1719 u8 res_170[12];
1720 u32 tpmmcmr0; /* Thread PM Machine Check Interrupt Mask Reg */
1721 u8 res_180[12];
1722 u32 tpmnmimr0; /* Thread PM NMI Mask Reg */
1723 u8 res_190[12];
1724 u32 tmcpmaskcr0; /* Thread Machine Check Mask Control Reg */
1725 u32 pctbenr; /* Physical Core Time Base Enable Reg */
1726 u32 pctbclkselr; /* Physical Core Time Base Clock Select */
1727 u32 tbclkdivr; /* Time Base Clock Divider Register */
1728 u8 res_1ac[4];
1729 u32 ttbhltcr[4]; /* Thread Time Base Halt Control Register */
1730 u32 clpcl10sr; /* Cluster PCL10 Status Register */
1731 u32 clpcl10setr; /* Cluster PCL30 Set Control Register */
1732 u32 clpcl10clrr; /* Cluster PCL30 Clear Control Register */
1733 u32 clpcl10psr; /* Cluster PCL30 Prev Status Register */
1734 u32 cddslpsetr; /* Core Domain Deep Sleep Set Register */
1735 u32 cddslpclrr; /* Core Domain Deep Sleep Clear Register */
1736 u32 cdpwroksetr; /* Core Domain Power OK Set Register */
1737 u32 cdpwrokclrr; /* Core Domain Power OK Clear Register */
1738 u32 cdpwrensr; /* Core Domain Power Enable Status Register */
1739 u32 cddslsr; /* Core Domain Deep Sleep Status Register */
1740 u8 res_1e8[8];
1741 u32 dslpcntcr[8]; /* Deep Sleep Counter Cfg Register */
1742 u8 res_300[3568];
1743} ccsr_rcpm_t;
1744
1745#define ctbenrl pctbenr
1746
1747#else
Kumar Galad5740162009-09-16 09:43:12 -05001748typedef struct ccsr_rcpm {
Kumar Gala3d8d9132009-09-28 21:38:00 -05001749 u8 res1[4];
1750 u32 cdozsrl; /* Core Doze Status */
1751 u8 res2[4];
1752 u32 cdozcrl; /* Core Doze Control */
1753 u8 res3[4];
1754 u32 cnapsrl; /* Core Nap Status */
1755 u8 res4[4];
1756 u32 cnapcrl; /* Core Nap Control */
1757 u8 res5[4];
1758 u32 cdozpsrl; /* Core Doze Previous Status */
1759 u8 res6[4];
1760 u32 cdozpcrl; /* Core Doze Previous Control */
1761 u8 res7[4];
1762 u32 cwaitsrl; /* Core Wait Status */
1763 u8 res8[8];
1764 u32 powmgtcsr; /* Power Mangement Control & Status */
1765 u8 res9[12];
1766 u32 ippdexpcr0; /* IP Powerdown Exception Control 0 */
1767 u8 res10[12];
1768 u8 res11[4];
1769 u32 cpmimrl; /* Core PM IRQ Masking */
1770 u8 res12[4];
1771 u32 cpmcimrl; /* Core PM Critical IRQ Masking */
1772 u8 res13[4];
1773 u32 cpmmcimrl; /* Core PM Machine Check IRQ Masking */
1774 u8 res14[4];
1775 u32 cpmnmimrl; /* Core PM NMI Masking */
1776 u8 res15[4];
1777 u32 ctbenrl; /* Core Time Base Enable */
1778 u8 res16[4];
1779 u32 ctbclkselrl; /* Core Time Base Clock Select */
1780 u8 res17[4];
1781 u32 ctbhltcrl; /* Core Time Base Halt Control */
Kumar Galad5740162009-09-16 09:43:12 -05001782 u8 res18[0xf68];
1783} ccsr_rcpm_t;
York Sunbfb29a22012-08-17 08:20:21 +00001784#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
Kumar Galad5740162009-09-16 09:43:12 -05001785
1786#else
wdenk9c53f402003-10-15 23:53:47 +00001787typedef struct ccsr_gur {
Kumar Gala3d8d9132009-09-28 21:38:00 -05001788 u32 porpllsr; /* POR PLL ratio status */
York Sun5557d6b2016-11-16 11:06:47 -08001789#ifdef CONFIG_ARCH_MPC8536
Jason Jinbfcd6c32008-09-27 14:40:57 +08001790#define MPC85xx_PORPLLSR_DDR_RATIO 0x3e000000
1791#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 25
York Sun4119aee2016-11-15 18:44:22 -08001792#elif defined(CONFIG_ARCH_C29X)
Mingkai Hu1a258072013-07-04 17:30:36 +08001793#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003f00
1794#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT (9 - ((gur->pordevsr2 \
1795 & MPC85xx_PORDEVSR2_DDR_SPD_0) \
1796 >> MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT))
Jason Jinbfcd6c32008-09-27 14:40:57 +08001797#else
York Suna80bdf72016-11-15 14:09:50 -08001798#if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132)
Prabhakar Kushwahabeebb882012-04-24 20:16:49 +00001799#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003f00
1800#else
Jason Jinbfcd6c32008-09-27 14:40:57 +08001801#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003e00
Prabhakar Kushwahabeebb882012-04-24 20:16:49 +00001802#endif
Jason Jinbfcd6c32008-09-27 14:40:57 +08001803#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 9
1804#endif
Haiying Wang61414682009-05-20 12:30:29 -04001805#define MPC85xx_PORPLLSR_QE_RATIO 0x3e000000
1806#define MPC85xx_PORPLLSR_QE_RATIO_SHIFT 25
Mingkai Huaec75c02009-09-22 14:53:34 +08001807#define MPC85xx_PORPLLSR_PLAT_RATIO 0x0000003e
Kumar Gala3d8d9132009-09-28 21:38:00 -05001808#define MPC85xx_PORPLLSR_PLAT_RATIO_SHIFT 1
1809 u32 porbmsr; /* POR boot mode status */
Wolfgang Denka1be4762008-05-20 16:00:29 +02001810#define MPC85xx_PORBMSR_HA 0x00070000
Peter Tyser3a68f3d2009-05-22 10:26:32 -05001811#define MPC85xx_PORBMSR_HA_SHIFT 16
Andy Fleming7cc7b772013-06-20 14:54:33 -05001812#define MPC85xx_PORBMSR_ROMLOC_SHIFT 24
Prabhakar Kushwaha92543c22013-01-23 17:59:57 +00001813#define PORBMSR_ROMLOC_SPI 0x6
1814#define PORBMSR_ROMLOC_SDHC 0x7
1815#define PORBMSR_ROMLOC_NAND_2K 0x9
1816#define PORBMSR_ROMLOC_NOR 0xf
Kumar Gala3d8d9132009-09-28 21:38:00 -05001817 u32 porimpscr; /* POR I/O impedance status & control */
1818 u32 pordevsr; /* POR I/O device status regsiter */
York Sunab507fb2016-11-16 16:06:48 -08001819#if defined(CONFIG_ARCH_P1023)
Roy Zang1de20b02011-02-03 22:14:19 -06001820#define MPC85xx_PORDEVSR_SGMII1_DIS 0x10000000
1821#define MPC85xx_PORDEVSR_SGMII2_DIS 0x08000000
Kumar Gala2683c532011-04-13 08:37:44 -05001822#define MPC85xx_PORDEVSR_TSEC1_PRTC 0x02000000
Roy Zang1de20b02011-02-03 22:14:19 -06001823#else
Ed Swarthout52b98522007-07-27 01:50:51 -05001824#define MPC85xx_PORDEVSR_SGMII1_DIS 0x20000000
1825#define MPC85xx_PORDEVSR_SGMII2_DIS 0x10000000
Roy Zang1de20b02011-02-03 22:14:19 -06001826#endif
Ed Swarthout52b98522007-07-27 01:50:51 -05001827#define MPC85xx_PORDEVSR_SGMII3_DIS 0x08000000
1828#define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000
Kumar Gala3d8d9132009-09-28 21:38:00 -05001829#define MPC85xx_PORDEVSR_SRDS2_IO_SEL 0x38000000
Peter Tyseraf7c3e32008-12-01 13:47:12 -06001830#define MPC85xx_PORDEVSR_PCI1 0x00800000
Tom Rini197f2902021-02-20 20:06:26 -05001831#if defined(CONFIG_ARCH_P1023)
Roy Zang1de20b02011-02-03 22:14:19 -06001832#define MPC85xx_PORDEVSR_IO_SEL 0x00600000
1833#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21
Dave Liuacbd8ec2010-04-14 19:05:06 +08001834#else
York Sun24f88b32016-11-16 13:08:52 -08001835#if defined(CONFIG_ARCH_P1010)
Prabhakar Kushwaha934e6ed2011-01-20 16:34:41 +05301836#define MPC85xx_PORDEVSR_IO_SEL 0x00600000
1837#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21
York Suna80bdf72016-11-15 14:09:50 -08001838#elif defined(CONFIG_ARCH_BSC9132)
Prabhakar Kushwaha92543c22013-01-23 17:59:57 +00001839#define MPC85xx_PORDEVSR_IO_SEL 0x00FE0000
1840#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 17
York Sun4119aee2016-11-15 18:44:22 -08001841#elif defined(CONFIG_ARCH_C29X)
Mingkai Hu1a258072013-07-04 17:30:36 +08001842#define MPC85xx_PORDEVSR_IO_SEL 0x00e00000
1843#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21
Prabhakar Kushwaha934e6ed2011-01-20 16:34:41 +05301844#else
Peter Tyser603e6382008-10-27 16:42:00 -05001845#define MPC85xx_PORDEVSR_IO_SEL 0x00780000
Peter Tyser3a68f3d2009-05-22 10:26:32 -05001846#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 19
York Sun24f88b32016-11-16 13:08:52 -08001847#endif /* if defined(CONFIG_ARCH_P1010) */
Dave Liuacbd8ec2010-04-14 19:05:06 +08001848#endif
Wolfgang Denka1be4762008-05-20 16:00:29 +02001849#define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000
1850#define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000
1851#define MPC85xx_PORDEVSR_PCI1_PCI32 0x00010000
1852#define MPC85xx_PORDEVSR_PCI1_SPD 0x00008000
1853#define MPC85xx_PORDEVSR_PCI2_SPD 0x00004000
Ed Swarthout52b98522007-07-27 01:50:51 -05001854#define MPC85xx_PORDEVSR_DRAM_RTYPE 0x00000060
Wolfgang Denka1be4762008-05-20 16:00:29 +02001855#define MPC85xx_PORDEVSR_RIO_CTLS 0x00000008
Ed Swarthout52b98522007-07-27 01:50:51 -05001856#define MPC85xx_PORDEVSR_RIO_DEV_ID 0x00000007
Kumar Gala3d8d9132009-09-28 21:38:00 -05001857 u32 pordbgmsr; /* POR debug mode status */
1858 u32 pordevsr2; /* POR I/O device status 2 */
York Sun4119aee2016-11-15 18:44:22 -08001859#if defined(CONFIG_ARCH_C29X)
Mingkai Hu1a258072013-07-04 17:30:36 +08001860#define MPC85xx_PORDEVSR2_DDR_SPD_0 0x00000008
1861#define MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT 3
1862#endif
Aneesh Bansalc4713ec2016-01-22 16:37:25 +05301863#define MPC85xx_PORDEVSR2_SBC_MASK 0x10000000
Timur Tabi206c7262008-10-20 15:16:47 -05001864/* The 8544 RM says this is bit 26, but it's really bit 24 */
Kumar Galaa5694a12008-10-16 21:58:50 -05001865#define MPC85xx_PORDEVSR2_SEC_CFG 0x00000080
Kumar Gala3d8d9132009-09-28 21:38:00 -05001866 u8 res1[8];
1867 u32 gpporcr; /* General-purpose POR configuration */
1868 u8 res2[12];
York Sun5557d6b2016-11-16 11:06:47 -08001869#if defined(CONFIG_ARCH_MPC8536)
Xie Xiaobo8f3933e2011-10-03 12:18:39 -07001870 u32 gencfgr; /* General Configuration Register */
1871#define MPC85xx_GENCFGR_SDHC_WP_INV 0x20000000
1872#else
Kumar Gala3d8d9132009-09-28 21:38:00 -05001873 u32 gpiocr; /* GPIO control */
Xie Xiaobo8f3933e2011-10-03 12:18:39 -07001874#endif
Kumar Gala3d8d9132009-09-28 21:38:00 -05001875 u8 res3[12];
Kumar Gala3d8d9132009-09-28 21:38:00 -05001876 u32 gpoutdr; /* General-purpose output data */
1877 u8 res4[12];
Kumar Gala3d8d9132009-09-28 21:38:00 -05001878 u32 gpindr; /* General-purpose input data */
1879 u8 res5[12];
1880 u32 pmuxcr; /* Alt. function signal multiplex control */
York Sun5f163882016-11-16 16:02:09 -08001881#if defined(CONFIG_ARCH_P1010)
Dipen Dudhat7b430412011-03-22 08:31:36 -05001882#define MPC85xx_PMUXCR_TSEC1_0_1588 0x40000000
1883#define MPC85xx_PMUXCR_TSEC1_0_RES 0xC0000000
1884#define MPC85xx_PMUXCR_TSEC1_1_1588_TRIG 0x10000000
1885#define MPC85xx_PMUXCR_TSEC1_1_GPIO_12 0x20000000
1886#define MPC85xx_PMUXCR_TSEC1_1_RES 0x30000000
1887#define MPC85xx_PMUXCR_TSEC1_2_DMA 0x04000000
1888#define MPC85xx_PMUXCR_TSEC1_2_GPIO 0x08000000
1889#define MPC85xx_PMUXCR_TSEC1_2_RES 0x0C000000
1890#define MPC85xx_PMUXCR_TSEC1_3_RES 0x01000000
1891#define MPC85xx_PMUXCR_TSEC1_3_GPIO_15 0x02000000
1892#define MPC85xx_PMUXCR_IFC_ADDR16_SDHC 0x00400000
1893#define MPC85xx_PMUXCR_IFC_ADDR16_USB 0x00800000
1894#define MPC85xx_PMUXCR_IFC_ADDR16_IFC_CS2 0x00C00000
1895#define MPC85xx_PMUXCR_IFC_ADDR17_18_SDHC 0x00100000
1896#define MPC85xx_PMUXCR_IFC_ADDR17_18_USB 0x00200000
1897#define MPC85xx_PMUXCR_IFC_ADDR17_18_DMA 0x00300000
1898#define MPC85xx_PMUXCR_IFC_ADDR19_SDHC_DATA 0x00040000
1899#define MPC85xx_PMUXCR_IFC_ADDR19_USB 0x00080000
1900#define MPC85xx_PMUXCR_IFC_ADDR19_DMA 0x000C0000
1901#define MPC85xx_PMUXCR_IFC_ADDR20_21_SDHC_DATA 0x00010000
1902#define MPC85xx_PMUXCR_IFC_ADDR20_21_USB 0x00020000
1903#define MPC85xx_PMUXCR_IFC_ADDR20_21_RES 0x00030000
1904#define MPC85xx_PMUXCR_IFC_ADDR22_SDHC 0x00004000
1905#define MPC85xx_PMUXCR_IFC_ADDR22_USB 0x00008000
1906#define MPC85xx_PMUXCR_IFC_ADDR22_RES 0x0000C000
1907#define MPC85xx_PMUXCR_IFC_ADDR23_SDHC 0x00001000
1908#define MPC85xx_PMUXCR_IFC_ADDR23_USB 0x00002000
1909#define MPC85xx_PMUXCR_IFC_ADDR23_RES 0x00003000
1910#define MPC85xx_PMUXCR_IFC_ADDR24_SDHC 0x00000400
1911#define MPC85xx_PMUXCR_IFC_ADDR24_USB 0x00000800
1912#define MPC85xx_PMUXCR_IFC_ADDR24_RES 0x00000C00
1913#define MPC85xx_PMUXCR_IFC_PAR_PERR_RES 0x00000300
1914#define MPC85xx_PMUXCR_IFC_PAR_PERR_USB 0x00000200
1915#define MPC85xx_PMUXCR_LCLK_RES 0x00000040
1916#define MPC85xx_PMUXCR_LCLK_USB 0x00000080
1917#define MPC85xx_PMUXCR_LCLK_IFC_CS3 0x000000C0
1918#define MPC85xx_PMUXCR_SPI_RES 0x00000030
1919#define MPC85xx_PMUXCR_SPI_GPIO 0x00000020
1920#define MPC85xx_PMUXCR_CAN1_UART 0x00000004
1921#define MPC85xx_PMUXCR_CAN1_TDM 0x00000008
1922#define MPC85xx_PMUXCR_CAN1_RES 0x0000000C
1923#define MPC85xx_PMUXCR_CAN2_UART 0x00000001
1924#define MPC85xx_PMUXCR_CAN2_TDM 0x00000002
1925#define MPC85xx_PMUXCR_CAN2_RES 0x00000003
1926#endif
York Sunab507fb2016-11-16 16:06:48 -08001927#if defined(CONFIG_ARCH_P1023)
Roy Zang6c6752d2011-02-04 13:42:45 -06001928#define MPC85xx_PMUXCR_TSEC1_1 0x10000000
1929#else
Andy Fleming6843a6e2008-10-30 16:51:33 -05001930#define MPC85xx_PMUXCR_SD_DATA 0x80000000
1931#define MPC85xx_PMUXCR_SDHC_CD 0x40000000
1932#define MPC85xx_PMUXCR_SDHC_WP 0x20000000
Ramneek Mehresh31253df2011-04-09 13:08:47 -05001933#define MPC85xx_PMUXCR_ELBC_OFF_USB2_ON 0x01000000
Zhao Chenhui36ffc412011-01-27 19:02:47 +08001934#define MPC85xx_PMUXCR_TDM_ENA 0x00800000
Haiying Wang8cb2af72011-02-11 01:25:30 -06001935#define MPC85xx_PMUXCR_QE0 0x00008000
1936#define MPC85xx_PMUXCR_QE1 0x00004000
1937#define MPC85xx_PMUXCR_QE2 0x00002000
1938#define MPC85xx_PMUXCR_QE3 0x00001000
1939#define MPC85xx_PMUXCR_QE4 0x00000800
1940#define MPC85xx_PMUXCR_QE5 0x00000400
1941#define MPC85xx_PMUXCR_QE6 0x00000200
1942#define MPC85xx_PMUXCR_QE7 0x00000100
1943#define MPC85xx_PMUXCR_QE8 0x00000080
1944#define MPC85xx_PMUXCR_QE9 0x00000040
1945#define MPC85xx_PMUXCR_QE10 0x00000020
1946#define MPC85xx_PMUXCR_QE11 0x00000010
1947#define MPC85xx_PMUXCR_QE12 0x00000008
Roy Zang6c6752d2011-02-04 13:42:45 -06001948#endif
York Suna80bdf72016-11-15 14:09:50 -08001949#if defined(CONFIG_ARCH_BSC9131)
Prabhakar Kushwahabeebb882012-04-24 20:16:49 +00001950#define MPC85xx_PMUXCR_TSEC2_DMA_GPIO_IRQ 0x40000000
1951#define MPC85xx_PMUXCR_TSEC2_USB 0xC0000000
1952#define MPC85xx_PMUXCR_TSEC2_1588_PPS 0x10000000
1953#define MPC85xx_PMUXCR_TSEC2_1588_RSVD 0x30000000
1954#define MPC85xx_PMUXCR_IFC_AD_GPIO 0x04000000
1955#define MPC85xx_PMUXCR_IFC_AD_GPIO_MASK 0x0C000000
1956#define MPC85xx_PMUXCR_IFC_AD15_GPIO 0x01000000
1957#define MPC85xx_PMUXCR_IFC_AD15_TIMER2 0x02000000
1958#define MPC85xx_PMUXCR_IFC_AD16_GPO8 0x00400000
1959#define MPC85xx_PMUXCR_IFC_AD16_MSRCID0 0x00800000
1960#define MPC85xx_PMUXCR_IFC_AD17_GPO 0x00100000
1961#define MPC85xx_PMUXCR_IFC_AD17_GPO_MASK 0x00300000
1962#define MPC85xx_PMUXCR_IFC_AD17_MSRCID_DSP 0x00200000
1963#define MPC85xx_PMUXCR_IFC_CS2_GPO65 0x00040000
1964#define MPC85xx_PMUXCR_IFC_CS2_DSP_TDI 0x00080000
1965#define MPC85xx_PMUXCR_SDHC_USIM 0x00010000
1966#define MPC85xx_PMUXCR_SDHC_TDM_RFS_RCK 0x00020000
1967#define MPC85xx_PMUXCR_SDHC_GPIO77 0x00030000
1968#define MPC85xx_PMUXCR_SDHC_RESV 0x00004000
1969#define MPC85xx_PMUXCR_SDHC_TDM_TXD_RXD 0x00008000
1970#define MPC85xx_PMUXCR_SDHC_GPIO_TIMER4 0x0000C000
1971#define MPC85xx_PMUXCR_USB_CLK_UART_SIN 0x00001000
1972#define MPC85xx_PMUXCR_USB_CLK_GPIO69 0x00002000
1973#define MPC85xx_PMUXCR_USB_CLK_TIMER3 0x00003000
1974#define MPC85xx_PMUXCR_USB_UART_GPIO0 0x00000400
1975#define MPC85xx_PMUXCR_USB_RSVD 0x00000C00
1976#define MPC85xx_PMUXCR_USB_GPIO62_TRIG_IN 0x00000800
1977#define MPC85xx_PMUXCR_USB_D1_2_IIC2_SDA_SCL 0x00000100
1978#define MPC85xx_PMUXCR_USB_D1_2_GPIO71_72 0x00000200
1979#define MPC85xx_PMUXCR_USB_D1_2_RSVD 0x00000300
1980#define MPC85xx_PMUXCR_USB_DIR_GPIO2 0x00000040
1981#define MPC85xx_PMUXCR_USB_DIR_TIMER1 0x00000080
1982#define MPC85xx_PMUXCR_USB_DIR_MCP_B 0x000000C0
1983#define MPC85xx_PMUXCR_SPI1_UART3 0x00000010
1984#define MPC85xx_PMUXCR_SPI1_SIM 0x00000020
1985#define MPC85xx_PMUXCR_SPI1_CKSTP_IN_GPO74 0x00000030
1986#define MPC85xx_PMUXCR_SPI1_CS2_CKSTP_OUT_B 0x00000004
1987#define MPC85xx_PMUXCR_SPI1_CS2_dbg_adi1_rxen 0x00000008
1988#define MPC85xx_PMUXCR_SPI1_CS2_GPO75 0x0000000C
1989#define MPC85xx_PMUXCR_SPI1_CS3_ANT_TCXO_PWM 0x00000001
1990#define MPC85xx_PMUXCR_SPI1_CS3_dbg_adi2_rxen 0x00000002
1991#define MPC85xx_PMUXCR_SPI1_CS3_GPO76 0x00000003
1992#endif
York Suna80bdf72016-11-15 14:09:50 -08001993#ifdef CONFIG_ARCH_BSC9132
Prabhakar Kushwaha92543c22013-01-23 17:59:57 +00001994#define MPC85xx_PMUXCR0_SIM_SEL_MASK 0x0003b000
1995#define MPC85xx_PMUXCR0_SIM_SEL 0x00014000
1996#endif
York Sun4119aee2016-11-15 18:44:22 -08001997#if defined(CONFIG_ARCH_C29X)
Mingkai Hu1a258072013-07-04 17:30:36 +08001998#define MPC85xx_PMUXCR_SPI_MASK 0x00000300
1999#define MPC85xx_PMUXCR_SPI 0x00000000
2000#define MPC85xx_PMUXCR_SPI_GPIO 0x00000100
2001#endif
Timur Tabib1508932010-05-20 12:45:39 -05002002 u32 pmuxcr2; /* Alt. function signal multiplex control 2 */
York Sun5f163882016-11-16 16:02:09 -08002003#if defined(CONFIG_ARCH_P1010)
Dipen Dudhat7b430412011-03-22 08:31:36 -05002004#define MPC85xx_PMUXCR2_UART_GPIO 0x40000000
2005#define MPC85xx_PMUXCR2_UART_TDM 0x80000000
2006#define MPC85xx_PMUXCR2_UART_RES 0xC0000000
2007#define MPC85xx_PMUXCR2_IRQ2_TRIG_IN 0x10000000
2008#define MPC85xx_PMUXCR2_IRQ2_RES 0x30000000
2009#define MPC85xx_PMUXCR2_IRQ3_SRESET 0x04000000
2010#define MPC85xx_PMUXCR2_IRQ3_RES 0x0C000000
2011#define MPC85xx_PMUXCR2_GPIO01_DRVVBUS 0x01000000
2012#define MPC85xx_PMUXCR2_GPIO01_RES 0x03000000
2013#define MPC85xx_PMUXCR2_GPIO23_CKSTP 0x00400000
2014#define MPC85xx_PMUXCR2_GPIO23_RES 0x00800000
2015#define MPC85xx_PMUXCR2_GPIO23_USB 0x00C00000
2016#define MPC85xx_PMUXCR2_GPIO4_MCP 0x00100000
2017#define MPC85xx_PMUXCR2_GPIO4_RES 0x00200000
2018#define MPC85xx_PMUXCR2_GPIO4_CLK_OUT 0x00300000
2019#define MPC85xx_PMUXCR2_GPIO5_UDE 0x00040000
2020#define MPC85xx_PMUXCR2_GPIO5_RES 0x00080000
2021#define MPC85xx_PMUXCR2_READY_ASLEEP 0x00020000
2022#define MPC85xx_PMUXCR2_DDR_ECC_MUX 0x00010000
2023#define MPC85xx_PMUXCR2_DEBUG_PORT_EXPOSE 0x00008000
2024#define MPC85xx_PMUXCR2_POST_EXPOSE 0x00004000
2025#define MPC85xx_PMUXCR2_DEBUG_MUX_SEL_USBPHY 0x00002000
2026#define MPC85xx_PMUXCR2_PLL_LKDT_EXPOSE 0x00001000
2027#endif
York Suna80bdf72016-11-15 14:09:50 -08002028#if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132)
2029#if defined(CONFIG_ARCH_BSC9131)
Prabhakar Kushwahabeebb882012-04-24 20:16:49 +00002030#define MPC85xx_PMUXCR2_UART_CTS_B0_SIM_PD 0X40000000
2031#define MPC85xx_PMUXCR2_UART_CTS_B0_DSP_TMS 0X80000000
2032#define MPC85xx_PMUXCR2_UART_CTS_B0_GPIO42 0xC0000000
2033#define MPC85xx_PMUXCR2_UART_RTS_B0_PWM2 0x10000000
2034#define MPC85xx_PMUXCR2_UART_RTS_B0_DSP_TCK 0x20000000
2035#define MPC85xx_PMUXCR2_UART_RTS_B0_GPIO43 0x30000000
2036#define MPC85xx_PMUXCR2_UART_CTS_B1_SIM_PD 0x04000000
2037#define MPC85xx_PMUXCR2_UART_CTS_B1_SRESET_B 0x08000000
2038#define MPC85xx_PMUXCR2_UART_CTS_B1_GPIO44 0x0C000000
2039#define MPC85xx_PMUXCR2_UART_RTS_B1_PPS_LED 0x01000000
2040#define MPC85xx_PMUXCR2_UART_RTS_B1_RSVD 0x02000000
2041#define MPC85xx_PMUXCR2_UART_RTS_B1_GPIO45 0x03000000
2042#define MPC85xx_PMUXCR2_TRIG_OUT_ASLEEP 0x00400000
2043#define MPC85xx_PMUXCR2_TRIG_OUT_DSP_TRST_B 0x00800000
2044#define MPC85xx_PMUXCR2_ANT1_TIMER5 0x00100000
2045#define MPC85xx_PMUXCR2_ANT1_TSEC_1588 0x00200000
2046#define MPC85xx_PMUXCR2_ANT1_GPIO95_19 0x00300000
2047#define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_MAX3_LOCK 0x00040000
2048#define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_RSVD 0x00080000
2049#define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_GPIO80_20 0x000C0000
2050#define MPC85xx_PMUXCR2_ANT1_DIO0_3_SPI3_CS0 0x00010000
2051#define MPC85xx_PMUXCR2_ANT1_DIO0_3_ANT2_DO_3 0x00020000
2052#define MPC85xx_PMUXCR2_ANT1_DIO0_3_GPIO81_84 0x00030000
2053#define MPC85xx_PMUXCR2_ANT1_DIO4_7_SPI4 0x00004000
2054#define MPC85xx_PMUXCR2_ANT1_DIO4_7_ANT2_DO4_7 0x00008000
2055#define MPC85xx_PMUXCR2_ANT1_DIO4_7_GPIO85_88 0x0000C000
2056#define MPC85xx_PMUXCR2_ANT1_DIO8_9_MAX2_1_LOCK 0x00001000
2057#define MPC85xx_PMUXCR2_ANT1_DIO8_9_ANT2_DO8_9 0x00002000
2058#define MPC85xx_PMUXCR2_ANT1_DIO8_9_GPIO21_22 0x00003000
2059#define MPC85xx_PMUXCR2_ANT1_DIO10_11_TIMER6_7 0x00000400
2060#define MPC85xx_PMUXCR2_ANT1_DIO10_11_ANT2_DO10_11 0x00000800
2061#define MPC85xx_PMUXCR2_ANT1_DIO10_11_GPIO23_24 0x00000C00
2062#define MPC85xx_PMUXCR2_ANT2_RSVD 0x00000100
2063#define MPC85xx_PMUXCR2_ANT2_GPO90_91_DMA 0x00000300
2064#define MPC85xx_PMUXCR2_ANT2_ENABLE_DIO0_10_USB 0x00000040
2065#define MPC85xx_PMUXCR2_ANT2_ENABLE_DIO0_10_GPIO 0x000000C0
2066#define MPC85xx_PMUXCR2_ANT2_DIO11_RSVD 0x00000010
2067#define MPC85xx_PMUXCR2_ANT2_DIO11_TIMER8 0x00000020
2068#define MPC85xx_PMUXCR2_ANT2_DIO11_GPIO61 0x00000030
2069#define MPC85xx_PMUXCR2_ANT3_AGC_GPO53 0x00000004
2070#define MPC85xx_PMUXCR2_ANT3_DO_TDM 0x00000001
2071#define MPC85xx_PMUXCR2_ANT3_DO_GPIO46_49 0x00000002
Prabhakar Kushwaha92543c22013-01-23 17:59:57 +00002072#endif
Prabhakar Kushwahabeebb882012-04-24 20:16:49 +00002073 u32 pmuxcr3;
York Suna80bdf72016-11-15 14:09:50 -08002074#if defined(CONFIG_ARCH_BSC9131)
Prabhakar Kushwahabeebb882012-04-24 20:16:49 +00002075#define MPC85xx_PMUXCR3_ANT3_DO4_5_TDM 0x40000000
2076#define MPC85xx_PMUXCR3_ANT3_DO4_5_GPIO_50_51 0x80000000
2077#define MPC85xx_PMUXCR3_ANT3_DO6_7_TRIG_IN_SRESET_B 0x10000000
2078#define MPC85xx_PMUXCR3_ANT3_DO6_7_GPIO_52_53 0x20000000
2079#define MPC85xx_PMUXCR3_ANT3_DO8_MCP_B 0x04000000
2080#define MPC85xx_PMUXCR3_ANT3_DO8_GPIO54 0x08000000
2081#define MPC85xx_PMUXCR3_ANT3_DO9_10_CKSTP_IN_OUT 0x01000000
2082#define MPC85xx_PMUXCR3_ANT3_DO9_10_GPIO55_56 0x02000000
2083#define MPC85xx_PMUXCR3_ANT3_DO11_IRQ_OUT 0x00400000
2084#define MPC85xx_PMUXCR3_ANT3_DO11_GPIO57 0x00800000
2085#define MPC85xx_PMUXCR3_SPI2_CS2_GPO93 0x00100000
2086#define MPC85xx_PMUXCR3_SPI2_CS3_GPO94 0x00040000
2087#define MPC85xx_PMUXCR3_ANT2_AGC_RSVD 0x00010000
2088#define MPC85xx_PMUXCR3_ANT2_GPO89 0x00030000
Prabhakar Kushwaha92543c22013-01-23 17:59:57 +00002089#endif
York Suna80bdf72016-11-15 14:09:50 -08002090#ifdef CONFIG_ARCH_BSC9132
Prabhakar Kushwaha92543c22013-01-23 17:59:57 +00002091#define MPC85xx_PMUXCR3_USB_SEL_MASK 0x0000ff00
2092#define MPC85xx_PMUXCR3_UART2_SEL 0x00005000
2093#define MPC85xx_PMUXCR3_UART3_SEL_MASK 0xc0000000
2094#define MPC85xx_PMUXCR3_UART3_SEL 0x40000000
2095#endif
Prabhakar Kushwahabeebb882012-04-24 20:16:49 +00002096 u32 pmuxcr4;
2097#else
Timur Tabib1508932010-05-20 12:45:39 -05002098 u8 res6[8];
Prabhakar Kushwahabeebb882012-04-24 20:16:49 +00002099#endif
Kumar Gala3d8d9132009-09-28 21:38:00 -05002100 u32 devdisr; /* Device disable control */
Ed Swarthout52b98522007-07-27 01:50:51 -05002101#define MPC85xx_DEVDISR_PCI1 0x80000000
2102#define MPC85xx_DEVDISR_PCI2 0x40000000
2103#define MPC85xx_DEVDISR_PCIE 0x20000000
2104#define MPC85xx_DEVDISR_LBC 0x08000000
2105#define MPC85xx_DEVDISR_PCIE2 0x04000000
2106#define MPC85xx_DEVDISR_PCIE3 0x02000000
2107#define MPC85xx_DEVDISR_SEC 0x01000000
2108#define MPC85xx_DEVDISR_SRIO 0x00080000
2109#define MPC85xx_DEVDISR_RMSG 0x00040000
Wolfgang Denka1be4762008-05-20 16:00:29 +02002110#define MPC85xx_DEVDISR_DDR 0x00010000
2111#define MPC85xx_DEVDISR_CPU 0x00008000
2112#define MPC85xx_DEVDISR_CPU0 MPC85xx_DEVDISR_CPU
2113#define MPC85xx_DEVDISR_TB 0x00004000
2114#define MPC85xx_DEVDISR_TB0 MPC85xx_DEVDISR_TB
2115#define MPC85xx_DEVDISR_CPU1 0x00002000
2116#define MPC85xx_DEVDISR_TB1 0x00001000
Ed Swarthout52b98522007-07-27 01:50:51 -05002117#define MPC85xx_DEVDISR_DMA 0x00000400
2118#define MPC85xx_DEVDISR_TSEC1 0x00000080
2119#define MPC85xx_DEVDISR_TSEC2 0x00000040
2120#define MPC85xx_DEVDISR_TSEC3 0x00000020
2121#define MPC85xx_DEVDISR_TSEC4 0x00000010
2122#define MPC85xx_DEVDISR_I2C 0x00000004
2123#define MPC85xx_DEVDISR_DUART 0x00000002
Kumar Gala3d8d9132009-09-28 21:38:00 -05002124 u8 res7[12];
2125 u32 powmgtcsr; /* Power management status & control */
2126 u8 res8[12];
2127 u32 mcpsumr; /* Machine check summary */
2128 u8 res9[12];
2129 u32 pvr; /* Processor version */
2130 u32 svr; /* System version */
Haiying Wang8cb2af72011-02-11 01:25:30 -06002131 u8 res10[8];
Kumar Gala3d8d9132009-09-28 21:38:00 -05002132 u32 rstcr; /* Reset control */
Tom Rini31f56052021-05-14 21:34:23 -04002133#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
Haiying Wang8cb2af72011-02-11 01:25:30 -06002134 u8 res11a[12];
2135 u32 iovselsr;
2136 u8 res11b[60];
2137 par_io_t qe_par_io[3];
2138 u8 res11c[1496];
Haiying Wangc4fc8832007-06-19 14:18:34 -04002139#else
Haiying Wang8cb2af72011-02-11 01:25:30 -06002140 u8 res11a[1868];
Haiying Wangc4fc8832007-06-19 14:18:34 -04002141#endif
Timur Tabib1508932010-05-20 12:45:39 -05002142 u32 clkdvdr; /* Clock Divide register */
Haiying Wang8cb2af72011-02-11 01:25:30 -06002143 u8 res12[1532];
Kumar Gala3d8d9132009-09-28 21:38:00 -05002144 u32 clkocr; /* Clock out select */
Haiying Wang8cb2af72011-02-11 01:25:30 -06002145 u8 res13[12];
Kumar Gala3d8d9132009-09-28 21:38:00 -05002146 u32 ddrdllcr; /* DDR DLL control */
Haiying Wang8cb2af72011-02-11 01:25:30 -06002147 u8 res14[12];
Kumar Gala3d8d9132009-09-28 21:38:00 -05002148 u32 lbcdllcr; /* LBC DLL control */
York Suna80bdf72016-11-15 14:09:50 -08002149#if defined(CONFIG_ARCH_BSC9131)
Prabhakar Kushwahabeebb882012-04-24 20:16:49 +00002150 u8 res15[12];
2151 u32 halt_req_mask;
2152#define HALTED_TO_HALT_REQ_MASK_0 0x80000000
2153 u8 res18[232];
2154#else
Haiying Wang8cb2af72011-02-11 01:25:30 -06002155 u8 res15[248];
Prabhakar Kushwahabeebb882012-04-24 20:16:49 +00002156#endif
Kumar Gala3d8d9132009-09-28 21:38:00 -05002157 u32 lbiuiplldcr0; /* LBIU PLL Debug Reg 0 */
2158 u32 lbiuiplldcr1; /* LBIU PLL Debug Reg 1 */
2159 u32 ddrioovcr; /* DDR IO Override Control */
2160 u32 tsec12ioovcr; /* eTSEC 1/2 IO override control */
2161 u32 tsec34ioovcr; /* eTSEC 3/4 IO override control */
Zhao Chenhui36ffc412011-01-27 19:02:47 +08002162 u8 res16[52];
2163 u32 sdhcdcr; /* SDHC debug control register */
2164 u8 res17[61592];
wdenk9c53f402003-10-15 23:53:47 +00002165} ccsr_gur_t;
Kumar Galad5740162009-09-16 09:43:12 -05002166#endif
2167
Zhao Chenhui36ffc412011-01-27 19:02:47 +08002168#define SDHCDCR_CD_INV 0x80000000 /* invert SDHC card detect */
2169
York Sun9650b632012-10-08 07:44:14 +00002170#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
2171#define MAX_SERDES 4
Tom Rinib4e60262021-05-14 21:34:22 -04002172#if defined(CONFIG_ARCH_T1024)
Paulo Zaneti7af45182017-05-05 11:08:18 -03002173#define SRDS_MAX_LANES 4
2174#else
York Sun7e0edbd2012-10-08 07:44:15 +00002175#define SRDS_MAX_LANES 8
Paulo Zaneti7af45182017-05-05 11:08:18 -03002176#endif
York Sun7e0edbd2012-10-08 07:44:15 +00002177#define SRDS_MAX_BANK 2
Kumar Gala2fb530b2009-10-15 23:22:10 -05002178typedef struct serdes_corenet {
2179 struct {
2180 u32 rstctl; /* Reset Control Register */
2181#define SRDS_RSTCTL_RST 0x80000000
2182#define SRDS_RSTCTL_RSTDONE 0x40000000
2183#define SRDS_RSTCTL_RSTERR 0x20000000
York Sun9650b632012-10-08 07:44:14 +00002184#define SRDS_RSTCTL_SWRST 0x10000000
Shaveta Leekha59d64272013-07-02 14:39:21 +05302185#define SRDS_RSTCTL_SDEN 0x00000020
2186#define SRDS_RSTCTL_SDRST_B 0x00000040
2187#define SRDS_RSTCTL_PLLRST_B 0x00000080
Shaveta Leekhad11523b2014-02-26 16:08:22 +05302188#define SRDS_RSTCTL_RSTERR_SHIFT 29
Kumar Gala2fb530b2009-10-15 23:22:10 -05002189 u32 pllcr0; /* PLL Control Register 0 */
York Sun9650b632012-10-08 07:44:14 +00002190#define SRDS_PLLCR0_POFF 0x80000000
2191#define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000
2192#define SRDS_PLLCR0_RFCK_SEL_100 0x00000000
2193#define SRDS_PLLCR0_RFCK_SEL_125 0x10000000
2194#define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000
2195#define SRDS_PLLCR0_RFCK_SEL_150 0x30000000
2196#define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000
2197#define SRDS_PLLCR0_RFCK_SEL_122_88 0x50000000
Shaveta Leekha7c0f5e82014-05-28 14:18:55 +05302198#define SRDS_PLLCR0_PLL_LCK 0x00800000
Shaveta Leekhad11523b2014-02-26 16:08:22 +05302199#define SRDS_PLLCR0_DCBIAS_OUT_EN 0x02000000
York Sun9650b632012-10-08 07:44:14 +00002200#define SRDS_PLLCR0_FRATE_SEL_MASK 0x000f0000
2201#define SRDS_PLLCR0_FRATE_SEL_5 0x00000000
Shaveta Leekha7c0f5e82014-05-28 14:18:55 +05302202#define SRDS_PLLCR0_FRATE_SEL_4_9152 0x00030000
York Sun9650b632012-10-08 07:44:14 +00002203#define SRDS_PLLCR0_FRATE_SEL_3_75 0x00050000
2204#define SRDS_PLLCR0_FRATE_SEL_5_15 0x00060000
2205#define SRDS_PLLCR0_FRATE_SEL_4 0x00070000
Shaveta Leekha7c0f5e82014-05-28 14:18:55 +05302206#define SRDS_PLLCR0_FRATE_SEL_3_125 0x00090000
2207#define SRDS_PLLCR0_FRATE_SEL_3_0 0x000a0000
2208#define SRDS_PLLCR0_FRATE_SEL_3_072 0x000c0000
Shaveta Leekhad11523b2014-02-26 16:08:22 +05302209#define SRDS_PLLCR0_DCBIAS_OVRD 0x000000F0
2210#define SRDS_PLLCR0_DCBIAS_OVRD_SHIFT 4
York Sun9650b632012-10-08 07:44:14 +00002211 u32 pllcr1; /* PLL Control Register 1 */
Shaveta Leekhad11523b2014-02-26 16:08:22 +05302212#define SRDS_PLLCR1_BCAP_EN 0x20000000
2213#define SRDS_PLLCR1_BCAP_OVD 0x10000000
2214#define SRDS_PLLCR1_PLL_FCAP 0x001F8000
2215#define SRDS_PLLCR1_PLL_FCAP_SHIFT 15
2216#define SRDS_PLLCR1_PLL_BWSEL 0x08000000
2217#define SRDS_PLLCR1_BYP_CAL 0x02000000
2218 u32 pllsr2; /* At 0x00c, PLL Status Register 2 */
2219#define SRDS_PLLSR2_BCAP_EN 0x00800000
2220#define SRDS_PLLSR2_BCAP_EN_SHIFT 23
2221#define SRDS_PLLSR2_FCAP 0x003F0000
2222#define SRDS_PLLSR2_FCAP_SHIFT 16
2223#define SRDS_PLLSR2_DCBIAS 0x000F0000
2224#define SRDS_PLLSR2_DCBIAS_SHIFT 16
York Sun9650b632012-10-08 07:44:14 +00002225 u32 pllcr3;
2226 u32 pllcr4;
2227 u8 res_18[0x20-0x18];
2228 } bank[2];
2229 u8 res_40[0x90-0x40];
2230 u32 srdstcalcr; /* 0x90 TX Calibration Control */
2231 u8 res_94[0xa0-0x94];
2232 u32 srdsrcalcr; /* 0xa0 RX Calibration Control */
2233 u8 res_a4[0xb0-0xa4];
2234 u32 srdsgr0; /* 0xb0 General Register 0 */
2235 u8 res_b4[0xe0-0xb4];
2236 u32 srdspccr0; /* 0xe0 Protocol Converter Config 0 */
2237 u32 srdspccr1; /* 0xe4 Protocol Converter Config 1 */
2238 u32 srdspccr2; /* 0xe8 Protocol Converter Config 2 */
2239 u32 srdspccr3; /* 0xec Protocol Converter Config 3 */
2240 u32 srdspccr4; /* 0xf0 Protocol Converter Config 4 */
2241 u8 res_f4[0x100-0xf4];
2242 struct {
2243 u32 lnpssr; /* 0x100, 0x120, ..., 0x1e0 */
2244 u8 res_104[0x120-0x104];
2245 } srdslnpssr[8];
2246 u8 res_200[0x800-0x200];
2247 struct {
2248 u32 gcr0; /* 0x800 General Control Register 0 */
2249 u32 gcr1; /* 0x804 General Control Register 1 */
2250 u32 gcr2; /* 0x808 General Control Register 2 */
2251 u32 res_80c;
2252 u32 recr0; /* 0x810 Receive Equalization Control */
2253 u32 res_814;
2254 u32 tecr0; /* 0x818 Transmit Equalization Control */
2255 u32 res_81c;
2256 u32 ttlcr0; /* 0x820 Transition Tracking Loop Ctrl 0 */
2257 u8 res_824[0x840-0x824];
2258 } lane[8]; /* Lane A, B, C, D, E, F, G, H */
2259 u8 res_a00[0x1000-0xa00]; /* from 0xa00 to 0xfff */
2260} serdes_corenet_t;
2261
2262#else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
2263
York Sun7e0edbd2012-10-08 07:44:15 +00002264#define SRDS_MAX_LANES 18
2265#define SRDS_MAX_BANK 3
York Sun9650b632012-10-08 07:44:14 +00002266typedef struct serdes_corenet {
2267 struct {
2268 u32 rstctl; /* Reset Control Register */
2269#define SRDS_RSTCTL_RST 0x80000000
2270#define SRDS_RSTCTL_RSTDONE 0x40000000
2271#define SRDS_RSTCTL_RSTERR 0x20000000
2272#define SRDS_RSTCTL_SDPD 0x00000020
2273 u32 pllcr0; /* PLL Control Register 0 */
York Sun75391c82012-10-08 07:44:12 +00002274#define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000
Timur Tabid5e13882012-10-05 11:09:19 +00002275#define SRDS_PLLCR0_PVCOCNT_EN 0x02000000
Kumar Gala13d1fe12010-04-07 10:39:46 -05002276#define SRDS_PLLCR0_RFCK_SEL_100 0x00000000
2277#define SRDS_PLLCR0_RFCK_SEL_125 0x10000000
2278#define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000
Kumar Galae38209e2011-02-09 02:00:08 +00002279#define SRDS_PLLCR0_RFCK_SEL_150 0x30000000
York Sun75391c82012-10-08 07:44:12 +00002280#define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000
Kumar Gala13d1fe12010-04-07 10:39:46 -05002281#define SRDS_PLLCR0_FRATE_SEL_MASK 0x00030000
2282#define SRDS_PLLCR0_FRATE_SEL_5 0x00000000
2283#define SRDS_PLLCR0_FRATE_SEL_6_25 0x00010000
Kumar Gala2fb530b2009-10-15 23:22:10 -05002284 u32 pllcr1; /* PLL Control Register 1 */
2285#define SRDS_PLLCR1_PLL_BWSEL 0x08000000
2286 u32 res[5];
2287 } bank[3];
2288 u32 res1[12];
2289 u32 srdstcalcr; /* TX Calibration Control */
2290 u32 res2[3];
2291 u32 srdsrcalcr; /* RX Calibration Control */
2292 u32 res3[3];
2293 u32 srdsgr0; /* General Register 0 */
2294 u32 res4[11];
2295 u32 srdspccr0; /* Protocol Converter Config 0 */
2296 u32 srdspccr1; /* Protocol Converter Config 1 */
2297 u32 srdspccr2; /* Protocol Converter Config 2 */
2298#define SRDS_PCCR2_RST_XGMII1 0x00800000
2299#define SRDS_PCCR2_RST_XGMII2 0x00400000
2300 u32 res5[197];
Timur Tabic5355dd2012-11-01 08:20:23 +00002301 struct serdes_lane {
Kumar Gala2fb530b2009-10-15 23:22:10 -05002302 u32 gcr0; /* General Control Register 0 */
2303#define SRDS_GCR0_RRST 0x00400000
2304#define SRDS_GCR0_1STLANE 0x00010000
Timur Tabid5e13882012-10-05 11:09:19 +00002305#define SRDS_GCR0_UOTHL 0x00100000
Kumar Gala2fb530b2009-10-15 23:22:10 -05002306 u32 gcr1; /* General Control Register 1 */
2307#define SRDS_GCR1_REIDL_CTL_MASK 0x001f0000
2308#define SRDS_GCR1_REIDL_CTL_PCIE 0x00100000
2309#define SRDS_GCR1_REIDL_CTL_SRIO 0x00000000
2310#define SRDS_GCR1_REIDL_CTL_SGMII 0x00040000
2311#define SRDS_GCR1_OPAD_CTL 0x04000000
2312 u32 res1[4];
2313 u32 tecr0; /* TX Equalization Control Reg 0 */
2314#define SRDS_TECR0_TEQ_TYPE_MASK 0x30000000
2315#define SRDS_TECR0_TEQ_TYPE_2LVL 0x10000000
2316 u32 res3;
2317 u32 ttlcr0; /* Transition Tracking Loop Ctrl 0 */
Emil Medveb01c81f2010-08-31 22:57:38 -05002318#define SRDS_TTLCR0_FLT_SEL_MASK 0x3f000000
Timur Tabicd586562012-11-01 08:20:22 +00002319#define SRDS_TTLCR0_FLT_SEL_KFR_26 0x10000000
2320#define SRDS_TTLCR0_FLT_SEL_KPH_28 0x08000000
Timur Tabi7ace5072011-04-14 15:37:06 -05002321#define SRDS_TTLCR0_FLT_SEL_750PPM 0x03000000
Emil Medveb01c81f2010-08-31 22:57:38 -05002322#define SRDS_TTLCR0_PM_DIS 0x00004000
Timur Tabicd586562012-11-01 08:20:22 +00002323#define SRDS_TTLCR0_FREQOVD_EN 0x00000001
Kumar Gala2fb530b2009-10-15 23:22:10 -05002324 u32 res4[7];
2325 } lane[24];
2326 u32 res6[384];
2327} serdes_corenet_t;
York Sun9650b632012-10-08 07:44:14 +00002328#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
Kumar Gala2fb530b2009-10-15 23:22:10 -05002329
2330enum {
2331 FSL_SRDS_B1_LANE_A = 0,
2332 FSL_SRDS_B1_LANE_B = 1,
2333 FSL_SRDS_B1_LANE_C = 2,
2334 FSL_SRDS_B1_LANE_D = 3,
2335 FSL_SRDS_B1_LANE_E = 4,
2336 FSL_SRDS_B1_LANE_F = 5,
2337 FSL_SRDS_B1_LANE_G = 6,
2338 FSL_SRDS_B1_LANE_H = 7,
2339 FSL_SRDS_B1_LANE_I = 8,
2340 FSL_SRDS_B1_LANE_J = 9,
2341 FSL_SRDS_B2_LANE_A = 16,
2342 FSL_SRDS_B2_LANE_B = 17,
2343 FSL_SRDS_B2_LANE_C = 18,
2344 FSL_SRDS_B2_LANE_D = 19,
2345 FSL_SRDS_B3_LANE_A = 20,
2346 FSL_SRDS_B3_LANE_B = 21,
2347 FSL_SRDS_B3_LANE_C = 22,
2348 FSL_SRDS_B3_LANE_D = 23,
2349};
2350
Kumar Gala74e78b62010-04-28 04:02:21 -05002351typedef struct ccsr_pme {
2352 u8 res0[0x804];
2353 u32 liodnbr; /* LIODN Base Register */
2354 u8 res1[0x1f8];
2355 u32 srcidr; /* Source ID Register */
2356 u8 res2[8];
2357 u32 liodnr; /* LIODN Register */
2358 u8 res3[0x1e8];
2359 u32 pm_ip_rev_1; /* PME IP Block Revision Reg 1*/
2360 u32 pm_ip_rev_2; /* PME IP Block Revision Reg 1*/
2361 u8 res4[0x400];
2362} ccsr_pme_t;
2363
Aneesh Bansal4b636c32016-01-22 17:05:59 +05302364struct ccsr_pamu {
2365 u32 ppbah;
2366 u32 ppbal;
2367 u32 pplah;
2368 u32 pplal;
2369 u32 spbah;
2370 u32 spbal;
2371 u32 splah;
2372 u32 splal;
2373 u32 obah;
2374 u32 obal;
2375 u32 olah;
2376 u32 olal;
2377};
2378
Kumar Gala9d8e8132011-09-10 10:44:13 -05002379#ifdef CONFIG_SYS_FSL_RAID_ENGINE
2380struct ccsr_raide {
2381 u8 res0[0x543];
2382 u32 liodnbr; /* LIODN Base Register */
2383 u8 res1[0xab8];
2384 struct {
2385 struct {
2386 u32 cfg0; /* cfg register 0 */
2387 u32 cfg1; /* cfg register 1 */
2388 u8 res1[0x3f8];
2389 } ring[2];
2390 u8 res[0x800];
2391 } jq[2];
2392};
2393#endif
2394
Kumar Gala4eb3c372011-10-14 13:28:52 -05002395#ifdef CONFIG_SYS_DPAA_RMAN
2396struct ccsr_rman {
2397 u8 res0[0xf64];
2398 u32 mmliodnbr; /* Message Manager LIODN Base Register */
2399 u32 mmitar; /* RMAN Inbound Translation Address Register */
2400 u32 mmitdr; /* RMAN Inbound Translation Data Register */
2401 u8 res4[0x1f090];
2402};
2403#endif
2404
Andy Fleming81177ad2012-10-08 07:44:18 +00002405#ifdef CONFIG_SYS_PMAN
2406struct ccsr_pman {
2407 u8 res_00[0x40];
2408 u32 poes1; /* PMAN Operation Error Status Register 1 */
2409 u32 poes2; /* PMAN Operation Error Status Register 2 */
2410 u32 poeah; /* PMAN Operation Error Address High */
2411 u32 poeal; /* PMAN Operation Error Address Low */
2412 u8 res_50[0x50];
2413 u32 pr1; /* PMAN Revision Register 1 */
2414 u32 pr2; /* PMAN Revision Register 2 */
2415 u8 res_a8[0x8];
2416 u32 pcap; /* PMAN Capabilities Register */
2417 u8 res_b4[0xc];
2418 u32 pc1; /* PMAN Control Register 1 */
2419 u32 pc2; /* PMAN Control Register 2 */
2420 u32 pc3; /* PMAN Control Register 3 */
2421 u32 pc4; /* PMAN Control Register 4 */
2422 u32 pc5; /* PMAN Control Register 5 */
2423 u32 pc6; /* PMAN Control Register 6 */
2424 u8 res_d8[0x8];
2425 u32 ppa1; /* PMAN Prefetch Attributes Register 1 */
2426 u32 ppa2; /* PMAN Prefetch Attributes Register 2 */
2427 u8 res_e8[0x8];
2428 u32 pics; /* PMAN Interrupt Control and Status */
2429 u8 res_f4[0xf0c];
2430};
2431#endif
2432
Kumar Galad5740162009-09-16 09:43:12 -05002433#ifdef CONFIG_FSL_CORENET
2434#define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000
Andy Fleming81177ad2012-10-08 07:44:18 +00002435#ifdef CONFIG_SYS_PMAN
2436#define CONFIG_SYS_FSL_CORENET_PMAN1_OFFSET 0x4000
2437#define CONFIG_SYS_FSL_CORENET_PMAN2_OFFSET 0x5000
2438#define CONFIG_SYS_FSL_CORENET_PMAN3_OFFSET 0x6000
2439#endif
Andy Fleming992562c2012-10-23 19:03:46 -05002440#define CONFIG_SYS_MPC8xxx_DDR_OFFSET 0x8000
2441#define CONFIG_SYS_MPC8xxx_DDR2_OFFSET 0x9000
2442#define CONFIG_SYS_MPC8xxx_DDR3_OFFSET 0xA000
Kumar Galad5740162009-09-16 09:43:12 -05002443#define CONFIG_SYS_FSL_CORENET_CLK_OFFSET 0xE1000
2444#define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET 0xE2000
Shaveta Leekha7c0f5e82014-05-28 14:18:55 +05302445#ifdef CONFIG_SYS_FSL_SFP_VER_3_0
2446/* In SFPv3, OSPR register is now at offset 0x200.
2447 * * So directly mapping sfp register map to this address */
2448#define CONFIG_SYS_OSPR_OFFSET 0x200
2449#define CONFIG_SYS_SFP_OFFSET (0xE8000 + CONFIG_SYS_OSPR_OFFSET)
2450#else
2451#define CONFIG_SYS_SFP_OFFSET 0xE8000
2452#endif
Kumar Gala2fb530b2009-10-15 23:22:10 -05002453#define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000
Timur Tabid5e13882012-10-05 11:09:19 +00002454#define CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET 0xEB000
Shaohui Xiea24a6aa2014-06-27 14:39:31 +08002455#define CONFIG_SYS_FSL_CORENET_SERDES3_OFFSET 0xEC000
2456#define CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET 0xED000
Becky Bruce475c2f92009-11-17 21:10:21 -06002457#define CONFIG_SYS_FSL_CPC_OFFSET 0x10000
Priyanka Jain794c1c72014-01-30 15:39:58 +05302458#define CONFIG_SYS_FSL_SCFG_OFFSET 0xFC000
Aneesh Bansal4b636c32016-01-22 17:05:59 +05302459#define CONFIG_SYS_FSL_PAMU_OFFSET 0x20000
Kumar Gala74e78b62010-04-28 04:02:21 -05002460#define CONFIG_SYS_MPC85xx_DMA1_OFFSET 0x100000
2461#define CONFIG_SYS_MPC85xx_DMA2_OFFSET 0x101000
Shengzhou Liuf305cd22013-11-22 17:39:10 +08002462#define CONFIG_SYS_MPC85xx_DMA3_OFFSET 0x102000
Kumar Gala74e78b62010-04-28 04:02:21 -05002463#define CONFIG_SYS_MPC85xx_DMA_OFFSET CONFIG_SYS_MPC85xx_DMA1_OFFSET
Kumar Galad5740162009-09-16 09:43:12 -05002464#define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x110000
2465#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x114000
2466#define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x124000
Kumar Gala45ff8002012-08-17 08:20:24 +00002467#define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x124000
Kumar Galad5740162009-09-16 09:43:12 -05002468#define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000
Sandeep Singh4fb16a12014-06-05 18:49:57 +05302469#define CONFIG_SYS_MPC85xx_TDM_OFFSET 0x185000
Zhao Qiangb818ba22014-03-21 16:21:45 +08002470#define CONFIG_SYS_MPC85xx_QE_OFFSET 0x140000
Kumar Gala4eb3c372011-10-14 13:28:52 -05002471#define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET 0x1e0000
York Sunfda566d2016-11-18 11:56:57 -08002472#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && !defined(CONFIG_ARCH_B4860) && \
2473 !defined(CONFIG_ARCH_B4420)
York Sun9941a222012-10-08 07:44:19 +00002474#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x240000
2475#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x250000
2476#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x260000
2477#define CONFIG_SYS_MPC85xx_PCIE4_OFFSET 0x270000
2478#else
Kumar Gala74e78b62010-04-28 04:02:21 -05002479#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x200000
2480#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x201000
2481#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x202000
2482#define CONFIG_SYS_MPC85xx_PCIE4_OFFSET 0x203000
York Sun9941a222012-10-08 07:44:19 +00002483#endif
Kumar Gala74e78b62010-04-28 04:02:21 -05002484#define CONFIG_SYS_MPC85xx_USB1_OFFSET 0x210000
2485#define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x211000
Roy Zang6d6a0e12011-04-13 00:08:51 -05002486#define CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET 0x214000
2487#define CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET 0x214100
Kumar Gala74e78b62010-04-28 04:02:21 -05002488#define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x220000
2489#define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x221000
Kim Phillips1b625492010-06-01 12:24:34 -05002490#define CONFIG_SYS_FSL_SEC_OFFSET 0x300000
Ruchika Guptaac1b2692014-10-15 11:35:30 +05302491#define CONFIG_SYS_FSL_JR0_OFFSET 0x301000
gaurav rana8b5ea652015-02-27 09:46:17 +05302492#define CONFIG_SYS_SEC_MON_OFFSET 0x314000
Kumar Gala74e78b62010-04-28 04:02:21 -05002493#define CONFIG_SYS_FSL_CORENET_PME_OFFSET 0x316000
Haiying Wang325a12f2011-01-20 22:26:31 +00002494#define CONFIG_SYS_FSL_QMAN_OFFSET 0x318000
2495#define CONFIG_SYS_FSL_BMAN_OFFSET 0x31a000
Kumar Gala9d8e8132011-09-10 10:44:13 -05002496#define CONFIG_SYS_FSL_RAID_ENGINE_OFFSET 0x320000
Kumar Gala74e78b62010-04-28 04:02:21 -05002497#define CONFIG_SYS_FSL_FM1_OFFSET 0x400000
2498#define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x488000
2499#define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x489000
2500#define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET 0x48a000
2501#define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET 0x48b000
2502#define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET 0x48c000
Andy Fleming81177ad2012-10-08 07:44:18 +00002503#define CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET 0x48d000
Kumar Gala74e78b62010-04-28 04:02:21 -05002504#define CONFIG_SYS_FSL_FM1_RX0_10G_OFFSET 0x490000
Andy Fleming81177ad2012-10-08 07:44:18 +00002505#define CONFIG_SYS_FSL_FM1_RX1_10G_OFFSET 0x491000
Kumar Gala74e78b62010-04-28 04:02:21 -05002506#define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0x4e0000
2507#define CONFIG_SYS_FSL_FM2_OFFSET 0x500000
2508#define CONFIG_SYS_FSL_FM2_RX0_1G_OFFSET 0x588000
2509#define CONFIG_SYS_FSL_FM2_RX1_1G_OFFSET 0x589000
2510#define CONFIG_SYS_FSL_FM2_RX2_1G_OFFSET 0x58a000
2511#define CONFIG_SYS_FSL_FM2_RX3_1G_OFFSET 0x58b000
2512#define CONFIG_SYS_FSL_FM2_RX4_1G_OFFSET 0x58c000
Andy Fleming81177ad2012-10-08 07:44:18 +00002513#define CONFIG_SYS_FSL_FM2_RX5_1G_OFFSET 0x58d000
Kumar Gala74e78b62010-04-28 04:02:21 -05002514#define CONFIG_SYS_FSL_FM2_RX0_10G_OFFSET 0x590000
Andy Fleming81177ad2012-10-08 07:44:18 +00002515#define CONFIG_SYS_FSL_FM2_RX1_10G_OFFSET 0x591000
York Sunc3d87b12012-10-08 07:44:08 +00002516#define CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET 0xC20000
Kumar Galad5740162009-09-16 09:43:12 -05002517#else
2518#define CONFIG_SYS_MPC85xx_ECM_OFFSET 0x0000
Andy Fleming992562c2012-10-23 19:03:46 -05002519#define CONFIG_SYS_MPC8xxx_DDR_OFFSET 0x2000
Kumar Galad5740162009-09-16 09:43:12 -05002520#define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x5000
Andy Fleming992562c2012-10-23 19:03:46 -05002521#define CONFIG_SYS_MPC8xxx_DDR2_OFFSET 0x6000
Kumar Galad5740162009-09-16 09:43:12 -05002522#define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x7000
Kumar Gala17ed6a22010-07-08 22:23:54 -05002523#define CONFIG_SYS_MPC85xx_PCI1_OFFSET 0x8000
Kumar Galad5740162009-09-16 09:43:12 -05002524#define CONFIG_SYS_MPC85xx_PCIX_OFFSET 0x8000
Kumar Gala17ed6a22010-07-08 22:23:54 -05002525#define CONFIG_SYS_MPC85xx_PCI2_OFFSET 0x9000
Kumar Galad5740162009-09-16 09:43:12 -05002526#define CONFIG_SYS_MPC85xx_PCIX2_OFFSET 0x9000
Kumar Gala17ed6a22010-07-08 22:23:54 -05002527#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0xa000
2528#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x9000
Tom Rinie1ef7082021-05-14 21:34:25 -04002529#if defined(CONFIG_ARCH_P2020)
Kumar Gala17ed6a22010-07-08 22:23:54 -05002530#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x8000
2531#else
2532#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0xb000
2533#endif
Kumar Galad5740162009-09-16 09:43:12 -05002534#define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0xF000
2535#define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x18000
2536#define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x19000
Dipen Dudhat00c42942011-01-20 16:29:35 +05302537#define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x1e000
Kumar Galad5740162009-09-16 09:43:12 -05002538#define CONFIG_SYS_MPC85xx_L2_OFFSET 0x20000
2539#define CONFIG_SYS_MPC85xx_DMA_OFFSET 0x21000
ramneek mehresh16b08062013-09-12 16:35:49 +05302540#define CONFIG_SYS_MPC85xx_USB1_OFFSET 0x22000
Ira W. Snydera07c0512011-11-23 08:25:58 -08002541#define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x23000
Sriram Dash1ae7e4c2016-08-17 11:47:53 +05302542#define CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET 0xE5000
2543#define CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET 0xE5100
Kumar Gala2e972932009-10-31 11:23:41 -05002544#ifdef CONFIG_TSECV2
2545#define CONFIG_SYS_TSEC1_OFFSET 0xB0000
Mingkai Hu1a258072013-07-04 17:30:36 +08002546#elif defined(CONFIG_TSECV2_1)
2547#define CONFIG_SYS_TSEC1_OFFSET 0x10000
Kumar Gala2e972932009-10-31 11:23:41 -05002548#else
Sandeep Gopalpetb5541ef2009-10-31 00:35:04 +05302549#define CONFIG_SYS_TSEC1_OFFSET 0x24000
Kumar Gala2e972932009-10-31 11:23:41 -05002550#endif
2551#define CONFIG_SYS_MDIO1_OFFSET 0x24000
Kumar Galad5740162009-09-16 09:43:12 -05002552#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000
York Sun4119aee2016-11-15 18:44:22 -08002553#if defined(CONFIG_ARCH_C29X)
Mingkai Hu1a258072013-07-04 17:30:36 +08002554#define CONFIG_SYS_FSL_SEC_OFFSET 0x80000
Ruchika Guptaac1b2692014-10-15 11:35:30 +05302555#define CONFIG_SYS_FSL_JR0_OFFSET 0x81000
Mingkai Hu1a258072013-07-04 17:30:36 +08002556#else
Vakul Garg90a7f9f2013-01-23 22:52:31 +00002557#define CONFIG_SYS_FSL_SEC_OFFSET 0x30000
Ruchika Guptaac1b2692014-10-15 11:35:30 +05302558#define CONFIG_SYS_FSL_JR0_OFFSET 0x31000
Mingkai Hu1a258072013-07-04 17:30:36 +08002559#endif
Kumar Galad5740162009-09-16 09:43:12 -05002560#define CONFIG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100
2561#define CONFIG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000
gaurav rana8b5ea652015-02-27 09:46:17 +05302562#define CONFIG_SYS_SEC_MON_OFFSET 0xE6000
Ruchika Gupta8ca8d822010-12-15 17:02:08 +00002563#define CONFIG_SYS_SFP_OFFSET 0xE7000
Roy Zang1de20b02011-02-03 22:14:19 -06002564#define CONFIG_SYS_FSL_QMAN_OFFSET 0x88000
2565#define CONFIG_SYS_FSL_BMAN_OFFSET 0x8a000
2566#define CONFIG_SYS_FSL_FM1_OFFSET 0x100000
2567#define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x188000
2568#define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x189000
2569#define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0x1e0000
Kumar Galad5740162009-09-16 09:43:12 -05002570#endif
2571
2572#define CONFIG_SYS_MPC85xx_PIC_OFFSET 0x40000
2573#define CONFIG_SYS_MPC85xx_GUTS_OFFSET 0xE0000
Liu Gang4cc85322012-03-08 00:33:17 +00002574#define CONFIG_SYS_FSL_SRIO_OFFSET 0xC0000
wdenk9c53f402003-10-15 23:53:47 +00002575
Becky Bruce475c2f92009-11-17 21:10:21 -06002576#define CONFIG_SYS_FSL_CPC_ADDR \
2577 (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET)
Priyanka Jain794c1c72014-01-30 15:39:58 +05302578#define CONFIG_SYS_FSL_SCFG_ADDR \
2579 (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_SCFG_OFFSET)
Haiying Wang325a12f2011-01-20 22:26:31 +00002580#define CONFIG_SYS_FSL_QMAN_ADDR \
2581 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_QMAN_OFFSET)
2582#define CONFIG_SYS_FSL_BMAN_ADDR \
2583 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_BMAN_OFFSET)
Kumar Gala74e78b62010-04-28 04:02:21 -05002584#define CONFIG_SYS_FSL_CORENET_PME_ADDR \
2585 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_PME_OFFSET)
Kumar Gala9d8e8132011-09-10 10:44:13 -05002586#define CONFIG_SYS_FSL_RAID_ENGINE_ADDR \
2587 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_RAID_ENGINE_OFFSET)
Kumar Gala4eb3c372011-10-14 13:28:52 -05002588#define CONFIG_SYS_FSL_CORENET_RMAN_ADDR \
2589 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RMAN_OFFSET)
Kumar Gala3d8d9132009-09-28 21:38:00 -05002590#define CONFIG_SYS_MPC85xx_GUTS_ADDR \
2591 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET)
2592#define CONFIG_SYS_FSL_CORENET_CCM_ADDR \
2593 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CCM_OFFSET)
2594#define CONFIG_SYS_FSL_CORENET_CLK_ADDR \
2595 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CLK_OFFSET)
2596#define CONFIG_SYS_FSL_CORENET_RCPM_ADDR \
2597 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RCPM_OFFSET)
2598#define CONFIG_SYS_MPC85xx_ECM_ADDR \
2599 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ECM_OFFSET)
York Sunf0626592013-09-30 09:22:09 -07002600#define CONFIG_SYS_FSL_DDR_ADDR \
Andy Fleming992562c2012-10-23 19:03:46 -05002601 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET)
York Sunf0626592013-09-30 09:22:09 -07002602#define CONFIG_SYS_FSL_DDR2_ADDR \
Andy Fleming992562c2012-10-23 19:03:46 -05002603 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR2_OFFSET)
York Sunf0626592013-09-30 09:22:09 -07002604#define CONFIG_SYS_FSL_DDR3_ADDR \
Andy Fleming992562c2012-10-23 19:03:46 -05002605 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR3_OFFSET)
Becky Bruce0d4cee12010-06-17 11:37:20 -05002606#define CONFIG_SYS_LBC_ADDR \
Kumar Gala3d8d9132009-09-28 21:38:00 -05002607 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET)
Dipen Dudhat00c42942011-01-20 16:29:35 +05302608#define CONFIG_SYS_IFC_ADDR \
2609 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_IFC_OFFSET)
Kumar Gala3d8d9132009-09-28 21:38:00 -05002610#define CONFIG_SYS_MPC85xx_ESPI_ADDR \
2611 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESPI_OFFSET)
2612#define CONFIG_SYS_MPC85xx_PCIX_ADDR \
2613 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX_OFFSET)
2614#define CONFIG_SYS_MPC85xx_PCIX2_ADDR \
2615 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX2_OFFSET)
2616#define CONFIG_SYS_MPC85xx_GPIO_ADDR \
2617 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GPIO_OFFSET)
2618#define CONFIG_SYS_MPC85xx_SATA1_ADDR \
2619 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA1_OFFSET)
2620#define CONFIG_SYS_MPC85xx_SATA2_ADDR \
2621 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA2_OFFSET)
2622#define CONFIG_SYS_MPC85xx_L2_ADDR \
2623 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_L2_OFFSET)
2624#define CONFIG_SYS_MPC85xx_DMA_ADDR \
2625 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DMA_OFFSET)
2626#define CONFIG_SYS_MPC85xx_ESDHC_ADDR \
2627 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESDHC_OFFSET)
Kim Phillips2ecbfeb2010-08-09 18:39:57 -05002628#define CONFIG_SYS_MPC8xxx_PIC_ADDR \
Kumar Gala3d8d9132009-09-28 21:38:00 -05002629 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET)
Kumar Gala3d8d9132009-09-28 21:38:00 -05002630#define CONFIG_SYS_MPC85xx_SERDES1_ADDR \
Prabhakarb4dccf82011-01-18 09:03:59 +05302631 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES1_OFFSET)
Kumar Gala3d8d9132009-09-28 21:38:00 -05002632#define CONFIG_SYS_MPC85xx_SERDES2_ADDR \
2633 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET)
Kumar Gala2fb530b2009-10-15 23:22:10 -05002634#define CONFIG_SYS_FSL_CORENET_SERDES_ADDR \
2635 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET)
Timur Tabid5e13882012-10-05 11:09:19 +00002636#define CONFIG_SYS_FSL_CORENET_SERDES2_ADDR \
2637 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET)
Shaohui Xiea24a6aa2014-06-27 14:39:31 +08002638#define CONFIG_SYS_FSL_CORENET_SERDES3_ADDR \
2639 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES3_OFFSET)
2640#define CONFIG_SYS_FSL_CORENET_SERDES4_ADDR \
2641 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET)
ramneek mehresh16b08062013-09-12 16:35:49 +05302642#define CONFIG_SYS_MPC85xx_USB1_ADDR \
2643 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_OFFSET)
2644#define CONFIG_SYS_MPC85xx_USB2_ADDR \
2645 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB2_OFFSET)
Roy Zang6d6a0e12011-04-13 00:08:51 -05002646#define CONFIG_SYS_MPC85xx_USB1_PHY_ADDR \
2647 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET)
2648#define CONFIG_SYS_MPC85xx_USB2_PHY_ADDR \
2649 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET)
Kim Phillips1b625492010-06-01 12:24:34 -05002650#define CONFIG_SYS_FSL_SEC_ADDR \
2651 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
Ruchika Guptaac1b2692014-10-15 11:35:30 +05302652#define CONFIG_SYS_FSL_JR0_ADDR \
2653 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
Kumar Gala74e78b62010-04-28 04:02:21 -05002654#define CONFIG_SYS_FSL_FM1_ADDR \
2655 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET)
2656#define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR \
2657 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET)
2658#define CONFIG_SYS_FSL_FM2_ADDR \
2659 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM2_OFFSET)
Liu Gang4cc85322012-03-08 00:33:17 +00002660#define CONFIG_SYS_FSL_SRIO_ADDR \
2661 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SRIO_OFFSET)
Aneesh Bansal4b636c32016-01-22 17:05:59 +05302662#define CONFIG_SYS_PAMU_ADDR \
2663 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_PAMU_OFFSET)
Kumar Galacd113a02007-11-28 00:36:33 -06002664
Kumar Gala17ed6a22010-07-08 22:23:54 -05002665#define CONFIG_SYS_PCI1_ADDR \
2666 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI1_OFFSET)
2667#define CONFIG_SYS_PCI2_ADDR \
2668 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI2_OFFSET)
2669#define CONFIG_SYS_PCIE1_ADDR \
2670 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE1_OFFSET)
2671#define CONFIG_SYS_PCIE2_ADDR \
2672 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE2_OFFSET)
2673#define CONFIG_SYS_PCIE3_ADDR \
2674 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE3_OFFSET)
Kumar Gala74e78b62010-04-28 04:02:21 -05002675#define CONFIG_SYS_PCIE4_ADDR \
2676 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE4_OFFSET)
Kumar Gala17ed6a22010-07-08 22:23:54 -05002677
Shaveta Leekha7c0f5e82014-05-28 14:18:55 +05302678#define CONFIG_SYS_SFP_ADDR \
2679 (CONFIG_SYS_IMMR + CONFIG_SYS_SFP_OFFSET)
2680
gaurav rana8b5ea652015-02-27 09:46:17 +05302681#define CONFIG_SYS_SEC_MON_ADDR \
2682 (CONFIG_SYS_IMMR + CONFIG_SYS_SEC_MON_OFFSET)
2683
Sandeep Gopalpetb5541ef2009-10-31 00:35:04 +05302684#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
2685#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
2686
York Sunc3d87b12012-10-08 07:44:08 +00002687#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
2688struct ccsr_cluster_l2 {
2689 u32 l2csr0; /* 0x000 L2 cache control and status register 0 */
2690 u32 l2csr1; /* 0x004 L2 cache control and status register 1 */
2691 u32 l2cfg0; /* 0x008 L2 cache configuration register 0 */
2692 u8 res_0c[500];/* 0x00c - 0x1ff */
2693 u32 l2pir0; /* 0x200 L2 cache partitioning ID register 0 */
2694 u8 res_204[4];
2695 u32 l2par0; /* 0x208 L2 cache partitioning allocation register 0 */
2696 u32 l2pwr0; /* 0x20c L2 cache partitioning way register 0 */
2697 u32 l2pir1; /* 0x210 L2 cache partitioning ID register 1 */
2698 u8 res_214[4];
2699 u32 l2par1; /* 0x218 L2 cache partitioning allocation register 1 */
2700 u32 l2pwr1; /* 0x21c L2 cache partitioning way register 1 */
2701 u32 u2pir2; /* 0x220 L2 cache partitioning ID register 2 */
2702 u8 res_224[4];
2703 u32 l2par2; /* 0x228 L2 cache partitioning allocation register 2 */
2704 u32 l2pwr2; /* 0x22c L2 cache partitioning way register 2 */
2705 u32 l2pir3; /* 0x230 L2 cache partitioning ID register 3 */
2706 u8 res_234[4];
2707 u32 l2par3; /* 0x238 L2 cache partitining allocation register 3 */
2708 u32 l2pwr3; /* 0x23c L2 cache partitining way register 3 */
2709 u32 l2pir4; /* 0x240 L2 cache partitioning ID register 3 */
2710 u8 res244[4];
2711 u32 l2par4; /* 0x248 L2 cache partitioning allocation register 3 */
2712 u32 l2pwr4; /* 0x24c L2 cache partitioning way register 3 */
2713 u32 l2pir5; /* 0x250 L2 cache partitioning ID register 3 */
2714 u8 res_254[4];
2715 u32 l2par5; /* 0x258 L2 cache partitioning allocation register 3 */
2716 u32 l2pwr5; /* 0x25c L2 cache partitioning way register 3 */
2717 u32 l2pir6; /* 0x260 L2 cache partitioning ID register 3 */
2718 u8 res_264[4];
2719 u32 l2par6; /* 0x268 L2 cache partitioning allocation register 3 */
2720 u32 l2pwr6; /* 0x26c L2 cache partitioning way register 3 */
2721 u32 l2pir7; /* 0x270 L2 cache partitioning ID register 3 */
2722 u8 res274[4];
2723 u32 l2par7; /* 0x278 L2 cache partitioning allocation register 3 */
2724 u32 l2pwr7; /* 0x27c L2 cache partitioning way register 3 */
2725 u8 res_280[0xb80]; /* 0x280 - 0xdff */
2726 u32 l2errinjhi; /* 0xe00 L2 cache error injection mask high */
2727 u32 l2errinjlo; /* 0xe04 L2 cache error injection mask low */
2728 u32 l2errinjctl;/* 0xe08 L2 cache error injection control */
2729 u8 res_e0c[20]; /* 0xe0c - 0x01f */
2730 u32 l2captdatahi; /* 0xe20 L2 cache error capture data high */
2731 u32 l2captdatalo; /* 0xe24 L2 cache error capture data low */
2732 u32 l2captecc; /* 0xe28 L2 cache error capture ECC syndrome */
2733 u8 res_e2c[20]; /* 0xe2c - 0xe3f */
2734 u32 l2errdet; /* 0xe40 L2 cache error detect */
2735 u32 l2errdis; /* 0xe44 L2 cache error disable */
2736 u32 l2errinten; /* 0xe48 L2 cache error interrupt enable */
2737 u32 l2errattr; /* 0xe4c L2 cache error attribute */
2738 u32 l2erreaddr; /* 0xe50 L2 cache error extended address */
2739 u32 l2erraddr; /* 0xe54 L2 cache error address */
2740 u32 l2errctl; /* 0xe58 L2 cache error control */
2741};
2742#define CONFIG_SYS_FSL_CLUSTER_1_L2 \
2743 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET)
2744#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
Xuleicf4f4932013-03-11 17:56:34 +00002745
2746#define CONFIG_SYS_DCSR_DCFG_OFFSET 0X20000
2747struct dcsr_dcfg_regs {
2748 u8 res_0[0x520];
2749 u32 ecccr1;
2750#define DCSR_DCFG_ECC_DISABLE_USB1 0x00008000
2751#define DCSR_DCFG_ECC_DISABLE_USB2 0x00004000
2752 u8 res_524[0x1000 - 0x524]; /* 0x524 - 0x1000 */
2753};
Tang Yuantian66f739d2014-03-26 16:08:05 +08002754
2755#define CONFIG_SYS_MPC85xx_SCFG \
2756 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SCFG_OFFSET)
2757#define CONFIG_SYS_MPC85xx_SCFG_OFFSET 0xfc000
2758/* The supplement configuration unit register */
2759struct ccsr_scfg {
2760 u32 dpslpcr; /* 0x000 Deep Sleep Control register */
2761 u32 usb1dpslpcsr;/* 0x004 USB1 Deep Sleep Control Status register */
2762 u32 usb2dpslpcsr;/* 0x008 USB2 Deep Sleep Control Status register */
2763 u32 fmclkdpslpcr;/* 0x00c FM Clock Deep Sleep Control register */
2764 u32 res1[4];
2765 u32 esgmiiselcr;/* 0x020 Ethernet Switch SGMII Select Control reg */
2766 u32 res2;
2767 u32 pixclkcr; /* 0x028 Pixel Clock Control register */
2768 u32 res3[245];
2769 u32 qeioclkcr; /* 0x400 QUICC Engine IO Clock Control register */
2770 u32 emiiocr; /* 0x404 EMI MDIO Control Register */
2771 u32 sdhciovselcr;/* 0x408 SDHC IO VSEL Control register */
2772 u32 qmifrstcr; /* 0x40c QMAN Interface Reset Control register */
2773 u32 res4[60];
2774 u32 sparecr[8]; /* 0x500 Spare Control register(0-7) */
2775};
wdenk9c53f402003-10-15 23:53:47 +00002776#endif /*__IMMAP_85xx__*/