| commit | bfcd6c3e0bc2aa3f472b81871ed0caa94c58d3bc | [log] [tgz] |
|---|---|---|
| author | Jason Jin <Jason.jin@freescale.com> | Sat Sep 27 14:40:57 2008 +0800 |
| committer | Andrew Fleming-AFLEMING <afleming@freescale.com> | Tue Oct 07 15:37:08 2008 -0500 |
| tree | 38f34ae2b3cdb04300ee0c5afb08e9317c2e5d05 | |
| parent | 64df226a8311aace1e4527e5855fd5786d16371f [diff] |
Fix the incorrect DDR clk freq reporting on 8536DS On 8536DS board, When the DDR clk is set async mode(SW3[6:8] != 111), The display is still sync mode DDR freq. This patch try to fix this. The display DDR freq is now the actual freq in both sync and async mode. Signed-off-by: Jason Jin <Jason.jin@freescale.com>