powerpc/85xx: Refactor Qman/Portal support to be shared between SoCs
There are some differences between CoreNet (P2040, P3041, P5020, P4080)
and and non-CoreNet (P1017, P1023) based SoCs in what features exist and
the memory maps.
* Rename various immap defines to remove _CORENET_ if they are shared
* Added P1023/P1017 specific memory offsets
* Only setup LIODNs or LIODN related code on CORENET based SoCs
(features doesn't exist on P1023/P1017)
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index ce27fec..d26d648 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -2204,8 +2204,8 @@
#define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x221000
#define CONFIG_SYS_FSL_SEC_OFFSET 0x300000
#define CONFIG_SYS_FSL_CORENET_PME_OFFSET 0x316000
-#define CONFIG_SYS_FSL_CORENET_QMAN_OFFSET 0x318000
-#define CONFIG_SYS_FSL_CORENET_BMAN_OFFSET 0x31a000
+#define CONFIG_SYS_FSL_QMAN_OFFSET 0x318000
+#define CONFIG_SYS_FSL_BMAN_OFFSET 0x31a000
#define CONFIG_SYS_FSL_FM1_OFFSET 0x400000
#define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x488000
#define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x489000
@@ -2268,10 +2268,10 @@
#define CONFIG_SYS_FSL_CPC_ADDR \
(CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET)
-#define CONFIG_SYS_FSL_CORENET_QMAN_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_QMAN_OFFSET)
-#define CONFIG_SYS_FSL_CORENET_BMAN_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_BMAN_OFFSET)
+#define CONFIG_SYS_FSL_QMAN_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_QMAN_OFFSET)
+#define CONFIG_SYS_FSL_BMAN_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_BMAN_OFFSET)
#define CONFIG_SYS_FSL_CORENET_PME_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_PME_OFFSET)
#define CONFIG_SYS_MPC85xx_GUTS_ADDR \