blob: b5509eee8cfedca86659fd66dd5d2ac062ffa6e8 [file] [log] [blame]
Simon Glass4cc43bf2021-08-18 21:40:25 -06001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Devicetree file for running sandbox tests
4 *
5 * This includes lots of extra devices used by various tests.
6 *
7 * Note that SPL use the main sandbox.dts file
8 */
9
Simon Glassb2c1cac2014-02-26 15:59:21 -070010/dts-v1/;
11
Patrick Delaunay23aee612020-01-13 11:35:13 +010012#include <dt-bindings/gpio/gpio.h>
13#include <dt-bindings/gpio/sandbox-gpio.h>
Marek Szyprowskiad398592021-02-18 11:33:18 +010014#include <dt-bindings/input/input.h>
Sean Anderson3438e3b2020-09-14 11:01:57 -040015#include <dt-bindings/pinctrl/sandbox-pinmux.h>
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +053016#include <dt-bindings/mux/mux.h>
Patrick Delaunay23aee612020-01-13 11:35:13 +010017
Simon Glassb2c1cac2014-02-26 15:59:21 -070018/ {
19 model = "sandbox";
20 compatible = "sandbox";
21 #address-cells = <1>;
Simon Glasscf61f742015-07-06 12:54:36 -060022 #size-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -070023
Simon Glassfef72b72014-07-23 06:55:03 -060024 aliases {
25 console = &uart0;
Michael Walle7efcdfd2021-02-25 16:51:11 +010026 ethernet0 = "/eth@10002000";
27 ethernet2 = &swp_0;
28 ethernet3 = &eth_3;
29 ethernet4 = &dsa_eth0;
30 ethernet5 = &eth_5;
Sean Anderson67d93a42022-05-05 13:11:30 -040031 ethernet6 = "/eth@10004000";
32 ethernet7 = &swp_1;
33 ethernet8 = &phy_eth0;
Simon Glass5620cf82018-10-01 12:22:40 -060034 gpio1 = &gpio_a;
35 gpio2 = &gpio_b;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +010036 gpio3 = &gpio_c;
Simon Glass0ccb0972015-01-25 08:27:05 -070037 i2c0 = "/i2c@0";
Simon Glasse4fef742017-04-23 20:02:07 -060038 mmc0 = "/mmc0";
39 mmc1 = "/mmc1";
Simon Glassf1eba352022-10-20 18:23:20 -060040 mmc2 = "/mmc2";
41 mmc3 = "/mmc3";
Bin Meng408e5902018-08-03 01:14:41 -070042 pci0 = &pci0;
43 pci1 = &pci1;
Bin Meng510dddb2018-08-03 01:14:50 -070044 pci2 = &pci2;
Michael Walle7c41a222020-06-02 01:47:09 +020045 remoteproc0 = &rproc_1;
46 remoteproc1 = &rproc_2;
Simon Glass336b2952015-05-22 15:42:17 -060047 rtc0 = &rtc_0;
48 rtc1 = &rtc_1;
Simon Glass5b968632015-05-22 15:42:15 -060049 spi0 = "/spi@0";
Przemyslaw Marczak3dbb55e2015-05-13 13:38:34 +020050 testfdt6 = "/e-test";
Simon Glass0ccb0972015-01-25 08:27:05 -070051 testbus3 = "/some-bus";
52 testfdt0 = "/some-bus/c-test@0";
Simon Glass7d5e4112020-12-16 21:20:26 -070053 testfdt12 = "/some-bus/c-test@1";
Simon Glass0ccb0972015-01-25 08:27:05 -070054 testfdt3 = "/b-test";
55 testfdt5 = "/some-bus/c-test@5";
56 testfdt8 = "/a-test";
Simon Glass791a17f2020-12-16 21:20:27 -070057 testfdtm1 = &testfdtm1;
Eugeniu Rosca5ba71e52018-05-19 14:13:55 +020058 fdt-dummy0 = "/translation-test@8000/dev@0,0";
59 fdt-dummy1 = "/translation-test@8000/dev@1,100";
60 fdt-dummy2 = "/translation-test@8000/dev@2,200";
61 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glass31680482015-03-25 12:23:05 -060062 usb0 = &usb_0;
63 usb1 = &usb_1;
64 usb2 = &usb_2;
Mario Six95922152018-08-09 14:51:19 +020065 axi0 = &axi;
Mario Six02ad6fb2018-09-27 09:19:31 +020066 osd0 = "/osd";
Simon Glassfef72b72014-07-23 06:55:03 -060067 };
68
Simon Glass5e135d32022-10-20 18:23:15 -060069 binman: binman {
Philippe Reynes462d1632022-03-28 22:56:53 +020070 };
71
Rasmus Villemoes30d4d2b2021-04-21 11:06:55 +020072 config {
Simon Glass0034d962021-08-07 07:24:01 -060073 testing-bool;
74 testing-int = <123>;
75 testing-str = "testing";
Rasmus Villemoes30d4d2b2021-04-21 11:06:55 +020076 environment {
77 from_fdt = "yes";
78 fdt_env_path = "";
79 };
80 };
81
Simon Glassb255efc2022-04-24 23:31:24 -060082 bootstd {
Simon Glassd3a98cb2023-02-13 08:56:33 -070083 bootph-verify;
Simon Glassb255efc2022-04-24 23:31:24 -060084 compatible = "u-boot,boot-std";
85
86 filename-prefixes = "/", "/boot/";
87 bootdev-order = "mmc2", "mmc1";
88
Simon Glassb71d7f72023-05-10 16:34:46 -060089 extlinux {
90 compatible = "u-boot,extlinux";
Simon Glassb255efc2022-04-24 23:31:24 -060091 };
92
93 efi {
94 compatible = "u-boot,distro-efi";
95 };
Simon Glassa9289612022-10-20 18:23:14 -060096
Simon Glassd2bc33ed2023-01-06 08:52:41 -060097 theme {
98 font-size = <30>;
Simon Glass86f1ac52023-06-01 10:23:00 -060099 menu-inset = <3>;
100 menuitem-gap-y = <1>;
Simon Glassd2bc33ed2023-01-06 08:52:41 -0600101 };
102
Simon Glassf1eba352022-10-20 18:23:20 -0600103 /*
104 * This is used for the VBE OS-request tests. A FAT filesystem
105 * created in a partition with the VBE information appearing
106 * before the parititon starts
107 */
Simon Glassa9289612022-10-20 18:23:14 -0600108 firmware0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700109 bootph-verify;
Simon Glassa9289612022-10-20 18:23:14 -0600110 compatible = "fwupd,vbe-simple";
111 storage = "mmc1";
112 skip-offset = <0x200>;
113 area-start = <0x400>;
114 area-size = <0x1000>;
115 state-offset = <0x400>;
116 state-size = <0x40>;
117 version-offset = <0x800>;
118 version-size = <0x100>;
119 };
Simon Glassf1eba352022-10-20 18:23:20 -0600120
121 /*
122 * This is used for the VBE VPL tests. The MMC device holds the
123 * binman image.bin file. The test progresses through each phase
124 * of U-Boot, loading each in turn from MMC.
125 *
126 * Note that the test enables this node (and mmc3) before
127 * running U-Boot
128 */
129 firmware1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700130 bootph-verify;
Simon Glassf1eba352022-10-20 18:23:20 -0600131 status = "disabled";
132 compatible = "fwupd,vbe-simple";
133 storage = "mmc3";
Simon Glass9bb73e32023-04-02 14:01:24 +1200134 skip-offset = <0x800000>;
Simon Glassf1eba352022-10-20 18:23:20 -0600135 area-start = <0>;
136 area-size = <0xe00000>;
137 state-offset = <0xdffc00>;
138 state-size = <0x40>;
139 version-offset = <0xdffe00>;
140 version-size = <0x100>;
141 };
Simon Glassb255efc2022-04-24 23:31:24 -0600142 };
143
Simon Glass61300722023-06-01 10:23:01 -0600144 cedit: cedit {
145 };
146
Simon Glassb8c26552023-06-01 10:23:03 -0600147 cedit-theme {
148 font-size = <30>;
149 menu-inset = <3>;
150 menuitem-gap-y = <1>;
151 };
152
Andrew Scull451b8b12022-05-30 10:00:12 +0000153 fuzzing-engine {
154 compatible = "sandbox,fuzzing-engine";
155 };
156
Nandor Han6521e5d2021-06-10 16:56:44 +0300157 reboot-mode0 {
158 compatible = "reboot-mode-gpio";
159 gpios = <&gpio_c 0 GPIO_ACTIVE_HIGH>, <&gpio_c 1 GPIO_ACTIVE_HIGH>;
160 u-boot,env-variable = "bootstatus";
161 mode-test = <0x01>;
162 mode-download = <0x03>;
163 };
164
Nandor Han7e4067a2021-06-10 16:56:45 +0300165 reboot_mode1: reboot-mode@14 {
166 compatible = "reboot-mode-rtc";
167 rtc = <&rtc_0>;
168 reg = <0x30 4>;
169 u-boot,env-variable = "bootstatus";
170 big-endian;
171 mode-test = <0x21969147>;
172 mode-download = <0x51939147>;
173 };
174
Simon Glassed96cde2018-12-10 10:37:33 -0700175 audio: audio-codec {
176 compatible = "sandbox,audio-codec";
177 #sound-dai-cells = <1>;
178 };
179
Philippe Reynes1ee26482020-07-24 18:19:51 +0200180 buttons {
181 compatible = "gpio-keys";
182
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200183 btn1 {
Philippe Reynes1ee26482020-07-24 18:19:51 +0200184 gpios = <&gpio_a 3 0>;
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200185 label = "button1";
Dzmitry Sankouski157f2c52023-01-22 18:21:24 +0300186 linux,code = <BTN_1>;
Philippe Reynes1ee26482020-07-24 18:19:51 +0200187 };
188
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200189 btn2 {
Philippe Reynes1ee26482020-07-24 18:19:51 +0200190 gpios = <&gpio_a 4 0>;
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200191 label = "button2";
Dzmitry Sankouski157f2c52023-01-22 18:21:24 +0300192 linux,code = <BTN_2>;
Philippe Reynes1ee26482020-07-24 18:19:51 +0200193 };
194 };
195
Marek Szyprowskiad398592021-02-18 11:33:18 +0100196 buttons2 {
197 compatible = "adc-keys";
198 io-channels = <&adc 3>;
199 keyup-threshold-microvolt = <3000000>;
200
201 button-up {
202 label = "button3";
203 linux,code = <KEY_F3>;
204 press-threshold-microvolt = <1500000>;
205 };
206
207 button-down {
208 label = "button4";
209 linux,code = <KEY_F4>;
210 press-threshold-microvolt = <1000000>;
211 };
212
213 button-enter {
214 label = "button5";
215 linux,code = <KEY_F5>;
216 press-threshold-microvolt = <500000>;
217 };
218 };
219
Simon Glassc953aaf2018-12-10 10:37:34 -0700220 cros_ec: cros-ec {
Simon Glass699c9ca2018-10-01 12:22:08 -0600221 reg = <0 0>;
222 compatible = "google,cros-ec-sandbox";
223
224 /*
225 * This describes the flash memory within the EC. Note
226 * that the STM32L flash erases to 0, not 0xff.
227 */
228 flash {
229 image-pos = <0x08000000>;
230 size = <0x20000>;
231 erase-value = <0>;
232
233 /* Information for sandbox */
234 ro {
235 image-pos = <0>;
236 size = <0xf000>;
237 };
238 wp-ro {
239 image-pos = <0xf000>;
240 size = <0x1000>;
Simon Glassbf0a6922021-01-21 13:57:14 -0700241 used = <0x884>;
242 compress = "lz4";
243 uncomp-size = <0xcf8>;
244 hash {
245 algo = "sha256";
246 value = [00 01 02 03 04 05 06 07
247 08 09 0a 0b 0c 0d 0e 0f
248 10 11 12 13 14 15 16 17
249 18 19 1a 1b 1c 1d 1e 1f];
250 };
Simon Glass699c9ca2018-10-01 12:22:08 -0600251 };
252 rw {
253 image-pos = <0x10000>;
254 size = <0x10000>;
255 };
256 };
Alper Nebi Yasak8a8cd4f2021-05-19 19:33:31 +0300257
258 cros_ec_pwm: cros-ec-pwm {
259 compatible = "google,cros-ec-pwm";
260 #pwm-cells = <1>;
261 };
262
Simon Glass699c9ca2018-10-01 12:22:08 -0600263 };
264
Yannick Fertré9712c822019-10-07 15:29:05 +0200265 dsi_host: dsi_host {
266 compatible = "sandbox,dsi-host";
267 };
268
Simon Glassb2c1cac2014-02-26 15:59:21 -0700269 a-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600270 reg = <0 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700271 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600272 ping-expect = <0>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700273 ping-add = <0>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700274 bootph-all;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100275 test-gpios = <&gpio_a 1>, <&gpio_a 4>,
276 <&gpio_b 5 GPIO_ACTIVE_HIGH 3 2 1>,
Simon Glass16e10402015-01-05 20:05:29 -0700277 <0>, <&gpio_a 12>;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100278 test2-gpios = <&gpio_a 1>, <&gpio_a 4>,
279 <&gpio_b 6 GPIO_ACTIVE_LOW 3 2 1>,
280 <&gpio_b 7 GPIO_IN 3 2 1>,
281 <&gpio_b 8 GPIO_OUT 3 2 1>,
282 <&gpio_b 9 (GPIO_OUT|GPIO_OUT_ACTIVE) 3 2 1>;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100283 test3-gpios =
284 <&gpio_c 0 (GPIO_OUT|GPIO_OPEN_DRAIN)>,
285 <&gpio_c 1 (GPIO_OUT|GPIO_OPEN_SOURCE)>,
286 <&gpio_c 2 GPIO_OUT>,
287 <&gpio_c 3 (GPIO_IN|GPIO_PULL_UP)>,
288 <&gpio_c 4 (GPIO_IN|GPIO_PULL_DOWN)>,
Neil Armstrong643778b2020-05-05 10:43:18 +0200289 <&gpio_c 5 GPIO_IN>,
290 <&gpio_c 6 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_DRAIN)>,
291 <&gpio_c 7 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_SOURCE)>;
Jean-Jacques Hiblot73873402020-09-11 13:43:35 +0530292 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
293 test5-gpios = <&gpio_a 19>;
294
Simon Glass73025392021-10-23 17:26:04 -0600295 bool-value;
Stefan Herbrechtsmeier1b090e62022-06-14 15:21:30 +0200296 int8-value = /bits/ 8 <0x12>;
297 int16-value = /bits/ 16 <0x1234>;
Simon Glass6df01f92018-12-10 10:37:37 -0700298 int-value = <1234>;
299 uint-value = <(-1234)>;
Dario Binacchi421e81e2020-03-29 18:04:40 +0200300 int64-value = /bits/ 64 <0x1111222233334444>;
Dario Binacchi81d80b52020-03-29 18:04:41 +0200301 int-array = <5678 9123 4567>;
Simon Glassdd0ed902020-07-07 13:11:58 -0600302 str-value = "test string";
Simon Glass515dcff2020-02-06 09:55:00 -0700303 interrupts-extended = <&irq 3 0>;
Simon Glass09642392020-07-07 13:12:11 -0600304 acpi,name = "GHIJ";
Patrick Delaunay8cd28012020-09-25 09:41:16 +0200305 phandle-value = <&gpio_c 10>, <0xFFFFFFFF 20>, <&gpio_a 30>;
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530306
307 mux-controls = <&muxcontroller0 0>, <&muxcontroller0 1>,
308 <&muxcontroller0 2>, <&muxcontroller0 3>,
309 <&muxcontroller1>;
310 mux-control-names = "mux0", "mux1", "mux2", "mux3", "mux4";
311 mux-syscon = <&syscon3>;
Dario Binacchi836cc9d2020-12-30 00:16:26 +0100312 display-timings {
313 timing0: 240x320 {
314 clock-frequency = <6500000>;
315 hactive = <240>;
316 vactive = <320>;
317 hfront-porch = <6>;
318 hback-porch = <7>;
319 hsync-len = <1>;
320 vback-porch = <5>;
321 vfront-porch = <8>;
322 vsync-len = <2>;
323 hsync-active = <1>;
324 vsync-active = <0>;
325 de-active = <1>;
326 pixelclk-active = <1>;
327 interlaced;
328 doublescan;
329 doubleclk;
330 };
331 timing1: 480x800 {
332 clock-frequency = <9000000>;
333 hactive = <480>;
334 vactive = <800>;
335 hfront-porch = <10>;
336 hback-porch = <59>;
337 hsync-len = <12>;
338 vback-porch = <15>;
339 vfront-porch = <17>;
340 vsync-len = <16>;
341 hsync-active = <0>;
342 vsync-active = <1>;
343 de-active = <0>;
344 pixelclk-active = <0>;
345 };
346 timing2: 800x480 {
347 clock-frequency = <33500000>;
348 hactive = <800>;
349 vactive = <480>;
350 hback-porch = <89>;
351 hfront-porch = <164>;
352 vback-porch = <23>;
353 vfront-porch = <10>;
354 hsync-len = <11>;
355 vsync-len = <13>;
356 };
357 };
Raphael Gallais-Poua853b922023-05-11 16:36:52 +0200358 panel-timing {
Nikhil M Jainbb9d1312023-01-31 15:35:15 +0530359 clock-frequency = <6500000>;
360 hactive = <240>;
361 vactive = <320>;
362 hfront-porch = <6>;
363 hback-porch = <7>;
364 hsync-len = <1>;
365 vback-porch = <5>;
366 vfront-porch = <8>;
367 vsync-len = <2>;
368 hsync-active = <1>;
369 vsync-active = <0>;
370 de-active = <1>;
371 pixelclk-active = <1>;
372 interlaced;
373 doublescan;
374 doubleclk;
375 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700376 };
377
378 junk {
Simon Glasscf61f742015-07-06 12:54:36 -0600379 reg = <1 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700380 compatible = "not,compatible";
381 };
382
383 no-compatible {
Simon Glasscf61f742015-07-06 12:54:36 -0600384 reg = <2 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700385 };
386
Simon Glass5620cf82018-10-01 12:22:40 -0600387 backlight: backlight {
388 compatible = "pwm-backlight";
389 enable-gpios = <&gpio_a 1>;
390 power-supply = <&ldo_1>;
391 pwms = <&pwm 0 1000>;
392 default-brightness-level = <5>;
393 brightness-levels = <0 16 32 64 128 170 202 234 255>;
394 };
395
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200396 bind-test {
Patrice Chotard7b7f9392020-07-28 09:13:33 +0200397 compatible = "simple-bus";
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200398 bind-test-child1 {
399 compatible = "sandbox,phy";
400 #phy-cells = <1>;
401 };
402
403 bind-test-child2 {
404 compatible = "simple-bus";
405 };
406 };
407
Simon Glassb2c1cac2014-02-26 15:59:21 -0700408 b-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600409 reg = <3 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700410 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600411 ping-expect = <3>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700412 ping-add = <3>;
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530413
414 mux-controls = <&muxcontroller0 0>;
415 mux-control-names = "mux0";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700416 };
417
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200418 phy_provider0: gen_phy@0 {
419 compatible = "sandbox,phy";
420 #phy-cells = <1>;
421 };
422
423 phy_provider1: gen_phy@1 {
424 compatible = "sandbox,phy";
425 #phy-cells = <0>;
426 broken;
427 };
428
developer71092972020-05-02 11:35:12 +0200429 phy_provider2: gen_phy@2 {
430 compatible = "sandbox,phy";
431 #phy-cells = <0>;
432 };
433
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200434 gen_phy_user: gen_phy_user {
435 compatible = "simple-bus";
436 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
437 phy-names = "phy1", "phy2", "phy3";
438 };
439
developer71092972020-05-02 11:35:12 +0200440 gen_phy_user1: gen_phy_user1 {
441 compatible = "simple-bus";
442 phys = <&phy_provider0 0>, <&phy_provider2>;
443 phy-names = "phy1", "phy2";
444 };
445
Simon Glassb2c1cac2014-02-26 15:59:21 -0700446 some-bus {
447 #address-cells = <1>;
448 #size-cells = <0>;
Simon Glass40717422014-07-23 06:55:18 -0600449 compatible = "denx,u-boot-test-bus";
Simon Glasscf61f742015-07-06 12:54:36 -0600450 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600451 ping-expect = <4>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700452 ping-add = <4>;
Simon Glass40717422014-07-23 06:55:18 -0600453 c-test@5 {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700454 compatible = "denx,u-boot-fdt-test";
455 reg = <5>;
Simon Glass40717422014-07-23 06:55:18 -0600456 ping-expect = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700457 ping-add = <5>;
458 };
Simon Glass40717422014-07-23 06:55:18 -0600459 c-test@0 {
460 compatible = "denx,u-boot-fdt-test";
461 reg = <0>;
462 ping-expect = <6>;
463 ping-add = <6>;
464 };
465 c-test@1 {
466 compatible = "denx,u-boot-fdt-test";
467 reg = <1>;
468 ping-expect = <7>;
469 ping-add = <7>;
470 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700471 };
472
473 d-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600474 reg = <3 1>;
Simon Glassdb6f0202014-07-23 06:55:12 -0600475 ping-expect = <6>;
476 ping-add = <6>;
477 compatible = "google,another-fdt-test";
478 };
479
480 e-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600481 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600482 ping-expect = <6>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700483 ping-add = <6>;
484 compatible = "google,another-fdt-test";
485 };
486
Simon Glass0ccb0972015-01-25 08:27:05 -0700487 f-test {
488 compatible = "denx,u-boot-fdt-test";
489 };
490
491 g-test {
492 compatible = "denx,u-boot-fdt-test";
493 };
494
Bin Mengd9d24782018-10-10 22:07:01 -0700495 h-test {
496 compatible = "denx,u-boot-fdt-test1";
497 };
498
developercf8bc132020-05-02 11:35:10 +0200499 i-test {
500 compatible = "mediatek,u-boot-fdt-test";
501 #address-cells = <1>;
502 #size-cells = <0>;
503
504 subnode@0 {
505 reg = <0>;
506 };
507
508 subnode@1 {
509 reg = <1>;
510 };
511
512 subnode@2 {
513 reg = <2>;
514 };
515 };
516
Simon Glass204675c2019-12-29 21:19:25 -0700517 devres-test {
518 compatible = "denx,u-boot-devres-test";
519 };
520
Jean-Jacques Hiblot73873402020-09-11 13:43:35 +0530521 another-test {
522 reg = <0 2>;
523 compatible = "denx,u-boot-fdt-test";
524 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
525 test5-gpios = <&gpio_a 19>;
526 };
527
Nicolas Saenz Julienne22b7f7e2021-01-12 13:55:23 +0100528 mmio-bus@0 {
529 #address-cells = <1>;
530 #size-cells = <1>;
531 compatible = "denx,u-boot-test-bus";
532 dma-ranges = <0x10000000 0x00000000 0x00040000>;
533
534 subnode@0 {
535 compatible = "denx,u-boot-fdt-test";
536 };
537 };
538
539 mmio-bus@1 {
540 #address-cells = <1>;
541 #size-cells = <1>;
542 compatible = "denx,u-boot-test-bus";
Nicolas Saenz Julienne892e9b42021-01-12 13:55:25 +0100543
544 subnode@0 {
545 compatible = "denx,u-boot-fdt-test";
546 };
Nicolas Saenz Julienne22b7f7e2021-01-12 13:55:23 +0100547 };
548
Simon Glass3c601b12020-07-07 13:12:06 -0600549 acpi_test1: acpi-test {
Simon Glass2d67fdf2020-04-08 16:57:34 -0600550 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600551 acpi-ssdt-test-data = "ab";
Simon Glass990cd5b2020-07-07 13:12:08 -0600552 acpi-dsdt-test-data = "hi";
Simon Glassebb2e832020-07-07 13:11:39 -0600553 child {
554 compatible = "denx,u-boot-acpi-test";
555 };
Simon Glass2d67fdf2020-04-08 16:57:34 -0600556 };
557
Simon Glass3c601b12020-07-07 13:12:06 -0600558 acpi_test2: acpi-test2 {
Simon Glass17968c32020-04-26 09:19:46 -0600559 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600560 acpi-ssdt-test-data = "cd";
Simon Glass990cd5b2020-07-07 13:12:08 -0600561 acpi-dsdt-test-data = "jk";
Simon Glass17968c32020-04-26 09:19:46 -0600562 };
563
Patrice Chotard9cc2d142017-09-04 14:55:57 +0200564 clocks {
565 clk_fixed: clk-fixed {
566 compatible = "fixed-clock";
567 #clock-cells = <0>;
568 clock-frequency = <1234>;
569 };
Anup Patel8d28c3c2019-02-25 08:14:55 +0000570
571 clk_fixed_factor: clk-fixed-factor {
572 compatible = "fixed-factor-clock";
573 #clock-cells = <0>;
574 clock-div = <3>;
575 clock-mult = <2>;
576 clocks = <&clk_fixed>;
577 };
Lukasz Majewskiccafcdd2019-06-24 15:50:47 +0200578
579 osc {
580 compatible = "fixed-clock";
581 #clock-cells = <0>;
582 clock-frequency = <20000000>;
583 };
Stephen Warrena9622432016-06-17 09:44:00 -0600584 };
585
586 clk_sandbox: clk-sbox {
Simon Glass8cc4d822015-07-06 12:54:24 -0600587 compatible = "sandbox,clk";
Stephen Warrena9622432016-06-17 09:44:00 -0600588 #clock-cells = <1>;
Jean-Jacques Hiblotc1e9c942019-10-22 14:00:07 +0200589 assigned-clocks = <&clk_sandbox 3>;
590 assigned-clock-rates = <321>;
Stephen Warrena9622432016-06-17 09:44:00 -0600591 };
592
593 clk-test {
594 compatible = "sandbox,clk-test";
595 clocks = <&clk_fixed>,
596 <&clk_sandbox 1>,
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200597 <&clk_sandbox 0>,
598 <&clk_sandbox 3>,
599 <&clk_sandbox 2>;
600 clock-names = "fixed", "i2c", "spi", "uart2", "uart1";
Simon Glass8cc4d822015-07-06 12:54:24 -0600601 };
602
Lukasz Majewski8c0709b2019-06-24 15:50:50 +0200603 ccf: clk-ccf {
604 compatible = "sandbox,clk-ccf";
605 };
606
Simon Glass507ab962021-12-04 08:56:31 -0700607 efi-media {
608 compatible = "sandbox,efi-media";
609 };
610
Simon Glass5b968632015-05-22 15:42:15 -0600611 eth@10002000 {
612 compatible = "sandbox,eth";
613 reg = <0x10002000 0x1000>;
Simon Glass5b968632015-05-22 15:42:15 -0600614 };
615
616 eth_5: eth@10003000 {
617 compatible = "sandbox,eth";
618 reg = <0x10003000 0x1000>;
Sean Anderson13652b82022-05-05 13:11:44 -0400619 nvmem-cells = <&eth5_addr>;
620 nvmem-cell-names = "mac-address";
Simon Glass5b968632015-05-22 15:42:15 -0600621 };
622
Bin Meng04a11cb2015-08-27 22:25:53 -0700623 eth_3: sbe5 {
624 compatible = "sandbox,eth";
625 reg = <0x10005000 0x1000>;
Sean Andersone2dc0e62022-05-05 13:11:42 -0400626 nvmem-cells = <&eth3_addr>;
627 nvmem-cell-names = "mac-address";
Bin Meng04a11cb2015-08-27 22:25:53 -0700628 };
629
Simon Glass5b968632015-05-22 15:42:15 -0600630 eth@10004000 {
631 compatible = "sandbox,eth";
632 reg = <0x10004000 0x1000>;
Simon Glass5b968632015-05-22 15:42:15 -0600633 };
634
Marek BehĂșnf4f1ddc2022-04-07 00:32:57 +0200635 phy_eth0: phy-test-eth {
636 compatible = "sandbox,eth";
637 reg = <0x10007000 0x1000>;
Sean Anderson24b1b8d2022-05-05 13:11:35 -0400638 mac-address = [ 02 00 11 22 33 49 ];
Marek BehĂșnf4f1ddc2022-04-07 00:32:57 +0200639 phy-handle = <&ethphy1>;
Marek BehĂșnbc194772022-04-07 00:33:01 +0200640 phy-mode = "2500base-x";
Marek BehĂșnf4f1ddc2022-04-07 00:32:57 +0200641 };
642
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800643 dsa_eth0: dsa-test-eth {
644 compatible = "sandbox,eth";
645 reg = <0x10006000 0x1000>;
Sean Anderson5768e8b2022-05-05 13:11:43 -0400646 nvmem-cells = <&eth4_addr>;
647 nvmem-cell-names = "mac-address";
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800648 };
649
650 dsa-test {
651 compatible = "sandbox,dsa";
652
653 ports {
654 #address-cells = <1>;
655 #size-cells = <0>;
656 swp_0: port@0 {
657 reg = <0>;
658 label = "lan0";
659 phy-mode = "rgmii-rxid";
660
661 fixed-link {
662 speed = <100>;
663 full-duplex;
664 };
665 };
666
667 swp_1: port@1 {
668 reg = <1>;
669 label = "lan1";
670 phy-mode = "rgmii-txid";
Bin Meng381ed972021-03-14 20:14:58 +0800671 fixed-link = <0 1 100 0 0>;
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800672 };
673
674 port@2 {
675 reg = <2>;
676 ethernet = <&dsa_eth0>;
677
678 fixed-link {
679 speed = <1000>;
680 full-duplex;
681 };
682 };
683 };
684 };
685
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700686 firmware {
687 sandbox_firmware: sandbox-firmware {
688 compatible = "sandbox,firmware";
689 };
Etienne Carriere02fd1262020-09-09 18:44:00 +0200690
Etienne Carriere09665cb2022-02-21 09:22:39 +0100691 scmi {
Etienne Carriere02fd1262020-09-09 18:44:00 +0200692 compatible = "sandbox,scmi-agent";
693 #address-cells = <1>;
694 #size-cells = <0>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200695
Etienne Carriere09665cb2022-02-21 09:22:39 +0100696 protocol@10 {
697 reg = <0x10>;
698 };
699
700 clk_scmi: protocol@14 {
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200701 reg = <0x14>;
702 #clock-cells = <1>;
703 };
Etienne Carriere8b9b6892020-09-09 18:44:07 +0200704
Etienne Carriere09665cb2022-02-21 09:22:39 +0100705 reset_scmi: protocol@16 {
Etienne Carriere8b9b6892020-09-09 18:44:07 +0200706 reg = <0x16>;
707 #reset-cells = <1>;
708 };
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100709
710 protocol@17 {
711 reg = <0x17>;
712
713 regulators {
714 #address-cells = <1>;
715 #size-cells = <0>;
716
Etienne Carriere09665cb2022-02-21 09:22:39 +0100717 regul0_scmi: reg@0 {
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100718 reg = <0>;
719 regulator-name = "sandbox-voltd0";
720 regulator-min-microvolt = <1100000>;
721 regulator-max-microvolt = <3300000>;
722 };
Etienne Carriere09665cb2022-02-21 09:22:39 +0100723 regul1_scmi: reg@1 {
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100724 reg = <0x1>;
725 regulator-name = "sandbox-voltd1";
726 regulator-min-microvolt = <1800000>;
727 };
728 };
729 };
Etienne Carriere02fd1262020-09-09 18:44:00 +0200730 };
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700731 };
732
Alexander Dahl6ac319d2022-09-30 14:04:30 +0200733 fpga {
734 compatible = "sandbox,fpga";
735 };
736
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100737 pinctrl-gpio {
738 compatible = "sandbox,pinctrl-gpio";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700739
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100740 gpio_a: base-gpios {
741 compatible = "sandbox,gpio";
742 gpio-controller;
743 #gpio-cells = <1>;
744 gpio-bank-name = "a";
745 sandbox,gpio-count = <20>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200746 hog_input_active_low {
747 gpio-hog;
748 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200749 gpios = <10 GPIO_ACTIVE_LOW>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200750 };
751 hog_input_active_high {
752 gpio-hog;
753 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200754 gpios = <11 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200755 };
756 hog_output_low {
757 gpio-hog;
758 output-low;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200759 gpios = <12 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200760 };
761 hog_output_high {
762 gpio-hog;
763 output-high;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200764 gpios = <13 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200765 };
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100766 };
767
768 gpio_b: extra-gpios {
769 compatible = "sandbox,gpio";
770 gpio-controller;
771 #gpio-cells = <5>;
772 gpio-bank-name = "b";
773 sandbox,gpio-count = <10>;
774 };
Simon Glass25348a42014-10-13 23:42:11 -0600775
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100776 gpio_c: pinmux-gpios {
777 compatible = "sandbox,gpio";
778 gpio-controller;
779 #gpio-cells = <2>;
780 gpio-bank-name = "c";
781 sandbox,gpio-count = <10>;
782 };
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100783 };
784
Simon Glass7df766e2014-12-10 08:55:55 -0700785 i2c@0 {
786 #address-cells = <1>;
787 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600788 reg = <0 1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700789 compatible = "sandbox,i2c";
790 clock-frequency = <100000>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +0200791 pinctrl-names = "default";
792 pinctrl-0 = <&pinmux_i2c0_pins>;
793
Simon Glass7df766e2014-12-10 08:55:55 -0700794 eeprom@2c {
Sean Andersone2dc0e62022-05-05 13:11:42 -0400795 #address-cells = <1>;
796 #size-cells = <1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700797 reg = <0x2c>;
798 compatible = "i2c-eeprom";
Simon Glass17b56f62018-11-18 08:14:34 -0700799 sandbox,emul = <&emul_eeprom>;
Michal Simek4f18f922020-05-28 11:48:55 +0200800 partitions {
801 compatible = "fixed-partitions";
802 #address-cells = <1>;
803 #size-cells = <1>;
804 bootcount_i2c: bootcount@10 {
805 reg = <10 2>;
806 };
807 };
Sean Andersone2dc0e62022-05-05 13:11:42 -0400808
809 eth3_addr: mac-address@24 {
810 reg = <24 6>;
811 };
Simon Glass7df766e2014-12-10 08:55:55 -0700812 };
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200813
Simon Glass336b2952015-05-22 15:42:17 -0600814 rtc_0: rtc@43 {
Sean Anderson5768e8b2022-05-05 13:11:43 -0400815 #address-cells = <1>;
816 #size-cells = <1>;
Simon Glass336b2952015-05-22 15:42:17 -0600817 reg = <0x43>;
818 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700819 sandbox,emul = <&emul0>;
Sean Anderson5768e8b2022-05-05 13:11:43 -0400820
821 eth4_addr: mac-address@40 {
822 reg = <0x40 6>;
823 };
Simon Glass336b2952015-05-22 15:42:17 -0600824 };
825
826 rtc_1: rtc@61 {
827 reg = <0x61>;
828 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700829 sandbox,emul = <&emul1>;
830 };
831
832 i2c_emul: emul {
833 reg = <0xff>;
834 compatible = "sandbox,i2c-emul-parent";
835 emul_eeprom: emul-eeprom {
836 compatible = "sandbox,i2c-eeprom";
837 sandbox,filename = "i2c.bin";
838 sandbox,size = <256>;
839 };
840 emul0: emul0 {
Simon Glass98af3742021-02-03 06:01:17 -0700841 compatible = "sandbox,i2c-rtc-emul";
Simon Glass17b56f62018-11-18 08:14:34 -0700842 };
843 emul1: emull {
Simon Glass98af3742021-02-03 06:01:17 -0700844 compatible = "sandbox,i2c-rtc-emul";
Simon Glass336b2952015-05-22 15:42:17 -0600845 };
846 };
847
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200848 sandbox_pmic: sandbox_pmic {
849 reg = <0x40>;
Simon Glass17b56f62018-11-18 08:14:34 -0700850 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200851 };
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200852
853 mc34708: pmic@41 {
854 reg = <0x41>;
Simon Glass17b56f62018-11-18 08:14:34 -0700855 sandbox,emul = <&emul_pmic1>;
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200856 };
Simon Glass7df766e2014-12-10 08:55:55 -0700857 };
858
Philipp Tomsich1fc53302018-12-14 21:14:29 +0100859 bootcount@0 {
860 compatible = "u-boot,bootcount-rtc";
861 rtc = <&rtc_1>;
862 offset = <0x13>;
863 };
864
Michal Simek4f18f922020-05-28 11:48:55 +0200865 bootcount {
866 compatible = "u-boot,bootcount-i2c-eeprom";
867 i2c-eeprom = <&bootcount_i2c>;
868 };
869
Nandor Han88895812021-06-10 15:40:38 +0300870 bootcount_4@0 {
871 compatible = "u-boot,bootcount-syscon";
872 syscon = <&syscon0>;
873 reg = <0x0 0x04>, <0x0 0x04>;
874 reg-names = "syscon_reg", "offset";
875 };
876
877 bootcount_2@0 {
878 compatible = "u-boot,bootcount-syscon";
879 syscon = <&syscon0>;
880 reg = <0x0 0x04>, <0x0 0x02> ;
881 reg-names = "syscon_reg", "offset";
882 };
883
Marek Szyprowskiad398592021-02-18 11:33:18 +0100884 adc: adc@0 {
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100885 compatible = "sandbox,adc";
Marek Szyprowskiad398592021-02-18 11:33:18 +0100886 #io-channel-cells = <1>;
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100887 vdd-supply = <&buck2>;
888 vss-microvolts = <0>;
889 };
890
Mark Kettenis67748ee2021-10-23 16:58:02 +0200891 iommu: iommu@0 {
892 compatible = "sandbox,iommu";
893 #iommu-cells = <0>;
894 };
895
Simon Glass515dcff2020-02-06 09:55:00 -0700896 irq: irq {
Simon Glass54028bc2019-12-06 21:41:59 -0700897 compatible = "sandbox,irq";
Simon Glass515dcff2020-02-06 09:55:00 -0700898 interrupt-controller;
899 #interrupt-cells = <2>;
Simon Glass54028bc2019-12-06 21:41:59 -0700900 };
901
Simon Glass90b6fef2016-01-18 19:52:26 -0700902 lcd {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700903 bootph-all;
Simon Glass90b6fef2016-01-18 19:52:26 -0700904 compatible = "sandbox,lcd-sdl";
Dario Binacchi20dd9e12021-04-11 09:39:50 +0200905 pinctrl-names = "default";
906 pinctrl-0 = <&pinmux_lcd_pins>;
Simon Glass90b6fef2016-01-18 19:52:26 -0700907 xres = <1366>;
908 yres = <768>;
909 };
910
Simon Glassd783eb32015-07-06 12:54:34 -0600911 leds {
912 compatible = "gpio-leds";
913
914 iracibble {
915 gpios = <&gpio_a 1 0>;
916 label = "sandbox:red";
917 };
918
919 martinet {
920 gpios = <&gpio_a 2 0>;
921 label = "sandbox:green";
922 };
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200923
924 default_on {
925 gpios = <&gpio_a 5 0>;
926 label = "sandbox:default_on";
927 default-state = "on";
928 };
929
930 default_off {
931 gpios = <&gpio_a 6 0>;
Sean Andersonfbf8d652020-09-14 11:02:03 -0400932 /* label intentionally omitted */
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200933 default-state = "off";
934 };
Simon Glassd783eb32015-07-06 12:54:34 -0600935 };
936
Paul Doelle709f0372022-07-04 09:00:25 +0000937 wdt-gpio-toggle {
Rasmus Villemoes2b673872021-08-19 11:57:05 +0200938 gpios = <&gpio_a 7 0>;
939 compatible = "linux,wdt-gpio";
Rasmus Villemoesf91ff5a2021-08-19 11:57:06 +0200940 hw_margin_ms = <100>;
Paul Doelle709f0372022-07-04 09:00:25 +0000941 hw_algo = "toggle";
942 always-running;
943 };
944
945 wdt-gpio-level {
946 gpios = <&gpio_a 7 0>;
947 compatible = "linux,wdt-gpio";
948 hw_margin_ms = <100>;
949 hw_algo = "level";
Rasmus Villemoes2b673872021-08-19 11:57:05 +0200950 always-running;
951 };
952
Stephen Warren62f2c902016-05-16 17:41:37 -0600953 mbox: mbox {
954 compatible = "sandbox,mbox";
955 #mbox-cells = <1>;
956 };
957
958 mbox-test {
959 compatible = "sandbox,mbox-test";
960 mboxes = <&mbox 100>, <&mbox 1>;
961 mbox-names = "other", "test";
962 };
963
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900964 cpus {
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +0200965 #address-cells = <1>;
966 #size-cells = <0>;
Sean Anderson79d3bba2020-09-28 10:52:23 -0400967 timebase-frequency = <2000000>;
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +0200968 cpu1: cpu@1 {
969 device_type = "cpu";
970 reg = <0x1>;
Sean Anderson79d3bba2020-09-28 10:52:23 -0400971 timebase-frequency = <3000000>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900972 compatible = "sandbox,cpu_sandbox";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700973 bootph-all;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900974 };
Mario Sixdea5df72018-08-06 10:23:44 +0200975
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +0200976 cpu2: cpu@2 {
977 device_type = "cpu";
978 reg = <0x2>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900979 compatible = "sandbox,cpu_sandbox";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700980 bootph-all;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900981 };
Mario Sixdea5df72018-08-06 10:23:44 +0200982
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +0200983 cpu3: cpu@3 {
984 device_type = "cpu";
985 reg = <0x3>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900986 compatible = "sandbox,cpu_sandbox";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700987 bootph-all;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900988 };
Mario Sixdea5df72018-08-06 10:23:44 +0200989 };
990
Dave Gerlach75dbdfc2020-07-15 23:39:58 -0500991 chipid: chipid {
992 compatible = "sandbox,soc";
993 };
994
Simon Glassc953aaf2018-12-10 10:37:34 -0700995 i2s: i2s {
996 compatible = "sandbox,i2s";
997 #sound-dai-cells = <1>;
Simon Glass4d5814c2019-02-16 20:24:56 -0700998 sandbox,silent; /* Don't emit sounds while testing */
Simon Glassc953aaf2018-12-10 10:37:34 -0700999 };
1000
Jean-Jacques Hiblotdb97c7f2019-07-05 09:33:57 +02001001 nop-test_0 {
1002 compatible = "sandbox,nop_sandbox1";
1003 nop-test_1 {
1004 compatible = "sandbox,nop_sandbox2";
1005 bind = "True";
1006 };
1007 nop-test_2 {
1008 compatible = "sandbox,nop_sandbox2";
1009 bind = "False";
1010 };
1011 };
1012
Roger Quadrosb0679a72022-10-20 16:30:46 +03001013 memory-controller {
1014 compatible = "sandbox,memory";
1015 };
1016
Mario Sixa8ce0ee2018-07-31 14:24:14 +02001017 misc-test {
Sean Anderson13652b82022-05-05 13:11:44 -04001018 #address-cells = <1>;
1019 #size-cells = <1>;
Mario Sixa8ce0ee2018-07-31 14:24:14 +02001020 compatible = "sandbox,misc_sandbox";
Sean Anderson13652b82022-05-05 13:11:44 -04001021
1022 eth5_addr: mac-address@10 {
1023 reg = <0x10 6>;
1024 };
Mario Sixa8ce0ee2018-07-31 14:24:14 +02001025 };
1026
Simon Glasse4fef742017-04-23 20:02:07 -06001027 mmc2 {
1028 compatible = "sandbox,mmc";
Simon Glass965cd402021-07-05 16:32:58 -06001029 non-removable;
Simon Glasse4fef742017-04-23 20:02:07 -06001030 };
1031
Simon Glassb255efc2022-04-24 23:31:24 -06001032 /* This is used for the bootdev tests */
Simon Glasse4fef742017-04-23 20:02:07 -06001033 mmc1 {
1034 compatible = "sandbox,mmc";
Simon Glassb255efc2022-04-24 23:31:24 -06001035 filename = "mmc1.img";
Simon Glasse4fef742017-04-23 20:02:07 -06001036 };
1037
Simon Glassb255efc2022-04-24 23:31:24 -06001038 /* This is used for the fastboot tests */
Sughosh Ganu77079e72022-10-21 18:16:05 +05301039 mmc0: mmc0 {
Simon Glassd3e58e42015-07-06 12:54:32 -06001040 compatible = "sandbox,mmc";
1041 };
1042
Simon Glassf1eba352022-10-20 18:23:20 -06001043 /* This is used for VBE VPL tests */
1044 mmc3 {
1045 status = "disabled";
1046 compatible = "sandbox,mmc";
1047 filename = "image.bin";
1048 non-removable;
1049 };
1050
Simon Glassd2bc33ed2023-01-06 08:52:41 -06001051 /* This is used for bootstd bootmenu tests */
1052 mmc4 {
1053 status = "disabled";
1054 compatible = "sandbox,mmc";
1055 filename = "mmc4.img";
1056 };
1057
Simon Glass53a68b32019-02-16 20:24:50 -07001058 pch {
1059 compatible = "sandbox,pch";
1060 };
1061
Tom Rini4a3ca482020-02-11 12:41:23 -05001062 pci0: pci@0 {
Simon Glass3a6eae62015-03-05 12:25:34 -07001063 compatible = "sandbox,pci";
1064 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -05001065 bus-range = <0x00 0xff>;
Simon Glass3a6eae62015-03-05 12:25:34 -07001066 #address-cells = <3>;
1067 #size-cells = <2>;
Simon Glass35464f72019-09-25 08:56:08 -06001068 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glass3a6eae62015-03-05 12:25:34 -07001069 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Mark Kettenis5dfd4ec2023-01-21 20:27:57 +01001070 iommu-map = <0x0010 &iommu 0 1>;
1071 iommu-map-mask = <0xfffffff8>;
Bin Mengcbf071b2018-08-03 01:14:39 -07001072 pci@0,0 {
1073 compatible = "pci-generic";
1074 reg = <0x0000 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001075 sandbox,emul = <&swap_case_emul0_0>;
Bin Mengcbf071b2018-08-03 01:14:39 -07001076 };
Alex Margineanf1274432019-06-07 11:24:24 +03001077 pci@1,0 {
1078 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -06001079 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
1080 reg = <0x02000814 0 0 0 0
1081 0x01000810 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001082 sandbox,emul = <&swap_case_emul0_1>;
Alex Margineanf1274432019-06-07 11:24:24 +03001083 };
Simon Glass937bb472019-12-06 21:41:57 -07001084 p2sb-pci@2,0 {
1085 compatible = "sandbox,p2sb";
1086 reg = <0x02001010 0 0 0 0>;
1087 sandbox,emul = <&p2sb_emul>;
1088
1089 adder {
1090 intel,p2sb-port-id = <3>;
1091 compatible = "sandbox,adder";
1092 };
1093 };
Simon Glass8c501022019-12-06 21:41:54 -07001094 pci@1e,0 {
1095 compatible = "sandbox,pmc";
1096 reg = <0xf000 0 0 0 0>;
1097 sandbox,emul = <&pmc_emul1e>;
1098 acpi-base = <0x400>;
1099 gpe0-dwx-mask = <0xf>;
1100 gpe0-dwx-shift-base = <4>;
1101 gpe0-dw = <6 7 9>;
1102 gpe0-sts = <0x20>;
1103 gpe0-en = <0x30>;
1104 };
Simon Glass3a6eae62015-03-05 12:25:34 -07001105 pci@1f,0 {
1106 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -06001107 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
1108 reg = <0x0100f810 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001109 sandbox,emul = <&swap_case_emul0_1f>;
Simon Glass3a6eae62015-03-05 12:25:34 -07001110 };
1111 };
1112
Simon Glassb98ba4c2019-09-25 08:56:10 -06001113 pci-emul0 {
1114 compatible = "sandbox,pci-emul-parent";
1115 swap_case_emul0_0: emul0@0,0 {
1116 compatible = "sandbox,swap-case";
1117 };
1118 swap_case_emul0_1: emul0@1,0 {
1119 compatible = "sandbox,swap-case";
1120 use-ea;
1121 };
1122 swap_case_emul0_1f: emul0@1f,0 {
1123 compatible = "sandbox,swap-case";
1124 };
Simon Glass937bb472019-12-06 21:41:57 -07001125 p2sb_emul: emul@2,0 {
1126 compatible = "sandbox,p2sb-emul";
1127 };
Simon Glass8c501022019-12-06 21:41:54 -07001128 pmc_emul1e: emul@1e,0 {
1129 compatible = "sandbox,pmc-emul";
1130 };
Simon Glassb98ba4c2019-09-25 08:56:10 -06001131 };
1132
Tom Rini4a3ca482020-02-11 12:41:23 -05001133 pci1: pci@1 {
Bin Meng408e5902018-08-03 01:14:41 -07001134 compatible = "sandbox,pci";
1135 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -05001136 bus-range = <0x00 0xff>;
Bin Meng408e5902018-08-03 01:14:41 -07001137 #address-cells = <3>;
1138 #size-cells = <2>;
Suneel Garapati3ac3aec2019-10-19 17:10:20 -07001139 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000 // MEM0
Andrew Scullc7456a42022-04-21 16:11:09 +00001140 0x02000000 0 0x31000000 0x3e000000 0 0x2000 // MEM1
Suneel Garapati3ac3aec2019-10-19 17:10:20 -07001141 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng5fed5362018-08-03 01:14:47 -07001142 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasute5733222018-10-10 21:27:08 +02001143 0x0c 0x00 0x1234 0x5678
1144 0x10 0x00 0x1234 0x5678>;
1145 pci@10,0 {
1146 reg = <0x8000 0 0 0 0>;
1147 };
Bin Meng408e5902018-08-03 01:14:41 -07001148 };
1149
Tom Rini4a3ca482020-02-11 12:41:23 -05001150 pci2: pci@2 {
Bin Meng510dddb2018-08-03 01:14:50 -07001151 compatible = "sandbox,pci";
1152 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -05001153 bus-range = <0x00 0xff>;
Bin Meng510dddb2018-08-03 01:14:50 -07001154 #address-cells = <3>;
1155 #size-cells = <2>;
1156 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
1157 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
1158 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
1159 pci@1f,0 {
1160 compatible = "pci-generic";
1161 reg = <0xf800 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001162 sandbox,emul = <&swap_case_emul2_1f>;
1163 };
1164 };
1165
1166 pci-emul2 {
1167 compatible = "sandbox,pci-emul-parent";
1168 swap_case_emul2_1f: emul2@1f,0 {
1169 compatible = "sandbox,swap-case";
Bin Meng510dddb2018-08-03 01:14:50 -07001170 };
1171 };
1172
Ramon Friedc64f19b2019-04-27 11:15:23 +03001173 pci_ep: pci_ep {
1174 compatible = "sandbox,pci_ep";
1175 };
1176
Simon Glass9c433fe2017-04-23 20:10:44 -06001177 probing {
1178 compatible = "simple-bus";
1179 test1 {
1180 compatible = "denx,u-boot-probe-test";
1181 };
1182
1183 test2 {
1184 compatible = "denx,u-boot-probe-test";
1185 };
1186
1187 test3 {
1188 compatible = "denx,u-boot-probe-test";
1189 };
1190
1191 test4 {
1192 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001193 first-syscon = <&syscon0>;
1194 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunayee010432019-03-07 09:57:13 +01001195 third-syscon = <&syscon2>;
Simon Glass9c433fe2017-04-23 20:10:44 -06001196 };
1197 };
1198
Stephen Warren92c67fa2016-07-13 13:45:31 -06001199 pwrdom: power-domain {
1200 compatible = "sandbox,power-domain";
1201 #power-domain-cells = <1>;
1202 };
1203
1204 power-domain-test {
1205 compatible = "sandbox,power-domain-test";
1206 power-domains = <&pwrdom 2>;
1207 };
1208
Simon Glass5620cf82018-10-01 12:22:40 -06001209 pwm: pwm {
Simon Glasse62f4be2017-04-16 21:01:11 -06001210 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -06001211 #pwm-cells = <2>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001212 pinctrl-names = "default";
1213 pinctrl-0 = <&pinmux_pwm_pins>;
Simon Glasse62f4be2017-04-16 21:01:11 -06001214 };
1215
1216 pwm2 {
1217 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -06001218 #pwm-cells = <2>;
Simon Glasse62f4be2017-04-16 21:01:11 -06001219 };
1220
Simon Glass3d355e62015-07-06 12:54:31 -06001221 ram {
1222 compatible = "sandbox,ram";
1223 };
1224
Simon Glassd860f222015-07-06 12:54:29 -06001225 reset@0 {
1226 compatible = "sandbox,warm-reset";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001227 bootph-some-ram;
Simon Glassd860f222015-07-06 12:54:29 -06001228 };
1229
1230 reset@1 {
1231 compatible = "sandbox,reset";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001232 bootph-some-ram;
Simon Glassd860f222015-07-06 12:54:29 -06001233 };
1234
Stephen Warren6488e642016-06-17 09:43:59 -06001235 resetc: reset-ctl {
1236 compatible = "sandbox,reset-ctl";
1237 #reset-cells = <1>;
1238 };
1239
1240 reset-ctl-test {
1241 compatible = "sandbox,reset-ctl-test";
Neil Armstrong9b4cdef2021-04-20 10:42:25 +02001242 resets = <&resetc 100>, <&resetc 2>, <&resetc 20>, <&resetc 40>;
1243 reset-names = "other", "test", "test2", "test3";
Stephen Warren6488e642016-06-17 09:43:59 -06001244 };
1245
Sughosh Ganu23e37512019-12-28 23:58:31 +05301246 rng {
1247 compatible = "sandbox,sandbox-rng";
1248 };
1249
Nishanth Menonedf85812015-09-17 15:42:41 -05001250 rproc_1: rproc@1 {
1251 compatible = "sandbox,test-processor";
1252 remoteproc-name = "remoteproc-test-dev1";
1253 };
1254
1255 rproc_2: rproc@2 {
1256 compatible = "sandbox,test-processor";
1257 internal-memory-mapped;
1258 remoteproc-name = "remoteproc-test-dev2";
1259 };
1260
Simon Glass5620cf82018-10-01 12:22:40 -06001261 panel {
1262 compatible = "simple-panel";
1263 backlight = <&backlight 0 100>;
1264 };
1265
Simon Glass509f32e2022-09-21 16:21:47 +02001266 scsi {
1267 compatible = "sandbox,scsi";
1268 sandbox,filepath = "scsi.img";
1269 };
1270
Ramon Fried26ed32e2018-07-02 02:57:59 +03001271 smem@0 {
1272 compatible = "sandbox,smem";
1273 };
1274
Simon Glass76072ac2018-12-10 10:37:36 -07001275 sound {
1276 compatible = "sandbox,sound";
1277 cpu {
1278 sound-dai = <&i2s 0>;
1279 };
1280
1281 codec {
1282 sound-dai = <&audio 0>;
1283 };
1284 };
1285
Simon Glass25348a42014-10-13 23:42:11 -06001286 spi@0 {
1287 #address-cells = <1>;
1288 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -06001289 reg = <0 1>;
Simon Glass25348a42014-10-13 23:42:11 -06001290 compatible = "sandbox,spi";
Ovidiu Panaitae734732020-12-14 19:06:47 +02001291 cs-gpios = <0>, <0>, <&gpio_a 0>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001292 pinctrl-names = "default";
1293 pinctrl-0 = <&pinmux_spi0_pins>;
1294
Simon Glass25348a42014-10-13 23:42:11 -06001295 spi.bin@0 {
1296 reg = <0>;
Neil Armstronga009fa72019-02-10 10:16:20 +00001297 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass25348a42014-10-13 23:42:11 -06001298 spi-max-frequency = <40000000>;
1299 sandbox,filename = "spi.bin";
1300 };
Ovidiu Panaitae734732020-12-14 19:06:47 +02001301 spi.bin@1 {
1302 reg = <1>;
1303 compatible = "spansion,m25p16", "jedec,spi-nor";
1304 spi-max-frequency = <50000000>;
1305 sandbox,filename = "spi.bin";
1306 spi-cpol;
1307 spi-cpha;
1308 };
Simon Glass25348a42014-10-13 23:42:11 -06001309 };
1310
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001311 syscon0: syscon@0 {
Simon Glasscd556522015-07-06 12:54:35 -06001312 compatible = "sandbox,syscon0";
Mario Sixe3f59f42018-10-04 09:00:40 +02001313 reg = <0x10 16>;
Simon Glasscd556522015-07-06 12:54:35 -06001314 };
1315
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001316 another_system_controller: syscon@1 {
Simon Glasscd556522015-07-06 12:54:35 -06001317 compatible = "sandbox,syscon1";
Simon Glasscf61f742015-07-06 12:54:36 -06001318 reg = <0x20 5
1319 0x28 6
1320 0x30 7
1321 0x38 8>;
Simon Glasscd556522015-07-06 12:54:35 -06001322 };
1323
Patrick Delaunayee010432019-03-07 09:57:13 +01001324 syscon2: syscon@2 {
Masahiro Yamada42ab1072018-04-23 13:26:53 +09001325 compatible = "simple-mfd", "syscon";
1326 reg = <0x40 5
1327 0x48 6
1328 0x50 7
1329 0x58 8>;
1330 };
1331
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +05301332 syscon3: syscon@3 {
1333 compatible = "simple-mfd", "syscon";
1334 reg = <0x000100 0x10>;
1335
1336 muxcontroller0: a-mux-controller {
1337 compatible = "mmio-mux";
1338 #mux-control-cells = <1>;
1339
1340 mux-reg-masks = <0x0 0x30>, /* 0: reg 0x0, bits 5:4 */
1341 <0xc 0x1E>, /* 1: reg 0xc, bits 4:1 */
1342 <0x4 0xFF>; /* 2: reg 0x4, bits 7:0 */
1343 idle-states = <MUX_IDLE_AS_IS>, <0x02>, <0x73>;
1344 u-boot,mux-autoprobe;
1345 };
1346 };
1347
1348 muxcontroller1: emul-mux-controller {
1349 compatible = "mux-emul";
1350 #mux-control-cells = <0>;
1351 u-boot,mux-autoprobe;
1352 idle-state = <0xabcd>;
1353 };
1354
Simon Glass791a17f2020-12-16 21:20:27 -07001355 testfdtm0 {
1356 compatible = "denx,u-boot-fdtm-test";
1357 };
1358
1359 testfdtm1: testfdtm1 {
1360 compatible = "denx,u-boot-fdtm-test";
1361 };
1362
1363 testfdtm2 {
1364 compatible = "denx,u-boot-fdtm-test";
1365 };
1366
Sean Anderson79d3bba2020-09-28 10:52:23 -04001367 timer@0 {
Thomas Chou6f2cfbf2015-12-11 16:27:34 +08001368 compatible = "sandbox,timer";
1369 clock-frequency = <1000000>;
1370 };
1371
Sean Anderson79d3bba2020-09-28 10:52:23 -04001372 timer@1 {
1373 compatible = "sandbox,timer";
1374 sandbox,timebase-frequency-fallback;
1375 };
1376
Miquel Raynal80938c12018-05-15 11:57:27 +02001377 tpm2 {
1378 compatible = "sandbox,tpm2";
1379 };
1380
Simon Glasseef107e2023-02-21 06:24:51 -07001381 tpm {
1382 compatible = "google,sandbox-tpm";
1383 };
1384
Simon Glass5b968632015-05-22 15:42:15 -06001385 uart0: serial {
1386 compatible = "sandbox,serial";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001387 bootph-all;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001388 pinctrl-names = "default";
1389 pinctrl-0 = <&pinmux_uart0_pins>;
Joe Hershberger4c197242015-03-22 17:09:15 -05001390 };
1391
Simon Glass31680482015-03-25 12:23:05 -06001392 usb_0: usb@0 {
1393 compatible = "sandbox,usb";
1394 status = "disabled";
1395 hub {
1396 compatible = "sandbox,usb-hub";
1397 #address-cells = <1>;
1398 #size-cells = <0>;
1399 flash-stick {
1400 reg = <0>;
1401 compatible = "sandbox,usb-flash";
1402 };
1403 };
1404 };
1405
1406 usb_1: usb@1 {
1407 compatible = "sandbox,usb";
Mark Kettenis67748ee2021-10-23 16:58:02 +02001408 iommus = <&iommu>;
Simon Glass31680482015-03-25 12:23:05 -06001409 hub {
1410 compatible = "usb-hub";
1411 usb,device-class = <9>;
Michael Walle7c961322020-06-02 01:47:07 +02001412 #address-cells = <1>;
1413 #size-cells = <0>;
Simon Glass31680482015-03-25 12:23:05 -06001414 hub-emul {
1415 compatible = "sandbox,usb-hub";
1416 #address-cells = <1>;
1417 #size-cells = <0>;
Simon Glass4700fe52015-11-08 23:48:01 -07001418 flash-stick@0 {
Simon Glass31680482015-03-25 12:23:05 -06001419 reg = <0>;
1420 compatible = "sandbox,usb-flash";
1421 sandbox,filepath = "testflash.bin";
1422 };
1423
Simon Glass4700fe52015-11-08 23:48:01 -07001424 flash-stick@1 {
1425 reg = <1>;
1426 compatible = "sandbox,usb-flash";
1427 sandbox,filepath = "testflash1.bin";
1428 };
1429
1430 flash-stick@2 {
1431 reg = <2>;
1432 compatible = "sandbox,usb-flash";
1433 sandbox,filepath = "testflash2.bin";
1434 };
1435
Simon Glassc0ccc722015-11-08 23:48:08 -07001436 keyb@3 {
1437 reg = <3>;
1438 compatible = "sandbox,usb-keyb";
1439 };
1440
Simon Glass31680482015-03-25 12:23:05 -06001441 };
Michael Walle7c961322020-06-02 01:47:07 +02001442
1443 usbstor@1 {
1444 reg = <1>;
1445 };
1446 usbstor@3 {
1447 reg = <3>;
1448 };
Simon Glass31680482015-03-25 12:23:05 -06001449 };
1450 };
1451
1452 usb_2: usb@2 {
1453 compatible = "sandbox,usb";
1454 status = "disabled";
1455 };
1456
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001457 spmi: spmi@0 {
1458 compatible = "sandbox,spmi";
1459 #address-cells = <0x1>;
1460 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -06001461 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001462 pm8916@0 {
1463 compatible = "qcom,spmi-pmic";
1464 reg = <0x0 0x1>;
1465 #address-cells = <0x1>;
1466 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -06001467 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001468
1469 spmi_gpios: gpios@c000 {
1470 compatible = "qcom,pm8916-gpio";
1471 reg = <0xc000 0x400>;
1472 gpio-controller;
1473 gpio-count = <4>;
1474 #gpio-cells = <2>;
1475 gpio-bank-name="spmi";
1476 };
1477 };
1478 };
maxims@google.comdaea6d42017-04-17 12:00:21 -07001479
1480 wdt0: wdt@0 {
1481 compatible = "sandbox,wdt";
Rasmus Villemoesf91ff5a2021-08-19 11:57:06 +02001482 hw_margin_ms = <200>;
maxims@google.comdaea6d42017-04-17 12:00:21 -07001483 };
Rob Clarka471b672018-01-10 11:33:30 +01001484
Mario Six95922152018-08-09 14:51:19 +02001485 axi: axi@0 {
1486 compatible = "sandbox,axi";
1487 #address-cells = <0x1>;
1488 #size-cells = <0x1>;
1489 store@0 {
1490 compatible = "sandbox,sandbox_store";
1491 reg = <0x0 0x400>;
1492 };
1493 };
1494
Rob Clarka471b672018-01-10 11:33:30 +01001495 chosen {
Simon Glass305ac9a2018-02-03 10:36:58 -07001496 #address-cells = <1>;
1497 #size-cells = <1>;
Simon Glassf3455962020-01-27 08:49:43 -07001498 setting = "sunrise ohoka";
1499 other-node = "/some-bus/c-test@5";
Simon Glasse09223c2020-01-27 08:49:46 -07001500 int-values = <0x1937 72993>;
Simon Glass3c601b12020-07-07 13:12:06 -06001501 u-boot,acpi-ssdt-order = <&acpi_test2 &acpi_test1>;
Rob Clarka471b672018-01-10 11:33:30 +01001502 chosen-test {
1503 compatible = "denx,u-boot-fdt-test";
1504 reg = <9 1>;
1505 };
1506 };
Mario Six35616ef2018-03-12 14:53:33 +01001507
1508 translation-test@8000 {
1509 compatible = "simple-bus";
1510 reg = <0x8000 0x4000>;
1511
1512 #address-cells = <0x2>;
1513 #size-cells = <0x1>;
1514
1515 ranges = <0 0x0 0x8000 0x1000
1516 1 0x100 0x9000 0x1000
1517 2 0x200 0xA000 0x1000
1518 3 0x300 0xB000 0x1000
1519 >;
1520
Fabien Dessenne22236e02019-05-31 15:11:30 +02001521 dma-ranges = <0 0x000 0x10000000 0x1000
1522 1 0x100 0x20000000 0x1000
1523 >;
1524
Mario Six35616ef2018-03-12 14:53:33 +01001525 dev@0,0 {
1526 compatible = "denx,u-boot-fdt-dummy";
1527 reg = <0 0x0 0x1000>;
Álvaro Fernåndez Rojasa3181152018-12-03 19:37:09 +01001528 reg-names = "sandbox-dummy-0";
Mario Six35616ef2018-03-12 14:53:33 +01001529 };
1530
1531 dev@1,100 {
1532 compatible = "denx,u-boot-fdt-dummy";
1533 reg = <1 0x100 0x1000>;
1534
1535 };
1536
1537 dev@2,200 {
1538 compatible = "denx,u-boot-fdt-dummy";
1539 reg = <2 0x200 0x1000>;
1540 };
1541
1542
1543 noxlatebus@3,300 {
1544 compatible = "simple-bus";
1545 reg = <3 0x300 0x1000>;
1546
1547 #address-cells = <0x1>;
1548 #size-cells = <0x0>;
1549
1550 dev@42 {
1551 compatible = "denx,u-boot-fdt-dummy";
1552 reg = <0x42>;
1553 };
1554 };
1555 };
Mario Six02ad6fb2018-09-27 09:19:31 +02001556
Dzmitry Sankouski54f4c832023-01-22 18:21:23 +03001557 ofnode-foreach {
1558 compatible = "foreach";
1559
1560 first {
1561 prop1 = <1>;
1562 prop2 = <2>;
1563 };
1564
1565 second {
1566 prop1 = <1>;
1567 prop2 = <2>;
1568 };
1569 };
1570
Mario Six02ad6fb2018-09-27 09:19:31 +02001571 osd {
1572 compatible = "sandbox,sandbox_osd";
1573 };
Tom Rinib93eea72018-09-30 18:16:51 -04001574
Jens Wiklander86afaa62018-09-25 16:40:16 +02001575 sandbox_tee {
1576 compatible = "sandbox,tee";
1577 };
Bin Meng1bb290d2018-10-15 02:21:26 -07001578
1579 sandbox_virtio1 {
1580 compatible = "sandbox,virtio1";
Simon Glass8de5a542023-01-17 10:47:51 -07001581 virtio-type = <4>; /* rng */
Bin Meng1bb290d2018-10-15 02:21:26 -07001582 };
1583
1584 sandbox_virtio2 {
1585 compatible = "sandbox,virtio2";
1586 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001587
Simon Glass8de5a542023-01-17 10:47:51 -07001588 sandbox-virtio-blk {
1589 compatible = "sandbox,virtio1";
1590 virtio-type = <2>; /* block */
1591 };
1592
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +02001593 sandbox_scmi {
1594 compatible = "sandbox,scmi-devices";
Etienne Carrierebf1f1322022-02-21 09:22:41 +01001595 clocks = <&clk_scmi 2>, <&clk_scmi 0>;
Etienne Carriere09665cb2022-02-21 09:22:39 +01001596 resets = <&reset_scmi 3>;
1597 regul0-supply = <&regul0_scmi>;
1598 regul1-supply = <&regul1_scmi>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +02001599 };
1600
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001601 pinctrl {
1602 compatible = "sandbox,pinctrl";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001603
Sean Anderson3438e3b2020-09-14 11:01:57 -04001604 pinctrl-names = "default", "alternate";
1605 pinctrl-0 = <&pinctrl_gpios>, <&pinctrl_i2s>;
1606 pinctrl-1 = <&pinctrl_spi>, <&pinctrl_i2c>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001607
Sean Anderson3438e3b2020-09-14 11:01:57 -04001608 pinctrl_gpios: gpios {
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001609 gpio0 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001610 pins = "P5";
1611 function = "GPIO";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001612 bias-pull-up;
1613 input-disable;
1614 };
1615 gpio1 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001616 pins = "P6";
1617 function = "GPIO";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001618 output-high;
1619 drive-open-drain;
1620 };
1621 gpio2 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001622 pinmux = <SANDBOX_PINMUX(7, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001623 bias-pull-down;
1624 input-enable;
1625 };
1626 gpio3 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001627 pinmux = <SANDBOX_PINMUX(8, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001628 bias-disable;
1629 };
1630 };
Sean Anderson3438e3b2020-09-14 11:01:57 -04001631
1632 pinctrl_i2c: i2c {
1633 groups {
1634 groups = "I2C_UART";
1635 function = "I2C";
1636 };
1637
1638 pins {
1639 pins = "P0", "P1";
1640 drive-open-drain;
1641 };
1642 };
1643
1644 pinctrl_i2s: i2s {
1645 groups = "SPI_I2S";
1646 function = "I2S";
1647 };
1648
1649 pinctrl_spi: spi {
1650 groups = "SPI_I2S";
1651 function = "SPI";
1652
1653 cs {
1654 pinmux = <SANDBOX_PINMUX(5, SANDBOX_PINMUX_CS)>,
1655 <SANDBOX_PINMUX(6, SANDBOX_PINMUX_CS)>;
1656 };
1657 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001658 };
Benjamin Gaignarda550b542018-11-27 13:49:50 +01001659
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001660 pinctrl-single-no-width {
1661 compatible = "pinctrl-single";
1662 reg = <0x0000 0x238>;
1663 #pinctrl-cells = <1>;
1664 pinctrl-single,function-mask = <0x7f>;
1665 };
1666
1667 pinctrl-single-pins {
1668 compatible = "pinctrl-single";
1669 reg = <0x0000 0x238>;
1670 #pinctrl-cells = <1>;
1671 pinctrl-single,register-width = <32>;
1672 pinctrl-single,function-mask = <0x7f>;
1673
1674 pinmux_pwm_pins: pinmux_pwm_pins {
1675 pinctrl-single,pins = < 0x48 0x06 >;
1676 };
1677
1678 pinmux_spi0_pins: pinmux_spi0_pins {
1679 pinctrl-single,pins = <
1680 0x190 0x0c
1681 0x194 0x0c
1682 0x198 0x23
1683 0x19c 0x0c
1684 >;
1685 };
1686
1687 pinmux_uart0_pins: pinmux_uart0_pins {
1688 pinctrl-single,pins = <
1689 0x70 0x30
1690 0x74 0x00
1691 >;
1692 };
1693 };
1694
1695 pinctrl-single-bits {
1696 compatible = "pinctrl-single";
1697 reg = <0x0000 0x50>;
1698 #pinctrl-cells = <2>;
1699 pinctrl-single,bit-per-mux;
1700 pinctrl-single,register-width = <32>;
1701 pinctrl-single,function-mask = <0xf>;
1702
1703 pinmux_i2c0_pins: pinmux_i2c0_pins {
1704 pinctrl-single,bits = <
1705 0x10 0x00002200 0x0000ff00
1706 >;
1707 };
1708
1709 pinmux_lcd_pins: pinmux_lcd_pins {
1710 pinctrl-single,bits = <
1711 0x40 0x22222200 0xffffff00
1712 0x44 0x22222222 0xffffffff
1713 0x48 0x00000022 0x000000ff
1714 0x48 0x02000000 0x0f000000
1715 0x4c 0x02000022 0x0f0000ff
1716 >;
1717 };
1718 };
1719
Benjamin Gaignarda550b542018-11-27 13:49:50 +01001720 hwspinlock@0 {
1721 compatible = "sandbox,hwspinlock";
1722 };
Grygorii Strashko19ebf0b2018-11-28 19:17:51 +01001723
1724 dma: dma {
1725 compatible = "sandbox,dma";
1726 #dma-cells = <1>;
1727
1728 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
1729 dma-names = "m2m", "tx0", "rx0";
1730 };
Alex Marginean0daa53a2019-06-03 19:12:28 +03001731
Alex Marginean0649be52019-07-12 10:13:53 +03001732 /*
1733 * keep mdio-mux ahead of mdio so that the mux is removed first at the
1734 * end of the test. If parent mdio is removed first, clean-up of the
1735 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
1736 * active at the end of the test. That it turn doesn't allow the mdio
1737 * class to be destroyed, triggering an error.
1738 */
1739 mdio-mux-test {
1740 compatible = "sandbox,mdio-mux";
1741 #address-cells = <1>;
1742 #size-cells = <0>;
1743 mdio-parent-bus = <&mdio>;
1744
1745 mdio-ch-test@0 {
1746 reg = <0>;
1747 };
1748 mdio-ch-test@1 {
1749 reg = <1>;
1750 };
1751 };
1752
1753 mdio: mdio-test {
Alex Marginean0daa53a2019-06-03 19:12:28 +03001754 compatible = "sandbox,mdio";
Marek BehĂșnf4f1ddc2022-04-07 00:32:57 +02001755 #address-cells = <1>;
1756 #size-cells = <0>;
1757
1758 ethphy1: ethernet-phy@1 {
1759 reg = <1>;
1760 };
Alex Marginean0daa53a2019-06-03 19:12:28 +03001761 };
Sean Andersonb7860542020-06-24 06:41:12 -04001762
1763 pm-bus-test {
1764 compatible = "simple-pm-bus";
1765 clocks = <&clk_sandbox 4>;
1766 power-domains = <&pwrdom 1>;
1767 };
Sean Anderson0c1f6bf2020-06-24 06:41:14 -04001768
1769 resetc2: syscon-reset {
1770 compatible = "syscon-reset";
1771 #reset-cells = <1>;
1772 regmap = <&syscon0>;
1773 offset = <1>;
1774 mask = <0x27FFFFFF>;
1775 assert-high = <0>;
1776 };
1777
1778 syscon-reset-test {
1779 compatible = "sandbox,misc_sandbox";
1780 resets = <&resetc2 15>, <&resetc2 30>, <&resetc2 60>;
1781 reset-names = "valid", "no_mask", "out_of_range";
1782 };
Jean-Jacques Hiblot0b89fc52020-09-24 10:04:18 +05301783
Simon Glass458b66a2020-11-05 06:32:05 -07001784 sysinfo {
1785 compatible = "sandbox,sysinfo-sandbox";
1786 };
1787
Sean Anderson1c830672021-04-20 10:50:58 -04001788 sysinfo-gpio {
1789 compatible = "gpio-sysinfo";
1790 gpios = <&gpio_a 15>, <&gpio_a 16>, <&gpio_a 17>;
1791 revisions = <19>, <5>;
1792 names = "rev_a", "foo";
1793 };
1794
Jean-Jacques Hiblot0b89fc52020-09-24 10:04:18 +05301795 some_regmapped-bus {
1796 #address-cells = <0x1>;
1797 #size-cells = <0x1>;
1798
1799 ranges = <0x0 0x0 0x10>;
1800 compatible = "simple-bus";
1801
1802 regmap-test_0 {
1803 reg = <0 0x10>;
1804 compatible = "sandbox,regmap_test";
1805 };
1806 };
Robert Marko9cf87122022-09-06 13:30:35 +02001807
1808 thermal {
1809 compatible = "sandbox,thermal";
1810 };
Sughosh Ganu77079e72022-10-21 18:16:05 +05301811
1812 fwu-mdata {
1813 compatible = "u-boot,fwu-mdata-gpt";
1814 fwu-mdata-store = <&mmc0>;
1815 };
Abdellatif El Khlifi6b005872023-04-17 10:11:55 +01001816
1817 nvmxip-qspi1@08000000 {
1818 compatible = "nvmxip,qspi";
1819 reg = <0x08000000 0x00200000>;
1820 lba_shift = <9>;
1821 lba = <4096>;
1822 };
1823
1824 nvmxip-qspi2@08200000 {
1825 compatible = "nvmxip,qspi";
1826 reg = <0x08200000 0x00100000>;
1827 lba_shift = <9>;
1828 lba = <2048>;
1829 };
Svyatoslav Ryhel669f5c82023-04-25 10:57:21 +03001830
1831 extcon {
1832 compatible = "sandbox,extcon";
1833 };
Simon Glassb2c1cac2014-02-26 15:59:21 -07001834};
Przemyslaw Marczak77bee052015-05-13 13:38:35 +02001835
1836#include "sandbox_pmic.dtsi"
Heinrich Schuchardte24fdef2021-02-18 13:01:35 +01001837#include "cros-ec-keyboard.dtsi"
Simon Glass5e135d32022-10-20 18:23:15 -06001838
1839#ifdef CONFIG_SANDBOX_VPL
1840#include "sandbox_vpl.dtsi"
1841#endif
Simon Glass61300722023-06-01 10:23:01 -06001842
1843#include "cedit.dtsi"