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Masahiro Yamadacc85b7b2015-07-26 02:46:26 +09001#
2# I2C subsystem configuration
3#
4
Simon Glass8e85e3c2021-07-10 21:14:35 -06005menuconfig I2C
6 bool "I2C support"
7 default y
8 help
9 Note:
10 This is a stand-in for an option to enable I2C support. In fact this
11 simply enables building of the I2C directory for U-Boot. The actual
12 I2C feature is enabled by DM_I2C (for driver model) and
13 the #define CONFIG_SYS_I2C_LEGACY (for the legacy I2C stack).
14
15 So at present there is no need to ever disable this option.
16
17 Eventually it will:
18
19 Enable support for the I2C (Inter-Integrated Circuit) bus in U-Boot.
20 I2C works with a clock and data line which can be driven by a
21 one or more masters or slaves. It is a fairly complex bus but is
22 widely used as it only needs two lines for communication. Speeds of
23 400kbps are typical but up to 3.4Mbps is supported by some
24 hardware. Enable this option to build the drivers in drivers/i2c as
25 part of a U-Boot build.
26
27if I2C
Masahiro Yamadacc85b7b2015-07-26 02:46:26 +090028
Masahiro Yamadacd5cf8e2015-01-13 12:44:35 +090029config DM_I2C
30 bool "Enable Driver Model for I2C drivers"
31 depends on DM
32 help
Przemyslaw Marczake5fa1212015-03-31 18:57:17 +020033 Enable driver model for I2C. The I2C uclass interface: probe, read,
34 write and speed, is implemented with the bus drivers operations,
35 which provide methods for bus setting and data transfer. Each chip
Simon Glass71fa5b42020-12-03 16:55:18 -070036 device (bus child) info is kept as parent plat. The interface
Bartosz Golaszewski1e4450c2019-07-29 08:58:00 +020037 is defined in include/i2c.h.
Simon Glasse200ee22015-02-13 12:20:48 -070038
Igor Opaniuk964f2322021-02-09 13:52:43 +020039config SPL_DM_I2C
40 bool "Enable Driver Model for I2C drivers in SPL"
41 depends on SPL_DM && DM_I2C
42 default y
43 help
44 Enable driver model for I2C. The I2C uclass interface: probe, read,
45 write and speed, is implemented with the bus drivers operations,
46 which provide methods for bus setting and data transfer. Each chip
47 device (bus child) info is kept as parent platdata. The interface
48 is defined in include/i2c.h.
49
Simon Glass0e01c622023-02-22 09:34:06 -070050config TPL_DM_I2C
51 bool "Enable Driver Model for I2C drivers in TPL"
52 depends on TPL_DM && DM_I2C
53 help
54 Enable driver model for I2C. The I2C uclass interface: probe, read,
55 write and speed, is implemented with the bus drivers operations,
56 which provide methods for bus setting and data transfer. Each chip
57 device (bus child) info is kept as parent platdata. The interface
58 is defined in include/i2c.h.
59
Simon Glasse7ca7da2022-04-30 00:56:53 -060060config VPL_DM_I2C
61 bool "Enable Driver Model for I2C drivers in VPL"
62 depends on VPL_DM && DM_I2C
63 default y
64 help
65 Enable driver model for I2C. The I2C uclass interface: probe, read,
66 write and speed, is implemented with the bus drivers operations,
67 which provide methods for bus setting and data transfer. Each chip
68 device (bus child) info is kept as parent platdata. The interface
69 is defined in include/i2c.h.
70
Tom Rini52b2e262021-08-18 23:12:24 -040071config SYS_I2C_LEGACY
72 bool "Enable legacy I2C subsystem and drivers"
73 depends on !DM_I2C
74 help
75 Enable the legacy I2C subsystem and drivers. While this is
76 deprecated in U-Boot itself, this can be useful in some situations
77 in SPL or TPL.
78
79config SPL_SYS_I2C_LEGACY
80 bool "Enable legacy I2C subsystem and drivers in SPL"
81 depends on SUPPORT_SPL && !SPL_DM_I2C
82 help
83 Enable the legacy I2C subsystem and drivers in SPL. This is useful
84 in some size constrained situations.
85
86config TPL_SYS_I2C_LEGACY
87 bool "Enable legacy I2C subsystem and drivers in TPL"
88 depends on SUPPORT_TPL && !SPL_DM_I2C
89 help
90 Enable the legacy I2C subsystem and drivers in TPL. This is useful
91 in some size constrained situations.
92
Tom Rini714482a2021-08-18 23:12:25 -040093config SYS_I2C_EARLY_INIT
94 bool "Enable legacy I2C subsystem early in boot"
95 depends on BOARD_EARLY_INIT_F && SPL_SYS_I2C_LEGACY && SYS_I2C_MXC
96 help
97 Add the function prototype for i2c_early_init_f which is called in
98 board_early_init_f.
99
Simon Glass9ad07af2015-08-03 08:19:23 -0600100config I2C_CROS_EC_TUNNEL
101 tristate "Chrome OS EC tunnel I2C bus"
102 depends on CROS_EC
103 help
104 This provides an I2C bus that will tunnel i2c commands through to
105 the other side of the Chrome OS EC to the I2C bus connected there.
106 This will work whatever the interface used to talk to the EC (SPI,
107 I2C or LPC). Some Chromebooks use this when the hardware design
108 does not allow direct access to the main PMIC from the AP.
109
Simon Glasseb2cc512015-08-03 08:19:24 -0600110config I2C_CROS_EC_LDO
111 bool "Provide access to LDOs on the Chrome OS EC"
112 depends on CROS_EC
113 ---help---
114 On many Chromebooks the main PMIC is inaccessible to the AP. This is
115 often dealt with by using an I2C pass-through interface provided by
116 the EC. On some unfortunate models (e.g. Spring) the pass-through
117 is not available, and an LDO message is available instead. This
118 option enables a driver which provides very basic access to those
119 regulators, via the EC. We implement this as an I2C bus which
120 emulates just the TPS65090 messages we know about. This is done to
121 avoid duplicating the logic in the TPS65090 regulator driver for
122 enabling/disabling an LDO.
Simon Glass9ad07af2015-08-03 08:19:23 -0600123
Lukasz Majewski0a556272017-03-21 12:08:25 +0100124config I2C_SET_DEFAULT_BUS_NUM
125 bool "Set default I2C bus number"
126 depends on DM_I2C
127 help
128 Set default number of I2C bus to be accessed. This option provides
129 behaviour similar to old (i.e. pre DM) I2C bus driver.
130
131config I2C_DEFAULT_BUS_NUMBER
132 hex "I2C default bus number"
133 depends on I2C_SET_DEFAULT_BUS_NUM
134 default 0x0
135 help
136 Number of default I2C bus to use
137
Przemyslaw Marczakd3aa7e12015-03-31 18:57:18 +0200138config DM_I2C_GPIO
139 bool "Enable Driver Model for software emulated I2C bus driver"
140 depends on DM_I2C && DM_GPIO
141 help
142 Enable the i2c bus driver emulation by using the GPIOs. The bus GPIO
143 configuration is given by the device tree. Kernel-style device tree
144 bindings are supported.
145 Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt
146
Igor Opaniuk964f2322021-02-09 13:52:43 +0200147config SPL_DM_I2C_GPIO
148 bool "Enable Driver Model for software emulated I2C bus driver in SPL"
Simon Glass035939e2021-07-10 21:14:30 -0600149 depends on SPL_DM && DM_I2C_GPIO && SPL_DM_GPIO && SPL_GPIO
Igor Opaniuk964f2322021-02-09 13:52:43 +0200150 default y
151 help
152 Enable the i2c bus driver emulation by using the GPIOs. The bus GPIO
153 configuration is given by the device tree. Kernel-style device tree
154 bindings are supported.
155 Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt
156
Songjun Wu26d88282016-06-20 13:22:38 +0800157config SYS_I2C_AT91
158 bool "Atmel I2C driver"
159 depends on DM_I2C && ARCH_AT91
160 help
161 Add support for the Atmel I2C driver. A serious problem is that there
162 is no documented way to issue repeated START conditions for more than
163 two messages, as needed to support combined I2C messages. Use the
164 i2c-gpio driver unless your system can cope with this limitation.
165 Binding info: doc/device-tree-bindings/i2c/i2c-at91.txt
166
Rayagonda Kokatanurd5dc36f2020-04-08 11:12:27 +0530167config SYS_I2C_IPROC
168 bool "Broadcom I2C driver"
169 depends on DM_I2C
170 help
171 Broadcom I2C driver.
172 Add support for Broadcom I2C driver.
173 Say yes here to to enable the Broadco I2C driver.
174
mario.six@gdsys.cc349686c2016-04-25 08:31:09 +0200175config SYS_I2C_FSL
176 bool "Freescale I2C bus driver"
mario.six@gdsys.cc349686c2016-04-25 08:31:09 +0200177 help
178 Add support for Freescale I2C busses as used on MPC8240, MPC8245, and
179 MPC85xx processors.
180
Tom Rinibe94c762021-08-18 23:12:35 -0400181if SYS_I2C_FSL && (SYS_I2C_LEGACY || SPL_SYS_I2C_LEGACY)
182config SYS_FSL_I2C_OFFSET
183 hex "Offset from the IMMR of the address of the first I2C controller"
184
185config SYS_FSL_HAS_I2C2_OFFSET
186 bool "Support a second I2C controller"
187
188config SYS_FSL_I2C2_OFFSET
189 hex "Offset from the IMMR of the address of the second I2C controller"
190 depends on SYS_FSL_HAS_I2C2_OFFSET
191
192config SYS_FSL_HAS_I2C3_OFFSET
193 bool "Support a third I2C controller"
194
195config SYS_FSL_I2C3_OFFSET
196 hex "Offset from the IMMR of the address of the third I2C controller"
197 depends on SYS_FSL_HAS_I2C3_OFFSET
198
199config SYS_FSL_HAS_I2C4_OFFSET
200 bool "Support a fourth I2C controller"
201
202config SYS_FSL_I2C4_OFFSET
203 hex "Offset from the IMMR of the address of the fourth I2C controller"
204 depends on SYS_FSL_HAS_I2C4_OFFSET
205endif
206
Moritz Fischer0075dac2015-12-28 09:47:11 -0800207config SYS_I2C_CADENCE
208 tristate "Cadence I2C Controller"
Michal Simekc28665d2020-08-06 15:18:36 +0200209 depends on DM_I2C
Moritz Fischer0075dac2015-12-28 09:47:11 -0800210 help
211 Say yes here to select Cadence I2C Host Controller. This controller is
212 e.g. used by Xilinx Zynq.
213
Arthur Life661ba2020-06-01 12:56:31 -0700214config SYS_I2C_CA
215 tristate "Cortina-Access I2C Controller"
216 depends on DM_I2C && CORTINA_PLATFORM
Arthur Life661ba2020-06-01 12:56:31 -0700217 help
218 Add support for the Cortina Access I2C host controller.
219 Say yes here to select Cortina-Access I2C Host Controller.
220
Adam Forddecc8952018-08-10 05:05:22 -0500221config SYS_I2C_DAVINCI
222 bool "Davinci I2C Controller"
223 depends on (ARCH_KEYSTONE || ARCH_DAVINCI)
224 help
225 Say yes here to add support for Davinci and Keystone I2C controller
226
Stefan Roeseb71955f2016-04-28 09:47:17 +0200227config SYS_I2C_DW
228 bool "Designware I2C Controller"
Stefan Roeseb71955f2016-04-28 09:47:17 +0200229 help
230 Say yes here to select the Designware I2C Host Controller. This
231 controller is used in various SoCs, e.g. the ST SPEAr, Altera
232 SoCFPGA, Synopsys ARC700 and some Intel x86 SoCs.
233
Minda Chen375be332023-07-25 17:46:47 +0800234config SYS_I2C_DW_PCI
235 bool "Designware PCI I2C Controller"
236 depends on SYS_I2C_DW && PCI && ACPIGEN
237 default y
238 help
239 Say yes here to select the Designware PCI I2C Host Controller.
240 This PCI I2C controller is the base on Desigware I2C host
241 controller.
242
Ryan Chen0c7132a2023-01-30 14:19:24 +0800243config SYS_I2C_AST2600
244 bool "AST2600 I2C Controller"
245 depends on DM_I2C && ARCH_ASPEED
246 help
247 Say yes here to select AST2600 I2C Host Controller. The driver
248 support AST2600 I2C new mode register. This I2C controller supports:
249 _Standard-mode (up to 100 kHz)
250 _Fast-mode (up to 400 kHz)
251 _Fast-mode Plus (up to 1 MHz)
252
maxims@google.com7f613312017-04-17 12:00:30 -0700253config SYS_I2C_ASPEED
254 bool "Aspeed I2C Controller"
255 depends on DM_I2C && ARCH_ASPEED
256 help
257 Say yes here to select Aspeed I2C Host Controller. The driver
258 supports AST2500 and AST2400 controllers, but is very limited.
259 Only single master mode is supported and only byte-by-byte
260 synchronous reads and writes are supported, no Pool Buffers or DMA.
261
Simon Glass5e66fdc2016-01-17 16:11:44 -0700262config SYS_I2C_INTEL
263 bool "Intel I2C/SMBUS driver"
264 depends on DM_I2C
265 help
266 Add support for the Intel SMBUS driver. So far this driver is just
267 a stub which perhaps some basic init. There is no implementation of
268 the I2C API meaning that any I2C operations will immediately fail
269 for now.
270
Peng Fand684adb2017-02-24 09:54:18 +0800271config SYS_I2C_IMX_LPI2C
272 bool "NXP i.MX LPI2C driver"
Peng Fand684adb2017-02-24 09:54:18 +0800273 help
274 Add support for the NXP i.MX LPI2C driver.
275
Trevor Woerner5f37e502021-06-10 22:37:08 -0400276config SYS_I2C_LPC32XX
277 bool "LPC32XX I2C driver"
278 depends on ARCH_LPC32XX
279 help
280 Enable support for the LPC32xx I2C driver.
281
Beniamino Galvanid5b199c2017-10-29 10:09:00 +0100282config SYS_I2C_MESON
283 bool "Amlogic Meson I2C driver"
284 depends on DM_I2C && ARCH_MESON
285 help
Beniamino Galvani83b153d2017-11-26 17:40:54 +0100286 Add support for the I2C controller available in Amlogic Meson
287 SoCs. The controller supports programmable bus speed including
288 standard (100kbits/s) and fast (400kbit/s) speed and allows the
289 software to define a flexible format of the bit streams. It has an
290 internal buffer holding up to 8 bytes for transfers and supports
291 both 7-bit and 10-bit addresses.
Beniamino Galvanid5b199c2017-10-29 10:09:00 +0100292
developer301212f2022-09-09 19:59:48 +0800293config SYS_I2C_MTK
294 bool "MediaTek I2C driver"
295 help
296 This selects the MediaTek Integrated Inter Circuit bus driver.
297 The I2C bus adapter is the base for some other I2C client,
298 eg: touch, sensors.
299 If you want to use MediaTek I2C interface, say Y here.
300 If unsure, say N.
301
Padmarao Begari7ddb4ec2021-11-17 18:21:16 +0530302config SYS_I2C_MICROCHIP
303 bool "Microchip I2C driver"
304 help
305 Add support for the Microchip I2C driver. This is operating on
306 standard mode up to 100 kbits/s and fast mode up to 400 kbits/s.
307
Jagan Teki0aedd7f2016-12-06 00:00:57 +0100308config SYS_I2C_MXC
Sriram Dash7122a0c2018-02-06 11:26:30 +0530309 bool "NXP MXC I2C driver"
Jagan Teki0aedd7f2016-12-06 00:00:57 +0100310 help
Chris Packham94d0d3d2019-01-13 22:13:25 +1300311 Add support for the NXP I2C driver. This supports up to four bus
312 channels and operating on standard mode up to 100 kbits/s and fast
313 mode up to 400 kbits/s.
Jagan Teki0aedd7f2016-12-06 00:00:57 +0100314
Tom Rini1a195882021-08-18 23:12:33 -0400315if SYS_I2C_MXC && (SYS_I2C_LEGACY || SPL_SYS_I2C_LEGACY)
Sriram Dash7122a0c2018-02-06 11:26:30 +0530316config SYS_I2C_MXC_I2C1
317 bool "NXP MXC I2C1"
318 help
319 Add support for NXP MXC I2C Controller 1.
320 Required for SoCs which have I2C MXC controller 1 eg LS1088A, LS2080A
321
322config SYS_I2C_MXC_I2C2
323 bool "NXP MXC I2C2"
324 help
325 Add support for NXP MXC I2C Controller 2.
326 Required for SoCs which have I2C MXC controller 2 eg LS1088A, LS2080A
327
328config SYS_I2C_MXC_I2C3
329 bool "NXP MXC I2C3"
330 help
331 Add support for NXP MXC I2C Controller 3.
332 Required for SoCs which have I2C MXC controller 3 eg LS1088A, LS2080A
333
334config SYS_I2C_MXC_I2C4
335 bool "NXP MXC I2C4"
336 help
337 Add support for NXP MXC I2C Controller 4.
338 Required for SoCs which have I2C MXC controller 4 eg LS1088A, LS2080A
Sriram Dasha64aa192018-02-06 11:26:31 +0530339
340config SYS_I2C_MXC_I2C5
341 bool "NXP MXC I2C5"
342 help
343 Add support for NXP MXC I2C Controller 5.
344 Required for SoCs which have I2C MXC controller 5 eg LX2160A
345
346config SYS_I2C_MXC_I2C6
347 bool "NXP MXC I2C6"
348 help
349 Add support for NXP MXC I2C Controller 6.
350 Required for SoCs which have I2C MXC controller 6 eg LX2160A
351
352config SYS_I2C_MXC_I2C7
353 bool "NXP MXC I2C7"
354 help
355 Add support for NXP MXC I2C Controller 7.
356 Required for SoCs which have I2C MXC controller 7 eg LX2160A
357
358config SYS_I2C_MXC_I2C8
359 bool "NXP MXC I2C8"
360 help
361 Add support for NXP MXC I2C Controller 8.
362 Required for SoCs which have I2C MXC controller 8 eg LX2160A
Sriram Dash7122a0c2018-02-06 11:26:30 +0530363endif
364
365if SYS_I2C_MXC_I2C1
366config SYS_MXC_I2C1_SPEED
367 int "I2C Channel 1 speed"
Tom Rini48425b12021-02-09 08:03:10 -0500368 default 40000000 if TARGET_LS2080A_EMU
Sriram Dash7122a0c2018-02-06 11:26:30 +0530369 default 100000
370 help
371 MXC I2C Channel 1 speed
372
373config SYS_MXC_I2C1_SLAVE
Tom Rini1a195882021-08-18 23:12:33 -0400374 hex "I2C1 Slave"
Tom Rinif18679c2023-08-02 11:09:43 -0400375 default 0x0
Sriram Dash7122a0c2018-02-06 11:26:30 +0530376 help
377 MXC I2C1 Slave
378endif
379
380if SYS_I2C_MXC_I2C2
381config SYS_MXC_I2C2_SPEED
382 int "I2C Channel 2 speed"
Tom Rini48425b12021-02-09 08:03:10 -0500383 default 40000000 if TARGET_LS2080A_EMU
Sriram Dash7122a0c2018-02-06 11:26:30 +0530384 default 100000
385 help
386 MXC I2C Channel 2 speed
387
388config SYS_MXC_I2C2_SLAVE
Tom Rini1a195882021-08-18 23:12:33 -0400389 hex "I2C2 Slave"
Tom Rinif18679c2023-08-02 11:09:43 -0400390 default 0x0
Sriram Dash7122a0c2018-02-06 11:26:30 +0530391 help
392 MXC I2C2 Slave
393endif
394
395if SYS_I2C_MXC_I2C3
396config SYS_MXC_I2C3_SPEED
397 int "I2C Channel 3 speed"
398 default 100000
399 help
400 MXC I2C Channel 3 speed
401
402config SYS_MXC_I2C3_SLAVE
Tom Rini1a195882021-08-18 23:12:33 -0400403 hex "I2C3 Slave"
Tom Rinif18679c2023-08-02 11:09:43 -0400404 default 0x0
Sriram Dash7122a0c2018-02-06 11:26:30 +0530405 help
406 MXC I2C3 Slave
407endif
408
409if SYS_I2C_MXC_I2C4
410config SYS_MXC_I2C4_SPEED
411 int "I2C Channel 4 speed"
412 default 100000
413 help
414 MXC I2C Channel 4 speed
415
416config SYS_MXC_I2C4_SLAVE
Tom Rini1a195882021-08-18 23:12:33 -0400417 hex "I2C4 Slave"
Tom Rinif18679c2023-08-02 11:09:43 -0400418 default 0x0
Sriram Dash7122a0c2018-02-06 11:26:30 +0530419 help
420 MXC I2C4 Slave
421endif
422
Sriram Dasha64aa192018-02-06 11:26:31 +0530423if SYS_I2C_MXC_I2C5
424config SYS_MXC_I2C5_SPEED
425 int "I2C Channel 5 speed"
426 default 100000
427 help
428 MXC I2C Channel 5 speed
429
430config SYS_MXC_I2C5_SLAVE
Tom Rini1a195882021-08-18 23:12:33 -0400431 hex "I2C5 Slave"
Tom Rinif18679c2023-08-02 11:09:43 -0400432 default 0x0
Sriram Dasha64aa192018-02-06 11:26:31 +0530433 help
434 MXC I2C5 Slave
435endif
436
437if SYS_I2C_MXC_I2C6
438config SYS_MXC_I2C6_SPEED
439 int "I2C Channel 6 speed"
440 default 100000
441 help
442 MXC I2C Channel 6 speed
443
444config SYS_MXC_I2C6_SLAVE
Tom Rini1a195882021-08-18 23:12:33 -0400445 hex "I2C6 Slave"
Tom Rinif18679c2023-08-02 11:09:43 -0400446 default 0x0
Sriram Dasha64aa192018-02-06 11:26:31 +0530447 help
448 MXC I2C6 Slave
449endif
450
451if SYS_I2C_MXC_I2C7
452config SYS_MXC_I2C7_SPEED
453 int "I2C Channel 7 speed"
454 default 100000
455 help
456 MXC I2C Channel 7 speed
457
458config SYS_MXC_I2C7_SLAVE
Tom Rini1a195882021-08-18 23:12:33 -0400459 hex "I2C7 Slave"
Tom Rinif18679c2023-08-02 11:09:43 -0400460 default 0x0
Sriram Dasha64aa192018-02-06 11:26:31 +0530461 help
462 MXC I2C7 Slave
463endif
464
465if SYS_I2C_MXC_I2C8
466config SYS_MXC_I2C8_SPEED
467 int "I2C Channel 8 speed"
468 default 100000
469 help
470 MXC I2C Channel 8 speed
471
472config SYS_MXC_I2C8_SLAVE
Tom Rini1a195882021-08-18 23:12:33 -0400473 hex "I2C8 Slave"
Tom Rinif18679c2023-08-02 11:09:43 -0400474 default 0x0
Sriram Dasha64aa192018-02-06 11:26:31 +0530475 help
476 MXC I2C8 Slave
477endif
478
Stefan Bosch9d85dfb2020-07-10 19:07:28 +0200479config SYS_I2C_NEXELL
480 bool "Nexell I2C driver"
481 depends on DM_I2C
482 help
483 Add support for the Nexell I2C driver. This is used with various
484 Nexell parts such as S5Pxx18 series SoCs. All chips
485 have several I2C ports and all are provided, controlled by the
486 device tree.
487
Jim Liub84426c2022-06-23 13:31:42 +0800488config SYS_I2C_NPCM
489 bool "Nuvoton NPCM I2C driver"
490 help
491 Support for Nuvoton I2C controller driver.
492
Pragnesh Patel1cfbd7a2020-11-14 14:42:34 +0530493config SYS_I2C_OCORES
494 bool "ocores I2C driver"
495 depends on DM_I2C
496 help
497 Add support for ocores I2C controller. For details see
498 https://opencores.org/projects/i2c
499
Adam Ford85901162017-08-07 13:11:34 -0500500config SYS_I2C_OMAP24XX
501 bool "TI OMAP2+ I2C driver"
Vignesh R64d4f552019-06-04 18:08:11 -0500502 depends on ARCH_OMAP2PLUS || ARCH_K3
Adam Ford85901162017-08-07 13:11:34 -0500503 help
504 Add support for the OMAP2+ I2C driver.
505
Marek Vasut27165962018-04-21 18:57:28 +0200506config SYS_I2C_RCAR_I2C
507 bool "Renesas RCar I2C driver"
Hai Phamf39867d32023-02-28 22:25:51 +0100508 depends on (RCAR_GEN2 || RCAR_64) && DM_I2C
Marek Vasut27165962018-04-21 18:57:28 +0200509 help
510 Support for Renesas RCar I2C controller.
511
Marek Vasut125d8df2017-11-28 08:02:27 +0100512config SYS_I2C_RCAR_IIC
513 bool "Renesas RCar Gen3 IIC driver"
Marek Vasutc3909092023-02-28 00:03:45 +0100514 depends on (RCAR_GEN2 || RCAR_GEN3) && DM_I2C
Marek Vasut125d8df2017-11-28 08:02:27 +0100515 help
516 Support for Renesas RCar Gen3 IIC controller.
517
Simon Glass3595f952015-08-30 16:55:39 -0600518config SYS_I2C_ROCKCHIP
519 bool "Rockchip I2C driver"
520 depends on DM_I2C
521 help
522 Add support for the Rockchip I2C driver. This is used with various
523 Rockchip parts such as RK3126, RK3128, RK3036 and RK3288. All chips
Chris Packham94d0d3d2019-01-13 22:13:25 +1300524 have several I2C ports and all are provided, controlled by the
Simon Glass3595f952015-08-30 16:55:39 -0600525 device tree.
526
Paul Barker7fe0e0a2024-02-27 20:40:30 +0000527config SYS_I2C_RZ_RIIC
528 bool "Renesas RZ/G2L RIIC driver"
529 depends on RZG2L && DM_I2C
530 help
531 Support for the I2C controller (RIIC) on the Renesas RZ/G2L SoC
532 family.
533
Simon Glass39bc3be2015-03-06 13:19:04 -0700534config SYS_I2C_SANDBOX
535 bool "Sandbox I2C driver"
536 depends on SANDBOX && DM_I2C
Simon Glass0e01c622023-02-22 09:34:06 -0700537 default y
538 help
539 Enable I2C support for sandbox. This is an emulation of a real I2C
540 bus. Devices can be attached to the bus using the device tree
541 which specifies the driver to use. See sandbox.dts as an example.
542
543config SPL_SYS_I2C_SANDBOX
544 bool "Sandbox I2C driver (SPL)"
545 depends on SPL && SANDBOX && DM_I2C
546 default y
Simon Glass39bc3be2015-03-06 13:19:04 -0700547 help
548 Enable I2C support for sandbox. This is an emulation of a real I2C
549 bus. Devices can be attached to the bus using the device tree
Masahiro Yamada8d8371d2017-02-11 12:39:55 +0900550 which specifies the driver to use. See sandbox.dts as an example.
Simon Glass39bc3be2015-03-06 13:19:04 -0700551
Tom Rinib9a254d2021-08-18 23:12:34 -0400552config SYS_I2C_SH
553 bool "Legacy SuperH I2C interface"
Marek Vasut6468c4c2024-02-27 17:05:55 +0100554 depends on ARCH_RENESAS && SYS_I2C_LEGACY
Tom Rinib9a254d2021-08-18 23:12:34 -0400555 help
556 Enable the legacy SuperH I2C interface.
557
558if SYS_I2C_SH
559config SYS_I2C_SH_NUM_CONTROLLERS
560 int
561 default 5
562
563config SYS_I2C_SH_BASE0
564 hex
565 default 0xE6820000
566
567config SYS_I2C_SH_BASE1
568 hex
569 default 0xE6822000
570
571config SYS_I2C_SH_BASE2
572 hex
573 default 0xE6824000
574
575config SYS_I2C_SH_BASE3
576 hex
577 default 0xE6826000
578
579config SYS_I2C_SH_BASE4
580 hex
581 default 0xE6828000
582
583config SH_I2C_8BIT
584 bool
585 default y
586
587config SH_I2C_DATA_HIGH
588 int
589 default 4
590
591config SH_I2C_DATA_LOW
592 int
593 default 5
594
595config SH_I2C_CLOCK
596 int
597 default 104000000
598endif
599
Tom Rini5817ff02021-08-17 17:59:46 -0400600config SYS_I2C_SOFT
601 bool "Legacy software I2C interface"
602 help
603 Enable the legacy software defined I2C interface
604
605config SYS_I2C_SOFT_SPEED
606 int "Software I2C bus speed"
607 depends on SYS_I2C_SOFT
608 default 100000
609 help
610 Speed of the software I2C bus
611
612config SYS_I2C_SOFT_SLAVE
613 hex "Software I2C slave address"
614 depends on SYS_I2C_SOFT
615 default 0xfe
616 help
617 Slave address of the software I2C bus
618
Suneel Garapatic6baea22020-05-26 14:13:07 +0200619config SYS_I2C_OCTEON
620 bool "Octeon II/III/TX/TX2 I2C driver"
621 depends on (ARCH_OCTEON || ARCH_OCTEONTX || ARCH_OCTEONTX2) && DM_I2C
622 default y
623 help
624 Add support for the Marvell Octeon I2C driver. This is used with
625 various Octeon parts such as Octeon II/III and OcteonTX/TX2. All
626 chips have several I2C ports and all are provided, controlled by
627 the device tree.
628
Sumit Garg77e4c4e2023-02-01 19:29:00 +0530629config SYS_I2C_QUP
630 bool "Qualcomm QUP I2C controller"
631 depends on ARCH_SNAPDRAGON
632 help
633 Support for Qualcomm QUP I2C controller based on Qualcomm Universal
634 Peripherals (QUP) engine. The QUP engine is an advanced high
635 performance slave port that provides a common data path (an output
636 FIFO and an input FIFO) for I2C and SPI interfaces. The I2C/SPI QUP
637 controller is publicly documented in the Snapdragon 410E (APQ8016E)
638 Technical Reference Manual, chapter "6.1 Qualcomm Universal
639 Peripherals Engine (QUP)".
640
Neil Armstrong32325852024-04-22 11:33:52 +0200641config SYS_I2C_GENI
642 bool "Qualcomm Generic Interface (GENI) I2C controller"
643 depends on ARCH_SNAPDRAGON
644 help
645 Support for the Qualcomm Generic Interface (GENI) I2C interface.
646 The Generic Interface (GENI) is a firmware based Qualcomm Universal
647 Peripherals (QUP) Serial Engine (SE) Wrapper which can support multiple
648 bus protocols depending on the firmware type loaded at early boot time
649 based on system configuration.
650
Jaehoon Chungf7e6a032017-01-09 14:47:52 +0900651config SYS_I2C_S3C24X0
652 bool "Samsung I2C driver"
Tom Rinifc917de2021-08-17 17:59:42 -0400653 depends on (ARCH_EXYNOS4 || ARCH_EXYNOS5) && DM_I2C
Jaehoon Chungf7e6a032017-01-09 14:47:52 +0900654 help
655 Support for Samsung I2C controller as Samsung SoCs.
Simon Glass39bc3be2015-03-06 13:19:04 -0700656
Patrice Chotardebf442d2017-08-09 14:45:27 +0200657config SYS_I2C_STM32F7
658 bool "STMicroelectronics STM32F7 I2C support"
Patrick Delaunay85b53972018-03-12 10:46:10 +0100659 depends on (STM32F7 || STM32H7 || ARCH_STM32MP) && DM_I2C
Patrice Chotardebf442d2017-08-09 14:45:27 +0200660 help
661 Enable this option to add support for STM32 I2C controller
662 introduced with STM32F7/H7 SoCs. This I2C controller supports :
663 _ Slave and master modes
664 _ Multimaster capability
665 _ Standard-mode (up to 100 kHz)
666 _ Fast-mode (up to 400 kHz)
667 _ Fast-mode Plus (up to 1 MHz)
668 _ 7-bit and 10-bit addressing mode
669 _ Multiple 7-bit slave addresses (2 addresses, 1 with configurable mask)
670 _ All 7-bit addresses acknowledge mode
671 _ General call
672 _ Programmable setup and hold times
673 _ Easy to use event management
674 _ Optional clock stretching
675 _ Software reset
676
Samuel Holland60d49282021-10-08 00:17:20 -0500677config SYS_I2C_SUN6I_P2WI
678 bool "Allwinner sun6i P2WI controller"
679 depends on ARCH_SUNXI
680 help
681 Support for the P2WI (Push/Pull 2 Wire Interface) controller embedded
682 in the Allwinner A31 and A31s SOCs. This interface is used to connect
683 to specific devices like the X-Powers AXP221 PMIC.
684
Samuel Hollandb348efb2021-10-08 00:17:21 -0500685config SYS_I2C_SUN8I_RSB
686 bool "Allwinner sun8i Reduced Serial Bus controller"
687 depends on ARCH_SUNXI
688 help
689 Support for Allwinner's Reduced Serial Bus (RSB) controller. This
690 controller is responsible for communicating with various RSB based
691 devices, such as X-Powers AXPxxx PMICs and AC100/AC200 CODEC ICs.
692
Jassi Brar23325cf2021-06-04 18:44:48 +0900693config SYS_I2C_SYNQUACER
694 bool "Socionext SynQuacer I2C controller"
695 depends on ARCH_SYNQUACER && DM_I2C
696 help
697 Support for Socionext Synquacer I2C controller. This I2C controller
698 will be used for RTC and LS-connector on DeveloperBox.
699
Peter Robinson12d37d82019-02-20 12:17:26 +0000700config SYS_I2C_TEGRA
701 bool "NVIDIA Tegra internal I2C controller"
Trevor Woerner513f6402020-05-06 08:02:41 -0400702 depends on ARCH_TEGRA
Peter Robinson12d37d82019-02-20 12:17:26 +0000703 help
704 Support for NVIDIA I2C controller available in Tegra SoCs.
705
Masahiro Yamada96a42ed2015-01-13 12:44:36 +0900706config SYS_I2C_UNIPHIER
707 bool "UniPhier I2C driver"
708 depends on ARCH_UNIPHIER && DM_I2C
709 default y
710 help
Masahiro Yamada563ee4c2015-05-29 17:30:01 +0900711 Support for UniPhier I2C controller driver. This I2C controller
712 is used on PH1-LD4, PH1-sLD8 or older UniPhier SoCs.
Masahiro Yamada4e82e5e2015-01-13 12:44:37 +0900713
714config SYS_I2C_UNIPHIER_F
715 bool "UniPhier FIFO-builtin I2C driver"
716 depends on ARCH_UNIPHIER && DM_I2C
717 default y
718 help
Masahiro Yamada563ee4c2015-05-29 17:30:01 +0900719 Support for UniPhier FIFO-builtin I2C controller driver.
Masahiro Yamada4e82e5e2015-01-13 12:44:37 +0900720 This I2C controller is used on PH1-Pro4 or newer UniPhier SoCs.
Simon Glass2a80c402015-08-03 08:19:21 -0600721
Heiko Schochera37c1962018-10-11 07:26:33 +0200722config SYS_I2C_VERSATILE
723 bool "Arm Ltd Versatile I2C bus driver"
Tom Rini5af921e2021-02-20 20:05:47 -0500724 depends on DM_I2C && TARGET_VEXPRESS64_JUNO
Heiko Schochera37c1962018-10-11 07:26:33 +0200725 help
726 Add support for the Arm Ltd Versatile Express I2C driver. The I2C host
727 controller is present in the development boards manufactured by Arm Ltd.
728
Marek BehĂșn53929db2021-10-09 19:33:37 +0200729config SYS_I2C_MV
730 bool "Marvell PXA (Armada 3720) I2C driver"
731 help
732 Support for PXA based I2C controller used on Armada 3720 SoC.
733 In Linux, this driver is called i2c-pxa.
734
mario.six@gdsys.cc355a1272016-07-21 11:57:10 +0200735config SYS_I2C_MVTWSI
736 bool "Marvell I2C driver"
mario.six@gdsys.cc355a1272016-07-21 11:57:10 +0200737 help
738 Support for Marvell I2C controllers as used on the orion5x and
739 kirkwood SoC families.
740
Stephen Warren67a83482016-08-08 11:28:27 -0600741config TEGRA186_BPMP_I2C
742 bool "Enable Tegra186 BPMP-based I2C driver"
743 depends on TEGRA186_BPMP
744 help
745 Support for Tegra I2C controllers managed by the BPMP (Boot and
746 Power Management Processor). On Tegra186, some I2C controllers are
747 directly controlled by the main CPU, whereas others are controlled
748 by the BPMP, and can only be accessed by the main CPU via IPC
749 requests to the BPMP. This driver covers the latter case.
750
Tom Rinia6e29232021-08-18 23:12:32 -0400751config SYS_I2C_SLAVE
752 hex "I2C Slave address channel (all buses)"
753 depends on SYS_I2C_LEGACY || SPL_SYS_I2C_LEGACY || TPL_SYS_I2C_LEGACY
754 default 0xfe
755 help
756 I2C Slave address channel 0 for all buses in the legacy drivers.
757 Many boards/controllers/drivers don't support an I2C slave
758 interface so provide a default slave address for them for use in
759 common code. A real value for CONFIG_SYS_I2C_SLAVE should be
760 defined for any board which does support a slave interface and
761 this default used otherwise.
762
763config SYS_I2C_SPEED
764 int "I2C Slave channel 0 speed (all buses)"
765 depends on SYS_I2C_LEGACY || SPL_SYS_I2C_LEGACY || TPL_SYS_I2C_LEGACY
766 default 100000
767 help
768 I2C Slave speed channel 0 for all buses in the legacy drivers.
769
Adam Fordfa1dd3d2017-08-11 06:39:34 -0500770config SYS_I2C_BUS_MAX
771 int "Max I2C busses"
Tom Rinia2359f52022-06-27 13:35:50 -0400772 depends on ARCH_OMAP2PLUS || ARCH_SOCFPGA
Tom Rinia2359f52022-06-27 13:35:50 -0400773 default 3 if OMAP34XX || AM33XX || AM43XX
Tom Rini8c6b4372024-07-15 13:35:53 -0600774 default 4 if ARCH_SOCFPGA
Adam Fordfa1dd3d2017-08-11 06:39:34 -0500775 default 5 if OMAP54XX
776 help
777 Define the maximum number of available I2C buses.
778
Marek Vasut9de0e2a2018-12-19 12:26:27 +0100779config SYS_I2C_XILINX_XIIC
780 bool "Xilinx AXI I2C driver"
781 depends on DM_I2C
782 help
783 Support for Xilinx AXI I2C controller.
784
Mario Six3bb409c2018-01-15 11:08:11 +0100785config SYS_I2C_IHS
786 bool "gdsys IHS I2C driver"
787 depends on DM_I2C
788 help
789 Support for gdsys IHS I2C driver on FPGA bus.
790
Simon Glass2a80c402015-08-03 08:19:21 -0600791source "drivers/i2c/muxes/Kconfig"
Masahiro Yamadacc85b7b2015-07-26 02:46:26 +0900792
Simon Glass8e85e3c2021-07-10 21:14:35 -0600793endif