Blame - arch/arm/mach-socfpga/Kconfig - filogic/uboot

blob: f6e5773272d64ae81f3274414f0ca136191f3cc7 [file] [log] [blame]

Masahiro Yamada	144a3e0	2015-04-21 20:38:20 +0900	[diff] [blame]	1	if ARCH_SOCFPGA
				2
Simon Glass	f2a8946	2016-09-12 23:18:41 -0600	[diff] [blame]	3	config SPL_LIBCOMMON_SUPPORT
				4	default y
				5
Simon Glass	f6de257	2016-09-12 23:18:42 -0600	[diff] [blame]	6	config SPL_LIBDISK_SUPPORT
				7	default y
				8
Simon Glass	b16c92c	2016-09-12 23:18:43 -0600	[diff] [blame]	9	config SPL_LIBGENERIC_SUPPORT
				10	default y
				11
Simon Glass	bd58f1d	2016-09-12 23:18:44 -0600	[diff] [blame]	12	config SPL_MMC_SUPPORT
				13	default y if DM_MMC
				14
Simon Glass	d5a307a	2016-09-12 23:18:48 -0600	[diff] [blame]	15	config SPL_NAND_SUPPORT
				16	default y if SPL_NAND_DENALI
				17
Simon Glass	e076d6f	2016-09-12 23:18:56 -0600	[diff] [blame]	18	config SPL_SERIAL_SUPPORT
				19	default y
				20
Simon Glass	219d612	2016-09-12 23:18:57 -0600	[diff] [blame]	21	config SPL_SPI_FLASH_SUPPORT
Simon Glass	b24fdca	2016-09-12 23:18:58 -0600	[diff] [blame]	22	default y if SPL_SPI_SUPPORT
				23
				24	config SPL_SPI_SUPPORT
Simon Glass	219d612	2016-09-12 23:18:57 -0600	[diff] [blame]	25	default y if DM_SPI
				26
Simon Glass	6662a9f	2016-09-12 23:19:02 -0600	[diff] [blame]	27	config SPL_WATCHDOG_SUPPORT
				28	default y
				29
Dalon Westergreen	8d770f4	2017-02-10 17:15:34 -0800	[diff] [blame]	30	config SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
				31	default y
				32
				33	config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE
				34	default 0xa2
				35
Marek Vasut	822e795	2015-08-02 21:57:57 +0200	[diff] [blame]	36	config TARGET_SOCFPGA_ARRIA5
				37	bool
Dinh Nguyen	677a16f	2015-12-02 13:31:25 -0600	[diff] [blame]	38	select TARGET_SOCFPGA_GEN5
Marek Vasut	822e795	2015-08-02 21:57:57 +0200	[diff] [blame]	39
				40	config TARGET_SOCFPGA_CYCLONE5
				41	bool
Dinh Nguyen	677a16f	2015-12-02 13:31:25 -0600	[diff] [blame]	42	select TARGET_SOCFPGA_GEN5
				43
				44	config TARGET_SOCFPGA_GEN5
				45	bool
Ley Foon Tan	016539e	2017-04-05 17:32:51 +0800	[diff] [blame]	46	select ALTERA_SDRAM
Marek Vasut	822e795	2015-08-02 21:57:57 +0200	[diff] [blame]	47
Masahiro Yamada	144a3e0	2015-04-21 20:38:20 +0900	[diff] [blame]	48	choice
				49	prompt "Altera SOCFPGA board select"
Joe Hershberger	f069960	2015-05-12 14:46:23 -0500	[diff] [blame]	50	optional
Masahiro Yamada	144a3e0	2015-04-21 20:38:20 +0900	[diff] [blame]	51
Marek Vasut	822e795	2015-08-02 21:57:57 +0200	[diff] [blame]	52	config TARGET_SOCFPGA_ARRIA5_SOCDK
				53	bool "Altera SOCFPGA SoCDK (Arria V)"
				54	select TARGET_SOCFPGA_ARRIA5
Masahiro Yamada	144a3e0	2015-04-21 20:38:20 +0900	[diff] [blame]	55
Marek Vasut	822e795	2015-08-02 21:57:57 +0200	[diff] [blame]	56	config TARGET_SOCFPGA_CYCLONE5_SOCDK
				57	bool "Altera SOCFPGA SoCDK (Cyclone V)"
				58	select TARGET_SOCFPGA_CYCLONE5
Masahiro Yamada	144a3e0	2015-04-21 20:38:20 +0900	[diff] [blame]	59
Marek Vasut	9d6c56b	2017-04-05 13:17:03 +0200	[diff] [blame]	60	config TARGET_SOCFPGA_ARIES_MCVEVK
				61	bool "Aries MCVEVK (Cyclone V)"
Marek Vasut	8e8b62a	2015-08-03 01:37:28 +0200	[diff] [blame]	62	select TARGET_SOCFPGA_CYCLONE5
				63
Marek Vasut	567356a	2015-11-23 17:06:27 +0100	[diff] [blame]	64	config TARGET_SOCFPGA_EBV_SOCRATES
				65	bool "EBV SoCrates (Cyclone V)"
				66	select TARGET_SOCFPGA_CYCLONE5
				67
Pavel Machek	9802e87	2016-06-07 12:37:23 +0200	[diff] [blame]	68	config TARGET_SOCFPGA_IS1
				69	bool "IS1 (Cyclone V)"
				70	select TARGET_SOCFPGA_CYCLONE5
				71
Marek Vasut	ba2ade9	2015-12-01 18:09:52 +0100	[diff] [blame]	72	config TARGET_SOCFPGA_SAMTEC_VINING_FPGA
				73	bool "samtec VIN\|ING FPGA (Cyclone V)"
Tom Rini	22d567e	2017-01-22 19:43:11 -0500	[diff] [blame]	74	select BOARD_LATE_INIT
Marek Vasut	ba2ade9	2015-12-01 18:09:52 +0100	[diff] [blame]	75	select TARGET_SOCFPGA_CYCLONE5
				76
Marek Vasut	2e717ec	2016-06-08 02:57:05 +0200	[diff] [blame]	77	config TARGET_SOCFPGA_SR1500
				78	bool "SR1500 (Cyclone V)"
				79	select TARGET_SOCFPGA_CYCLONE5
				80
Dinh Nguyen	c3364da	2015-09-01 17:41:52 -0500	[diff] [blame]	81	config TARGET_SOCFPGA_TERASIC_DE0_NANO
				82	bool "Terasic DE0-Nano-Atlas (Cyclone V)"
				83	select TARGET_SOCFPGA_CYCLONE5
				84
Dalon Westergreen	7a0fe0d	2017-04-18 08:11:16 -0700	[diff] [blame]	85	config TARGET_SOCFPGA_TERASIC_DE10_NANO
				86	bool "Terasic DE10-Nano (Cyclone V)"
				87	select TARGET_SOCFPGA_CYCLONE5
				88
Anatolij Gustschin	705bf37	2016-11-14 16:07:10 +0100	[diff] [blame]	89	config TARGET_SOCFPGA_TERASIC_DE1_SOC
				90	bool "Terasic DE1-SoC (Cyclone V)"
				91	select TARGET_SOCFPGA_CYCLONE5
				92
Marek Vasut	b415bad	2015-06-21 17:28:53 +0200	[diff] [blame]	93	config TARGET_SOCFPGA_TERASIC_SOCKIT
				94	bool "Terasic SoCkit (Cyclone V)"
				95	select TARGET_SOCFPGA_CYCLONE5
				96
Masahiro Yamada	144a3e0	2015-04-21 20:38:20 +0900	[diff] [blame]	97	endchoice
				98
				99	config SYS_BOARD
Marek Vasut	3f4c561	2015-08-10 21:24:53 +0200	[diff] [blame]	100	default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
				101	default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
Dinh Nguyen	c3364da	2015-09-01 17:41:52 -0500	[diff] [blame]	102	default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
Anatolij Gustschin	705bf37	2016-11-14 16:07:10 +0100	[diff] [blame]	103	default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
Dalon Westergreen	7a0fe0d	2017-04-18 08:11:16 -0700	[diff] [blame]	104	default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
Pavel Machek	9802e87	2016-06-07 12:37:23 +0200	[diff] [blame]	105	default "is1" if TARGET_SOCFPGA_IS1
Marek Vasut	9d6c56b	2017-04-05 13:17:03 +0200	[diff] [blame]	106	default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
Marek Vasut	b415bad	2015-06-21 17:28:53 +0200	[diff] [blame]	107	default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
Marek Vasut	567356a	2015-11-23 17:06:27 +0100	[diff] [blame]	108	default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
Stefan Roese	bf5ed2e	2015-11-18 11:06:09 +0100	[diff] [blame]	109	default "sr1500" if TARGET_SOCFPGA_SR1500
Marek Vasut	ba2ade9	2015-12-01 18:09:52 +0100	[diff] [blame]	110	default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
Masahiro Yamada	144a3e0	2015-04-21 20:38:20 +0900	[diff] [blame]	111
				112	config SYS_VENDOR
Marek Vasut	822e795	2015-08-02 21:57:57 +0200	[diff] [blame]	113	default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
				114	default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
Marek Vasut	9d6c56b	2017-04-05 13:17:03 +0200	[diff] [blame]	115	default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK
Marek Vasut	567356a	2015-11-23 17:06:27 +0100	[diff] [blame]	116	default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
Marek Vasut	ba2ade9	2015-12-01 18:09:52 +0100	[diff] [blame]	117	default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
Dinh Nguyen	c3364da	2015-09-01 17:41:52 -0500	[diff] [blame]	118	default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
Anatolij Gustschin	705bf37	2016-11-14 16:07:10 +0100	[diff] [blame]	119	default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC
Dalon Westergreen	7a0fe0d	2017-04-18 08:11:16 -0700	[diff] [blame]	120	default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO
Marek Vasut	b415bad	2015-06-21 17:28:53 +0200	[diff] [blame]	121	default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
Masahiro Yamada	144a3e0	2015-04-21 20:38:20 +0900	[diff] [blame]	122
				123	config SYS_SOC
				124	default "socfpga"
				125
				126	config SYS_CONFIG_NAME
Dinh Nguyen	16f6ffd	2015-09-22 17:01:32 -0500	[diff] [blame]	127	default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
				128	default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
Dinh Nguyen	c3364da	2015-09-01 17:41:52 -0500	[diff] [blame]	129	default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
Anatolij Gustschin	705bf37	2016-11-14 16:07:10 +0100	[diff] [blame]	130	default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
Dalon Westergreen	7a0fe0d	2017-04-18 08:11:16 -0700	[diff] [blame]	131	default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
Pavel Machek	9802e87	2016-06-07 12:37:23 +0200	[diff] [blame]	132	default "socfpga_is1" if TARGET_SOCFPGA_IS1
Marek Vasut	9d6c56b	2017-04-05 13:17:03 +0200	[diff] [blame]	133	default "socfpga_mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
Marek Vasut	b415bad	2015-06-21 17:28:53 +0200	[diff] [blame]	134	default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
Marek Vasut	567356a	2015-11-23 17:06:27 +0100	[diff] [blame]	135	default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
Stefan Roese	bf5ed2e	2015-11-18 11:06:09 +0100	[diff] [blame]	136	default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
Marek Vasut	ba2ade9	2015-12-01 18:09:52 +0100	[diff] [blame]	137	default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
Masahiro Yamada	144a3e0	2015-04-21 20:38:20 +0900	[diff] [blame]	138
				139	endif