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Simon Glass4cc43bf2021-08-18 21:40:25 -06001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Devicetree file for running sandbox tests
4 *
5 * This includes lots of extra devices used by various tests.
6 *
7 * Note that SPL use the main sandbox.dts file
8 */
9
Simon Glassb2c1cac2014-02-26 15:59:21 -070010/dts-v1/;
11
Patrick Delaunay23aee612020-01-13 11:35:13 +010012#include <dt-bindings/gpio/gpio.h>
13#include <dt-bindings/gpio/sandbox-gpio.h>
Marek Szyprowskiad398592021-02-18 11:33:18 +010014#include <dt-bindings/input/input.h>
Sean Anderson3438e3b2020-09-14 11:01:57 -040015#include <dt-bindings/pinctrl/sandbox-pinmux.h>
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +053016#include <dt-bindings/mux/mux.h>
Patrick Delaunay23aee612020-01-13 11:35:13 +010017
Simon Glassb2c1cac2014-02-26 15:59:21 -070018/ {
19 model = "sandbox";
20 compatible = "sandbox";
21 #address-cells = <1>;
Simon Glasscf61f742015-07-06 12:54:36 -060022 #size-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -070023
Simon Glassfef72b72014-07-23 06:55:03 -060024 aliases {
25 console = &uart0;
Michael Walle7efcdfd2021-02-25 16:51:11 +010026 ethernet0 = "/eth@10002000";
27 ethernet2 = &swp_0;
28 ethernet3 = &eth_3;
29 ethernet4 = &dsa_eth0;
30 ethernet5 = &eth_5;
Sean Anderson67d93a42022-05-05 13:11:30 -040031 ethernet6 = "/eth@10004000";
32 ethernet7 = &swp_1;
33 ethernet8 = &phy_eth0;
Simon Glass5620cf82018-10-01 12:22:40 -060034 gpio1 = &gpio_a;
35 gpio2 = &gpio_b;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +010036 gpio3 = &gpio_c;
Simon Glass0ccb0972015-01-25 08:27:05 -070037 i2c0 = "/i2c@0";
Simon Glasse4fef742017-04-23 20:02:07 -060038 mmc0 = "/mmc0";
39 mmc1 = "/mmc1";
Bin Meng408e5902018-08-03 01:14:41 -070040 pci0 = &pci0;
41 pci1 = &pci1;
Bin Meng510dddb2018-08-03 01:14:50 -070042 pci2 = &pci2;
Michael Walle7c41a222020-06-02 01:47:09 +020043 remoteproc0 = &rproc_1;
44 remoteproc1 = &rproc_2;
Simon Glass336b2952015-05-22 15:42:17 -060045 rtc0 = &rtc_0;
46 rtc1 = &rtc_1;
Simon Glass5b968632015-05-22 15:42:15 -060047 spi0 = "/spi@0";
Przemyslaw Marczak3dbb55e2015-05-13 13:38:34 +020048 testfdt6 = "/e-test";
Simon Glass0ccb0972015-01-25 08:27:05 -070049 testbus3 = "/some-bus";
50 testfdt0 = "/some-bus/c-test@0";
Simon Glass7d5e4112020-12-16 21:20:26 -070051 testfdt12 = "/some-bus/c-test@1";
Simon Glass0ccb0972015-01-25 08:27:05 -070052 testfdt3 = "/b-test";
53 testfdt5 = "/some-bus/c-test@5";
54 testfdt8 = "/a-test";
Simon Glass791a17f2020-12-16 21:20:27 -070055 testfdtm1 = &testfdtm1;
Eugeniu Rosca5ba71e52018-05-19 14:13:55 +020056 fdt-dummy0 = "/translation-test@8000/dev@0,0";
57 fdt-dummy1 = "/translation-test@8000/dev@1,100";
58 fdt-dummy2 = "/translation-test@8000/dev@2,200";
59 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glass31680482015-03-25 12:23:05 -060060 usb0 = &usb_0;
61 usb1 = &usb_1;
62 usb2 = &usb_2;
Mario Six95922152018-08-09 14:51:19 +020063 axi0 = &axi;
Mario Six02ad6fb2018-09-27 09:19:31 +020064 osd0 = "/osd";
Simon Glassfef72b72014-07-23 06:55:03 -060065 };
66
Philippe Reynes462d1632022-03-28 22:56:53 +020067 binman {
68 };
69
Rasmus Villemoes30d4d2b2021-04-21 11:06:55 +020070 config {
Simon Glass0034d962021-08-07 07:24:01 -060071 testing-bool;
72 testing-int = <123>;
73 testing-str = "testing";
Rasmus Villemoes30d4d2b2021-04-21 11:06:55 +020074 environment {
75 from_fdt = "yes";
76 fdt_env_path = "";
77 };
78 };
79
Simon Glassb255efc2022-04-24 23:31:24 -060080 bootstd {
81 compatible = "u-boot,boot-std";
82
83 filename-prefixes = "/", "/boot/";
84 bootdev-order = "mmc2", "mmc1";
85
86 syslinux {
87 compatible = "u-boot,distro-syslinux";
88 };
89
90 efi {
91 compatible = "u-boot,distro-efi";
92 };
93 };
94
Andrew Scull451b8b12022-05-30 10:00:12 +000095 fuzzing-engine {
96 compatible = "sandbox,fuzzing-engine";
97 };
98
Nandor Han6521e5d2021-06-10 16:56:44 +030099 reboot-mode0 {
100 compatible = "reboot-mode-gpio";
101 gpios = <&gpio_c 0 GPIO_ACTIVE_HIGH>, <&gpio_c 1 GPIO_ACTIVE_HIGH>;
102 u-boot,env-variable = "bootstatus";
103 mode-test = <0x01>;
104 mode-download = <0x03>;
105 };
106
Nandor Han7e4067a2021-06-10 16:56:45 +0300107 reboot_mode1: reboot-mode@14 {
108 compatible = "reboot-mode-rtc";
109 rtc = <&rtc_0>;
110 reg = <0x30 4>;
111 u-boot,env-variable = "bootstatus";
112 big-endian;
113 mode-test = <0x21969147>;
114 mode-download = <0x51939147>;
115 };
116
Simon Glassed96cde2018-12-10 10:37:33 -0700117 audio: audio-codec {
118 compatible = "sandbox,audio-codec";
119 #sound-dai-cells = <1>;
120 };
121
Philippe Reynes1ee26482020-07-24 18:19:51 +0200122 buttons {
123 compatible = "gpio-keys";
124
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200125 btn1 {
Philippe Reynes1ee26482020-07-24 18:19:51 +0200126 gpios = <&gpio_a 3 0>;
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200127 label = "button1";
Philippe Reynes1ee26482020-07-24 18:19:51 +0200128 };
129
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200130 btn2 {
Philippe Reynes1ee26482020-07-24 18:19:51 +0200131 gpios = <&gpio_a 4 0>;
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200132 label = "button2";
Philippe Reynes1ee26482020-07-24 18:19:51 +0200133 };
134 };
135
Marek Szyprowskiad398592021-02-18 11:33:18 +0100136 buttons2 {
137 compatible = "adc-keys";
138 io-channels = <&adc 3>;
139 keyup-threshold-microvolt = <3000000>;
140
141 button-up {
142 label = "button3";
143 linux,code = <KEY_F3>;
144 press-threshold-microvolt = <1500000>;
145 };
146
147 button-down {
148 label = "button4";
149 linux,code = <KEY_F4>;
150 press-threshold-microvolt = <1000000>;
151 };
152
153 button-enter {
154 label = "button5";
155 linux,code = <KEY_F5>;
156 press-threshold-microvolt = <500000>;
157 };
158 };
159
Simon Glassc953aaf2018-12-10 10:37:34 -0700160 cros_ec: cros-ec {
Simon Glass699c9ca2018-10-01 12:22:08 -0600161 reg = <0 0>;
162 compatible = "google,cros-ec-sandbox";
163
164 /*
165 * This describes the flash memory within the EC. Note
166 * that the STM32L flash erases to 0, not 0xff.
167 */
168 flash {
169 image-pos = <0x08000000>;
170 size = <0x20000>;
171 erase-value = <0>;
172
173 /* Information for sandbox */
174 ro {
175 image-pos = <0>;
176 size = <0xf000>;
177 };
178 wp-ro {
179 image-pos = <0xf000>;
180 size = <0x1000>;
Simon Glassbf0a6922021-01-21 13:57:14 -0700181 used = <0x884>;
182 compress = "lz4";
183 uncomp-size = <0xcf8>;
184 hash {
185 algo = "sha256";
186 value = [00 01 02 03 04 05 06 07
187 08 09 0a 0b 0c 0d 0e 0f
188 10 11 12 13 14 15 16 17
189 18 19 1a 1b 1c 1d 1e 1f];
190 };
Simon Glass699c9ca2018-10-01 12:22:08 -0600191 };
192 rw {
193 image-pos = <0x10000>;
194 size = <0x10000>;
195 };
196 };
Alper Nebi Yasak8a8cd4f2021-05-19 19:33:31 +0300197
198 cros_ec_pwm: cros-ec-pwm {
199 compatible = "google,cros-ec-pwm";
200 #pwm-cells = <1>;
201 };
202
Simon Glass699c9ca2018-10-01 12:22:08 -0600203 };
204
Yannick Fertré9712c822019-10-07 15:29:05 +0200205 dsi_host: dsi_host {
206 compatible = "sandbox,dsi-host";
207 };
208
Simon Glassb2c1cac2014-02-26 15:59:21 -0700209 a-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600210 reg = <0 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700211 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600212 ping-expect = <0>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700213 ping-add = <0>;
Simon Glassfef72b72014-07-23 06:55:03 -0600214 u-boot,dm-pre-reloc;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100215 test-gpios = <&gpio_a 1>, <&gpio_a 4>,
216 <&gpio_b 5 GPIO_ACTIVE_HIGH 3 2 1>,
Simon Glass16e10402015-01-05 20:05:29 -0700217 <0>, <&gpio_a 12>;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100218 test2-gpios = <&gpio_a 1>, <&gpio_a 4>,
219 <&gpio_b 6 GPIO_ACTIVE_LOW 3 2 1>,
220 <&gpio_b 7 GPIO_IN 3 2 1>,
221 <&gpio_b 8 GPIO_OUT 3 2 1>,
222 <&gpio_b 9 (GPIO_OUT|GPIO_OUT_ACTIVE) 3 2 1>;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100223 test3-gpios =
224 <&gpio_c 0 (GPIO_OUT|GPIO_OPEN_DRAIN)>,
225 <&gpio_c 1 (GPIO_OUT|GPIO_OPEN_SOURCE)>,
226 <&gpio_c 2 GPIO_OUT>,
227 <&gpio_c 3 (GPIO_IN|GPIO_PULL_UP)>,
228 <&gpio_c 4 (GPIO_IN|GPIO_PULL_DOWN)>,
Neil Armstrong643778b2020-05-05 10:43:18 +0200229 <&gpio_c 5 GPIO_IN>,
230 <&gpio_c 6 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_DRAIN)>,
231 <&gpio_c 7 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_SOURCE)>;
Jean-Jacques Hiblot73873402020-09-11 13:43:35 +0530232 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
233 test5-gpios = <&gpio_a 19>;
234
Simon Glass73025392021-10-23 17:26:04 -0600235 bool-value;
Stefan Herbrechtsmeier1b090e62022-06-14 15:21:30 +0200236 int8-value = /bits/ 8 <0x12>;
237 int16-value = /bits/ 16 <0x1234>;
Simon Glass6df01f92018-12-10 10:37:37 -0700238 int-value = <1234>;
239 uint-value = <(-1234)>;
Dario Binacchi421e81e2020-03-29 18:04:40 +0200240 int64-value = /bits/ 64 <0x1111222233334444>;
Dario Binacchi81d80b52020-03-29 18:04:41 +0200241 int-array = <5678 9123 4567>;
Simon Glassdd0ed902020-07-07 13:11:58 -0600242 str-value = "test string";
Simon Glass515dcff2020-02-06 09:55:00 -0700243 interrupts-extended = <&irq 3 0>;
Simon Glass09642392020-07-07 13:12:11 -0600244 acpi,name = "GHIJ";
Patrick Delaunay8cd28012020-09-25 09:41:16 +0200245 phandle-value = <&gpio_c 10>, <0xFFFFFFFF 20>, <&gpio_a 30>;
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530246
247 mux-controls = <&muxcontroller0 0>, <&muxcontroller0 1>,
248 <&muxcontroller0 2>, <&muxcontroller0 3>,
249 <&muxcontroller1>;
250 mux-control-names = "mux0", "mux1", "mux2", "mux3", "mux4";
251 mux-syscon = <&syscon3>;
Dario Binacchi836cc9d2020-12-30 00:16:26 +0100252 display-timings {
253 timing0: 240x320 {
254 clock-frequency = <6500000>;
255 hactive = <240>;
256 vactive = <320>;
257 hfront-porch = <6>;
258 hback-porch = <7>;
259 hsync-len = <1>;
260 vback-porch = <5>;
261 vfront-porch = <8>;
262 vsync-len = <2>;
263 hsync-active = <1>;
264 vsync-active = <0>;
265 de-active = <1>;
266 pixelclk-active = <1>;
267 interlaced;
268 doublescan;
269 doubleclk;
270 };
271 timing1: 480x800 {
272 clock-frequency = <9000000>;
273 hactive = <480>;
274 vactive = <800>;
275 hfront-porch = <10>;
276 hback-porch = <59>;
277 hsync-len = <12>;
278 vback-porch = <15>;
279 vfront-porch = <17>;
280 vsync-len = <16>;
281 hsync-active = <0>;
282 vsync-active = <1>;
283 de-active = <0>;
284 pixelclk-active = <0>;
285 };
286 timing2: 800x480 {
287 clock-frequency = <33500000>;
288 hactive = <800>;
289 vactive = <480>;
290 hback-porch = <89>;
291 hfront-porch = <164>;
292 vback-porch = <23>;
293 vfront-porch = <10>;
294 hsync-len = <11>;
295 vsync-len = <13>;
296 };
297 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700298 };
299
300 junk {
Simon Glasscf61f742015-07-06 12:54:36 -0600301 reg = <1 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700302 compatible = "not,compatible";
303 };
304
305 no-compatible {
Simon Glasscf61f742015-07-06 12:54:36 -0600306 reg = <2 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700307 };
308
Simon Glass5620cf82018-10-01 12:22:40 -0600309 backlight: backlight {
310 compatible = "pwm-backlight";
311 enable-gpios = <&gpio_a 1>;
312 power-supply = <&ldo_1>;
313 pwms = <&pwm 0 1000>;
314 default-brightness-level = <5>;
315 brightness-levels = <0 16 32 64 128 170 202 234 255>;
316 };
317
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200318 bind-test {
Patrice Chotard7b7f9392020-07-28 09:13:33 +0200319 compatible = "simple-bus";
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200320 bind-test-child1 {
321 compatible = "sandbox,phy";
322 #phy-cells = <1>;
323 };
324
325 bind-test-child2 {
326 compatible = "simple-bus";
327 };
328 };
329
Simon Glassb2c1cac2014-02-26 15:59:21 -0700330 b-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600331 reg = <3 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700332 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600333 ping-expect = <3>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700334 ping-add = <3>;
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530335
336 mux-controls = <&muxcontroller0 0>;
337 mux-control-names = "mux0";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700338 };
339
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200340 phy_provider0: gen_phy@0 {
341 compatible = "sandbox,phy";
342 #phy-cells = <1>;
343 };
344
345 phy_provider1: gen_phy@1 {
346 compatible = "sandbox,phy";
347 #phy-cells = <0>;
348 broken;
349 };
350
developer71092972020-05-02 11:35:12 +0200351 phy_provider2: gen_phy@2 {
352 compatible = "sandbox,phy";
353 #phy-cells = <0>;
354 };
355
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200356 gen_phy_user: gen_phy_user {
357 compatible = "simple-bus";
358 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
359 phy-names = "phy1", "phy2", "phy3";
360 };
361
developer71092972020-05-02 11:35:12 +0200362 gen_phy_user1: gen_phy_user1 {
363 compatible = "simple-bus";
364 phys = <&phy_provider0 0>, <&phy_provider2>;
365 phy-names = "phy1", "phy2";
366 };
367
Simon Glassb2c1cac2014-02-26 15:59:21 -0700368 some-bus {
369 #address-cells = <1>;
370 #size-cells = <0>;
Simon Glass40717422014-07-23 06:55:18 -0600371 compatible = "denx,u-boot-test-bus";
Simon Glasscf61f742015-07-06 12:54:36 -0600372 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600373 ping-expect = <4>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700374 ping-add = <4>;
Simon Glass40717422014-07-23 06:55:18 -0600375 c-test@5 {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700376 compatible = "denx,u-boot-fdt-test";
377 reg = <5>;
Simon Glass40717422014-07-23 06:55:18 -0600378 ping-expect = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700379 ping-add = <5>;
380 };
Simon Glass40717422014-07-23 06:55:18 -0600381 c-test@0 {
382 compatible = "denx,u-boot-fdt-test";
383 reg = <0>;
384 ping-expect = <6>;
385 ping-add = <6>;
386 };
387 c-test@1 {
388 compatible = "denx,u-boot-fdt-test";
389 reg = <1>;
390 ping-expect = <7>;
391 ping-add = <7>;
392 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700393 };
394
395 d-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600396 reg = <3 1>;
Simon Glassdb6f0202014-07-23 06:55:12 -0600397 ping-expect = <6>;
398 ping-add = <6>;
399 compatible = "google,another-fdt-test";
400 };
401
402 e-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600403 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600404 ping-expect = <6>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700405 ping-add = <6>;
406 compatible = "google,another-fdt-test";
407 };
408
Simon Glass0ccb0972015-01-25 08:27:05 -0700409 f-test {
410 compatible = "denx,u-boot-fdt-test";
411 };
412
413 g-test {
414 compatible = "denx,u-boot-fdt-test";
415 };
416
Bin Mengd9d24782018-10-10 22:07:01 -0700417 h-test {
418 compatible = "denx,u-boot-fdt-test1";
419 };
420
developercf8bc132020-05-02 11:35:10 +0200421 i-test {
422 compatible = "mediatek,u-boot-fdt-test";
423 #address-cells = <1>;
424 #size-cells = <0>;
425
426 subnode@0 {
427 reg = <0>;
428 };
429
430 subnode@1 {
431 reg = <1>;
432 };
433
434 subnode@2 {
435 reg = <2>;
436 };
437 };
438
Simon Glass204675c2019-12-29 21:19:25 -0700439 devres-test {
440 compatible = "denx,u-boot-devres-test";
441 };
442
Jean-Jacques Hiblot73873402020-09-11 13:43:35 +0530443 another-test {
444 reg = <0 2>;
445 compatible = "denx,u-boot-fdt-test";
446 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
447 test5-gpios = <&gpio_a 19>;
448 };
449
Nicolas Saenz Julienne22b7f7e2021-01-12 13:55:23 +0100450 mmio-bus@0 {
451 #address-cells = <1>;
452 #size-cells = <1>;
453 compatible = "denx,u-boot-test-bus";
454 dma-ranges = <0x10000000 0x00000000 0x00040000>;
455
456 subnode@0 {
457 compatible = "denx,u-boot-fdt-test";
458 };
459 };
460
461 mmio-bus@1 {
462 #address-cells = <1>;
463 #size-cells = <1>;
464 compatible = "denx,u-boot-test-bus";
Nicolas Saenz Julienne892e9b42021-01-12 13:55:25 +0100465
466 subnode@0 {
467 compatible = "denx,u-boot-fdt-test";
468 };
Nicolas Saenz Julienne22b7f7e2021-01-12 13:55:23 +0100469 };
470
Simon Glass3c601b12020-07-07 13:12:06 -0600471 acpi_test1: acpi-test {
Simon Glass2d67fdf2020-04-08 16:57:34 -0600472 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600473 acpi-ssdt-test-data = "ab";
Simon Glass990cd5b2020-07-07 13:12:08 -0600474 acpi-dsdt-test-data = "hi";
Simon Glassebb2e832020-07-07 13:11:39 -0600475 child {
476 compatible = "denx,u-boot-acpi-test";
477 };
Simon Glass2d67fdf2020-04-08 16:57:34 -0600478 };
479
Simon Glass3c601b12020-07-07 13:12:06 -0600480 acpi_test2: acpi-test2 {
Simon Glass17968c32020-04-26 09:19:46 -0600481 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600482 acpi-ssdt-test-data = "cd";
Simon Glass990cd5b2020-07-07 13:12:08 -0600483 acpi-dsdt-test-data = "jk";
Simon Glass17968c32020-04-26 09:19:46 -0600484 };
485
Patrice Chotard9cc2d142017-09-04 14:55:57 +0200486 clocks {
487 clk_fixed: clk-fixed {
488 compatible = "fixed-clock";
489 #clock-cells = <0>;
490 clock-frequency = <1234>;
491 };
Anup Patel8d28c3c2019-02-25 08:14:55 +0000492
493 clk_fixed_factor: clk-fixed-factor {
494 compatible = "fixed-factor-clock";
495 #clock-cells = <0>;
496 clock-div = <3>;
497 clock-mult = <2>;
498 clocks = <&clk_fixed>;
499 };
Lukasz Majewskiccafcdd2019-06-24 15:50:47 +0200500
501 osc {
502 compatible = "fixed-clock";
503 #clock-cells = <0>;
504 clock-frequency = <20000000>;
505 };
Stephen Warrena9622432016-06-17 09:44:00 -0600506 };
507
508 clk_sandbox: clk-sbox {
Simon Glass8cc4d822015-07-06 12:54:24 -0600509 compatible = "sandbox,clk";
Stephen Warrena9622432016-06-17 09:44:00 -0600510 #clock-cells = <1>;
Jean-Jacques Hiblotc1e9c942019-10-22 14:00:07 +0200511 assigned-clocks = <&clk_sandbox 3>;
512 assigned-clock-rates = <321>;
Stephen Warrena9622432016-06-17 09:44:00 -0600513 };
514
515 clk-test {
516 compatible = "sandbox,clk-test";
517 clocks = <&clk_fixed>,
518 <&clk_sandbox 1>,
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200519 <&clk_sandbox 0>,
520 <&clk_sandbox 3>,
521 <&clk_sandbox 2>;
522 clock-names = "fixed", "i2c", "spi", "uart2", "uart1";
Simon Glass8cc4d822015-07-06 12:54:24 -0600523 };
524
Lukasz Majewski8c0709b2019-06-24 15:50:50 +0200525 ccf: clk-ccf {
526 compatible = "sandbox,clk-ccf";
527 };
528
Simon Glass507ab962021-12-04 08:56:31 -0700529 efi-media {
530 compatible = "sandbox,efi-media";
531 };
532
Simon Glass5b968632015-05-22 15:42:15 -0600533 eth@10002000 {
534 compatible = "sandbox,eth";
535 reg = <0x10002000 0x1000>;
Simon Glass5b968632015-05-22 15:42:15 -0600536 };
537
538 eth_5: eth@10003000 {
539 compatible = "sandbox,eth";
540 reg = <0x10003000 0x1000>;
Sean Anderson13652b82022-05-05 13:11:44 -0400541 nvmem-cells = <&eth5_addr>;
542 nvmem-cell-names = "mac-address";
Simon Glass5b968632015-05-22 15:42:15 -0600543 };
544
Bin Meng04a11cb2015-08-27 22:25:53 -0700545 eth_3: sbe5 {
546 compatible = "sandbox,eth";
547 reg = <0x10005000 0x1000>;
Sean Andersone2dc0e62022-05-05 13:11:42 -0400548 nvmem-cells = <&eth3_addr>;
549 nvmem-cell-names = "mac-address";
Bin Meng04a11cb2015-08-27 22:25:53 -0700550 };
551
Simon Glass5b968632015-05-22 15:42:15 -0600552 eth@10004000 {
553 compatible = "sandbox,eth";
554 reg = <0x10004000 0x1000>;
Simon Glass5b968632015-05-22 15:42:15 -0600555 };
556
Marek BehĂșnf4f1ddc2022-04-07 00:32:57 +0200557 phy_eth0: phy-test-eth {
558 compatible = "sandbox,eth";
559 reg = <0x10007000 0x1000>;
Sean Anderson24b1b8d2022-05-05 13:11:35 -0400560 mac-address = [ 02 00 11 22 33 49 ];
Marek BehĂșnf4f1ddc2022-04-07 00:32:57 +0200561 phy-handle = <&ethphy1>;
Marek BehĂșnbc194772022-04-07 00:33:01 +0200562 phy-mode = "2500base-x";
Marek BehĂșnf4f1ddc2022-04-07 00:32:57 +0200563 };
564
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800565 dsa_eth0: dsa-test-eth {
566 compatible = "sandbox,eth";
567 reg = <0x10006000 0x1000>;
Sean Anderson5768e8b2022-05-05 13:11:43 -0400568 nvmem-cells = <&eth4_addr>;
569 nvmem-cell-names = "mac-address";
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800570 };
571
572 dsa-test {
573 compatible = "sandbox,dsa";
574
575 ports {
576 #address-cells = <1>;
577 #size-cells = <0>;
578 swp_0: port@0 {
579 reg = <0>;
580 label = "lan0";
581 phy-mode = "rgmii-rxid";
582
583 fixed-link {
584 speed = <100>;
585 full-duplex;
586 };
587 };
588
589 swp_1: port@1 {
590 reg = <1>;
591 label = "lan1";
592 phy-mode = "rgmii-txid";
Bin Meng381ed972021-03-14 20:14:58 +0800593 fixed-link = <0 1 100 0 0>;
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800594 };
595
596 port@2 {
597 reg = <2>;
598 ethernet = <&dsa_eth0>;
599
600 fixed-link {
601 speed = <1000>;
602 full-duplex;
603 };
604 };
605 };
606 };
607
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700608 firmware {
609 sandbox_firmware: sandbox-firmware {
610 compatible = "sandbox,firmware";
611 };
Etienne Carriere02fd1262020-09-09 18:44:00 +0200612
Etienne Carriere09665cb2022-02-21 09:22:39 +0100613 scmi {
Etienne Carriere02fd1262020-09-09 18:44:00 +0200614 compatible = "sandbox,scmi-agent";
615 #address-cells = <1>;
616 #size-cells = <0>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200617
Etienne Carriere09665cb2022-02-21 09:22:39 +0100618 protocol@10 {
619 reg = <0x10>;
620 };
621
622 clk_scmi: protocol@14 {
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200623 reg = <0x14>;
624 #clock-cells = <1>;
625 };
Etienne Carriere8b9b6892020-09-09 18:44:07 +0200626
Etienne Carriere09665cb2022-02-21 09:22:39 +0100627 reset_scmi: protocol@16 {
Etienne Carriere8b9b6892020-09-09 18:44:07 +0200628 reg = <0x16>;
629 #reset-cells = <1>;
630 };
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100631
632 protocol@17 {
633 reg = <0x17>;
634
635 regulators {
636 #address-cells = <1>;
637 #size-cells = <0>;
638
Etienne Carriere09665cb2022-02-21 09:22:39 +0100639 regul0_scmi: reg@0 {
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100640 reg = <0>;
641 regulator-name = "sandbox-voltd0";
642 regulator-min-microvolt = <1100000>;
643 regulator-max-microvolt = <3300000>;
644 };
Etienne Carriere09665cb2022-02-21 09:22:39 +0100645 regul1_scmi: reg@1 {
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100646 reg = <0x1>;
647 regulator-name = "sandbox-voltd1";
648 regulator-min-microvolt = <1800000>;
649 };
650 };
651 };
Etienne Carriere02fd1262020-09-09 18:44:00 +0200652 };
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700653 };
654
Alexander Dahl6ac319d2022-09-30 14:04:30 +0200655 fpga {
656 compatible = "sandbox,fpga";
657 };
658
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100659 pinctrl-gpio {
660 compatible = "sandbox,pinctrl-gpio";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700661
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100662 gpio_a: base-gpios {
663 compatible = "sandbox,gpio";
664 gpio-controller;
665 #gpio-cells = <1>;
666 gpio-bank-name = "a";
667 sandbox,gpio-count = <20>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200668 hog_input_active_low {
669 gpio-hog;
670 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200671 gpios = <10 GPIO_ACTIVE_LOW>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200672 };
673 hog_input_active_high {
674 gpio-hog;
675 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200676 gpios = <11 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200677 };
678 hog_output_low {
679 gpio-hog;
680 output-low;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200681 gpios = <12 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200682 };
683 hog_output_high {
684 gpio-hog;
685 output-high;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200686 gpios = <13 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200687 };
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100688 };
689
690 gpio_b: extra-gpios {
691 compatible = "sandbox,gpio";
692 gpio-controller;
693 #gpio-cells = <5>;
694 gpio-bank-name = "b";
695 sandbox,gpio-count = <10>;
696 };
Simon Glass25348a42014-10-13 23:42:11 -0600697
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100698 gpio_c: pinmux-gpios {
699 compatible = "sandbox,gpio";
700 gpio-controller;
701 #gpio-cells = <2>;
702 gpio-bank-name = "c";
703 sandbox,gpio-count = <10>;
704 };
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100705 };
706
Simon Glass7df766e2014-12-10 08:55:55 -0700707 i2c@0 {
708 #address-cells = <1>;
709 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600710 reg = <0 1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700711 compatible = "sandbox,i2c";
712 clock-frequency = <100000>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +0200713 pinctrl-names = "default";
714 pinctrl-0 = <&pinmux_i2c0_pins>;
715
Simon Glass7df766e2014-12-10 08:55:55 -0700716 eeprom@2c {
Sean Andersone2dc0e62022-05-05 13:11:42 -0400717 #address-cells = <1>;
718 #size-cells = <1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700719 reg = <0x2c>;
720 compatible = "i2c-eeprom";
Simon Glass17b56f62018-11-18 08:14:34 -0700721 sandbox,emul = <&emul_eeprom>;
Michal Simek4f18f922020-05-28 11:48:55 +0200722 partitions {
723 compatible = "fixed-partitions";
724 #address-cells = <1>;
725 #size-cells = <1>;
726 bootcount_i2c: bootcount@10 {
727 reg = <10 2>;
728 };
729 };
Sean Andersone2dc0e62022-05-05 13:11:42 -0400730
731 eth3_addr: mac-address@24 {
732 reg = <24 6>;
733 };
Simon Glass7df766e2014-12-10 08:55:55 -0700734 };
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200735
Simon Glass336b2952015-05-22 15:42:17 -0600736 rtc_0: rtc@43 {
Sean Anderson5768e8b2022-05-05 13:11:43 -0400737 #address-cells = <1>;
738 #size-cells = <1>;
Simon Glass336b2952015-05-22 15:42:17 -0600739 reg = <0x43>;
740 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700741 sandbox,emul = <&emul0>;
Sean Anderson5768e8b2022-05-05 13:11:43 -0400742
743 eth4_addr: mac-address@40 {
744 reg = <0x40 6>;
745 };
Simon Glass336b2952015-05-22 15:42:17 -0600746 };
747
748 rtc_1: rtc@61 {
749 reg = <0x61>;
750 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700751 sandbox,emul = <&emul1>;
752 };
753
754 i2c_emul: emul {
755 reg = <0xff>;
756 compatible = "sandbox,i2c-emul-parent";
757 emul_eeprom: emul-eeprom {
758 compatible = "sandbox,i2c-eeprom";
759 sandbox,filename = "i2c.bin";
760 sandbox,size = <256>;
761 };
762 emul0: emul0 {
Simon Glass98af3742021-02-03 06:01:17 -0700763 compatible = "sandbox,i2c-rtc-emul";
Simon Glass17b56f62018-11-18 08:14:34 -0700764 };
765 emul1: emull {
Simon Glass98af3742021-02-03 06:01:17 -0700766 compatible = "sandbox,i2c-rtc-emul";
Simon Glass336b2952015-05-22 15:42:17 -0600767 };
768 };
769
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200770 sandbox_pmic: sandbox_pmic {
771 reg = <0x40>;
Simon Glass17b56f62018-11-18 08:14:34 -0700772 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200773 };
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200774
775 mc34708: pmic@41 {
776 reg = <0x41>;
Simon Glass17b56f62018-11-18 08:14:34 -0700777 sandbox,emul = <&emul_pmic1>;
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200778 };
Simon Glass7df766e2014-12-10 08:55:55 -0700779 };
780
Philipp Tomsich1fc53302018-12-14 21:14:29 +0100781 bootcount@0 {
782 compatible = "u-boot,bootcount-rtc";
783 rtc = <&rtc_1>;
784 offset = <0x13>;
785 };
786
Michal Simek4f18f922020-05-28 11:48:55 +0200787 bootcount {
788 compatible = "u-boot,bootcount-i2c-eeprom";
789 i2c-eeprom = <&bootcount_i2c>;
790 };
791
Nandor Han88895812021-06-10 15:40:38 +0300792 bootcount_4@0 {
793 compatible = "u-boot,bootcount-syscon";
794 syscon = <&syscon0>;
795 reg = <0x0 0x04>, <0x0 0x04>;
796 reg-names = "syscon_reg", "offset";
797 };
798
799 bootcount_2@0 {
800 compatible = "u-boot,bootcount-syscon";
801 syscon = <&syscon0>;
802 reg = <0x0 0x04>, <0x0 0x02> ;
803 reg-names = "syscon_reg", "offset";
804 };
805
Marek Szyprowskiad398592021-02-18 11:33:18 +0100806 adc: adc@0 {
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100807 compatible = "sandbox,adc";
Marek Szyprowskiad398592021-02-18 11:33:18 +0100808 #io-channel-cells = <1>;
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100809 vdd-supply = <&buck2>;
810 vss-microvolts = <0>;
811 };
812
Mark Kettenis67748ee2021-10-23 16:58:02 +0200813 iommu: iommu@0 {
814 compatible = "sandbox,iommu";
815 #iommu-cells = <0>;
816 };
817
Simon Glass515dcff2020-02-06 09:55:00 -0700818 irq: irq {
Simon Glass54028bc2019-12-06 21:41:59 -0700819 compatible = "sandbox,irq";
Simon Glass515dcff2020-02-06 09:55:00 -0700820 interrupt-controller;
821 #interrupt-cells = <2>;
Simon Glass54028bc2019-12-06 21:41:59 -0700822 };
823
Simon Glass90b6fef2016-01-18 19:52:26 -0700824 lcd {
825 u-boot,dm-pre-reloc;
826 compatible = "sandbox,lcd-sdl";
Dario Binacchi20dd9e12021-04-11 09:39:50 +0200827 pinctrl-names = "default";
828 pinctrl-0 = <&pinmux_lcd_pins>;
Simon Glass90b6fef2016-01-18 19:52:26 -0700829 xres = <1366>;
830 yres = <768>;
831 };
832
Simon Glassd783eb32015-07-06 12:54:34 -0600833 leds {
834 compatible = "gpio-leds";
835
836 iracibble {
837 gpios = <&gpio_a 1 0>;
838 label = "sandbox:red";
839 };
840
841 martinet {
842 gpios = <&gpio_a 2 0>;
843 label = "sandbox:green";
844 };
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200845
846 default_on {
847 gpios = <&gpio_a 5 0>;
848 label = "sandbox:default_on";
849 default-state = "on";
850 };
851
852 default_off {
853 gpios = <&gpio_a 6 0>;
Sean Andersonfbf8d652020-09-14 11:02:03 -0400854 /* label intentionally omitted */
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200855 default-state = "off";
856 };
Simon Glassd783eb32015-07-06 12:54:34 -0600857 };
858
Paul Doelle709f0372022-07-04 09:00:25 +0000859 wdt-gpio-toggle {
Rasmus Villemoes2b673872021-08-19 11:57:05 +0200860 gpios = <&gpio_a 7 0>;
861 compatible = "linux,wdt-gpio";
Rasmus Villemoesf91ff5a2021-08-19 11:57:06 +0200862 hw_margin_ms = <100>;
Paul Doelle709f0372022-07-04 09:00:25 +0000863 hw_algo = "toggle";
864 always-running;
865 };
866
867 wdt-gpio-level {
868 gpios = <&gpio_a 7 0>;
869 compatible = "linux,wdt-gpio";
870 hw_margin_ms = <100>;
871 hw_algo = "level";
Rasmus Villemoes2b673872021-08-19 11:57:05 +0200872 always-running;
873 };
874
Stephen Warren62f2c902016-05-16 17:41:37 -0600875 mbox: mbox {
876 compatible = "sandbox,mbox";
877 #mbox-cells = <1>;
878 };
879
880 mbox-test {
881 compatible = "sandbox,mbox-test";
882 mboxes = <&mbox 100>, <&mbox 1>;
883 mbox-names = "other", "test";
884 };
885
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900886 cpus {
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +0200887 #address-cells = <1>;
888 #size-cells = <0>;
Sean Anderson79d3bba2020-09-28 10:52:23 -0400889 timebase-frequency = <2000000>;
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +0200890 cpu1: cpu@1 {
891 device_type = "cpu";
892 reg = <0x1>;
Sean Anderson79d3bba2020-09-28 10:52:23 -0400893 timebase-frequency = <3000000>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900894 compatible = "sandbox,cpu_sandbox";
895 u-boot,dm-pre-reloc;
896 };
Mario Sixdea5df72018-08-06 10:23:44 +0200897
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +0200898 cpu2: cpu@2 {
899 device_type = "cpu";
900 reg = <0x2>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900901 compatible = "sandbox,cpu_sandbox";
902 u-boot,dm-pre-reloc;
903 };
Mario Sixdea5df72018-08-06 10:23:44 +0200904
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +0200905 cpu3: cpu@3 {
906 device_type = "cpu";
907 reg = <0x3>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900908 compatible = "sandbox,cpu_sandbox";
909 u-boot,dm-pre-reloc;
910 };
Mario Sixdea5df72018-08-06 10:23:44 +0200911 };
912
Dave Gerlach75dbdfc2020-07-15 23:39:58 -0500913 chipid: chipid {
914 compatible = "sandbox,soc";
915 };
916
Simon Glassc953aaf2018-12-10 10:37:34 -0700917 i2s: i2s {
918 compatible = "sandbox,i2s";
919 #sound-dai-cells = <1>;
Simon Glass4d5814c2019-02-16 20:24:56 -0700920 sandbox,silent; /* Don't emit sounds while testing */
Simon Glassc953aaf2018-12-10 10:37:34 -0700921 };
922
Jean-Jacques Hiblotdb97c7f2019-07-05 09:33:57 +0200923 nop-test_0 {
924 compatible = "sandbox,nop_sandbox1";
925 nop-test_1 {
926 compatible = "sandbox,nop_sandbox2";
927 bind = "True";
928 };
929 nop-test_2 {
930 compatible = "sandbox,nop_sandbox2";
931 bind = "False";
932 };
933 };
934
Mario Sixa8ce0ee2018-07-31 14:24:14 +0200935 misc-test {
Sean Anderson13652b82022-05-05 13:11:44 -0400936 #address-cells = <1>;
937 #size-cells = <1>;
Mario Sixa8ce0ee2018-07-31 14:24:14 +0200938 compatible = "sandbox,misc_sandbox";
Sean Anderson13652b82022-05-05 13:11:44 -0400939
940 eth5_addr: mac-address@10 {
941 reg = <0x10 6>;
942 };
Mario Sixa8ce0ee2018-07-31 14:24:14 +0200943 };
944
Simon Glasse4fef742017-04-23 20:02:07 -0600945 mmc2 {
946 compatible = "sandbox,mmc";
Simon Glass965cd402021-07-05 16:32:58 -0600947 non-removable;
Simon Glasse4fef742017-04-23 20:02:07 -0600948 };
949
Simon Glassb255efc2022-04-24 23:31:24 -0600950 /* This is used for the bootdev tests */
Simon Glasse4fef742017-04-23 20:02:07 -0600951 mmc1 {
952 compatible = "sandbox,mmc";
Simon Glassb255efc2022-04-24 23:31:24 -0600953 filename = "mmc1.img";
Simon Glasse4fef742017-04-23 20:02:07 -0600954 };
955
Simon Glassb255efc2022-04-24 23:31:24 -0600956 /* This is used for the fastboot tests */
Simon Glasse4fef742017-04-23 20:02:07 -0600957 mmc0 {
Simon Glassd3e58e42015-07-06 12:54:32 -0600958 compatible = "sandbox,mmc";
959 };
960
Simon Glass53a68b32019-02-16 20:24:50 -0700961 pch {
962 compatible = "sandbox,pch";
963 };
964
Tom Rini4a3ca482020-02-11 12:41:23 -0500965 pci0: pci@0 {
Simon Glass3a6eae62015-03-05 12:25:34 -0700966 compatible = "sandbox,pci";
967 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500968 bus-range = <0x00 0xff>;
Simon Glass3a6eae62015-03-05 12:25:34 -0700969 #address-cells = <3>;
970 #size-cells = <2>;
Simon Glass35464f72019-09-25 08:56:08 -0600971 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glass3a6eae62015-03-05 12:25:34 -0700972 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Bin Mengcbf071b2018-08-03 01:14:39 -0700973 pci@0,0 {
974 compatible = "pci-generic";
975 reg = <0x0000 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600976 sandbox,emul = <&swap_case_emul0_0>;
Bin Mengcbf071b2018-08-03 01:14:39 -0700977 };
Alex Margineanf1274432019-06-07 11:24:24 +0300978 pci@1,0 {
979 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -0600980 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
981 reg = <0x02000814 0 0 0 0
982 0x01000810 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600983 sandbox,emul = <&swap_case_emul0_1>;
Alex Margineanf1274432019-06-07 11:24:24 +0300984 };
Simon Glass937bb472019-12-06 21:41:57 -0700985 p2sb-pci@2,0 {
986 compatible = "sandbox,p2sb";
987 reg = <0x02001010 0 0 0 0>;
988 sandbox,emul = <&p2sb_emul>;
989
990 adder {
991 intel,p2sb-port-id = <3>;
992 compatible = "sandbox,adder";
993 };
994 };
Simon Glass8c501022019-12-06 21:41:54 -0700995 pci@1e,0 {
996 compatible = "sandbox,pmc";
997 reg = <0xf000 0 0 0 0>;
998 sandbox,emul = <&pmc_emul1e>;
999 acpi-base = <0x400>;
1000 gpe0-dwx-mask = <0xf>;
1001 gpe0-dwx-shift-base = <4>;
1002 gpe0-dw = <6 7 9>;
1003 gpe0-sts = <0x20>;
1004 gpe0-en = <0x30>;
1005 };
Simon Glass3a6eae62015-03-05 12:25:34 -07001006 pci@1f,0 {
1007 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -06001008 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
1009 reg = <0x0100f810 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001010 sandbox,emul = <&swap_case_emul0_1f>;
Simon Glass3a6eae62015-03-05 12:25:34 -07001011 };
1012 };
1013
Simon Glassb98ba4c2019-09-25 08:56:10 -06001014 pci-emul0 {
1015 compatible = "sandbox,pci-emul-parent";
1016 swap_case_emul0_0: emul0@0,0 {
1017 compatible = "sandbox,swap-case";
1018 };
1019 swap_case_emul0_1: emul0@1,0 {
1020 compatible = "sandbox,swap-case";
1021 use-ea;
1022 };
1023 swap_case_emul0_1f: emul0@1f,0 {
1024 compatible = "sandbox,swap-case";
1025 };
Simon Glass937bb472019-12-06 21:41:57 -07001026 p2sb_emul: emul@2,0 {
1027 compatible = "sandbox,p2sb-emul";
1028 };
Simon Glass8c501022019-12-06 21:41:54 -07001029 pmc_emul1e: emul@1e,0 {
1030 compatible = "sandbox,pmc-emul";
1031 };
Simon Glassb98ba4c2019-09-25 08:56:10 -06001032 };
1033
Tom Rini4a3ca482020-02-11 12:41:23 -05001034 pci1: pci@1 {
Bin Meng408e5902018-08-03 01:14:41 -07001035 compatible = "sandbox,pci";
1036 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -05001037 bus-range = <0x00 0xff>;
Bin Meng408e5902018-08-03 01:14:41 -07001038 #address-cells = <3>;
1039 #size-cells = <2>;
Suneel Garapati3ac3aec2019-10-19 17:10:20 -07001040 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000 // MEM0
Andrew Scullc7456a42022-04-21 16:11:09 +00001041 0x02000000 0 0x31000000 0x3e000000 0 0x2000 // MEM1
Suneel Garapati3ac3aec2019-10-19 17:10:20 -07001042 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng5fed5362018-08-03 01:14:47 -07001043 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasute5733222018-10-10 21:27:08 +02001044 0x0c 0x00 0x1234 0x5678
1045 0x10 0x00 0x1234 0x5678>;
1046 pci@10,0 {
1047 reg = <0x8000 0 0 0 0>;
1048 };
Bin Meng408e5902018-08-03 01:14:41 -07001049 };
1050
Tom Rini4a3ca482020-02-11 12:41:23 -05001051 pci2: pci@2 {
Bin Meng510dddb2018-08-03 01:14:50 -07001052 compatible = "sandbox,pci";
1053 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -05001054 bus-range = <0x00 0xff>;
Bin Meng510dddb2018-08-03 01:14:50 -07001055 #address-cells = <3>;
1056 #size-cells = <2>;
1057 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
1058 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
1059 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
1060 pci@1f,0 {
1061 compatible = "pci-generic";
1062 reg = <0xf800 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001063 sandbox,emul = <&swap_case_emul2_1f>;
1064 };
1065 };
1066
1067 pci-emul2 {
1068 compatible = "sandbox,pci-emul-parent";
1069 swap_case_emul2_1f: emul2@1f,0 {
1070 compatible = "sandbox,swap-case";
Bin Meng510dddb2018-08-03 01:14:50 -07001071 };
1072 };
1073
Ramon Friedc64f19b2019-04-27 11:15:23 +03001074 pci_ep: pci_ep {
1075 compatible = "sandbox,pci_ep";
1076 };
1077
Simon Glass9c433fe2017-04-23 20:10:44 -06001078 probing {
1079 compatible = "simple-bus";
1080 test1 {
1081 compatible = "denx,u-boot-probe-test";
1082 };
1083
1084 test2 {
1085 compatible = "denx,u-boot-probe-test";
1086 };
1087
1088 test3 {
1089 compatible = "denx,u-boot-probe-test";
1090 };
1091
1092 test4 {
1093 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001094 first-syscon = <&syscon0>;
1095 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunayee010432019-03-07 09:57:13 +01001096 third-syscon = <&syscon2>;
Simon Glass9c433fe2017-04-23 20:10:44 -06001097 };
1098 };
1099
Stephen Warren92c67fa2016-07-13 13:45:31 -06001100 pwrdom: power-domain {
1101 compatible = "sandbox,power-domain";
1102 #power-domain-cells = <1>;
1103 };
1104
1105 power-domain-test {
1106 compatible = "sandbox,power-domain-test";
1107 power-domains = <&pwrdom 2>;
1108 };
1109
Simon Glass5620cf82018-10-01 12:22:40 -06001110 pwm: pwm {
Simon Glasse62f4be2017-04-16 21:01:11 -06001111 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -06001112 #pwm-cells = <2>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001113 pinctrl-names = "default";
1114 pinctrl-0 = <&pinmux_pwm_pins>;
Simon Glasse62f4be2017-04-16 21:01:11 -06001115 };
1116
1117 pwm2 {
1118 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -06001119 #pwm-cells = <2>;
Simon Glasse62f4be2017-04-16 21:01:11 -06001120 };
1121
Simon Glass3d355e62015-07-06 12:54:31 -06001122 ram {
1123 compatible = "sandbox,ram";
1124 };
1125
Simon Glassd860f222015-07-06 12:54:29 -06001126 reset@0 {
1127 compatible = "sandbox,warm-reset";
1128 };
1129
1130 reset@1 {
1131 compatible = "sandbox,reset";
1132 };
1133
Stephen Warren6488e642016-06-17 09:43:59 -06001134 resetc: reset-ctl {
1135 compatible = "sandbox,reset-ctl";
1136 #reset-cells = <1>;
1137 };
1138
1139 reset-ctl-test {
1140 compatible = "sandbox,reset-ctl-test";
Neil Armstrong9b4cdef2021-04-20 10:42:25 +02001141 resets = <&resetc 100>, <&resetc 2>, <&resetc 20>, <&resetc 40>;
1142 reset-names = "other", "test", "test2", "test3";
Stephen Warren6488e642016-06-17 09:43:59 -06001143 };
1144
Sughosh Ganu23e37512019-12-28 23:58:31 +05301145 rng {
1146 compatible = "sandbox,sandbox-rng";
1147 };
1148
Nishanth Menonedf85812015-09-17 15:42:41 -05001149 rproc_1: rproc@1 {
1150 compatible = "sandbox,test-processor";
1151 remoteproc-name = "remoteproc-test-dev1";
1152 };
1153
1154 rproc_2: rproc@2 {
1155 compatible = "sandbox,test-processor";
1156 internal-memory-mapped;
1157 remoteproc-name = "remoteproc-test-dev2";
1158 };
1159
Simon Glass5620cf82018-10-01 12:22:40 -06001160 panel {
1161 compatible = "simple-panel";
1162 backlight = <&backlight 0 100>;
1163 };
1164
Simon Glass509f32e2022-09-21 16:21:47 +02001165 scsi {
1166 compatible = "sandbox,scsi";
1167 sandbox,filepath = "scsi.img";
1168 };
1169
Ramon Fried26ed32e2018-07-02 02:57:59 +03001170 smem@0 {
1171 compatible = "sandbox,smem";
1172 };
1173
Simon Glass76072ac2018-12-10 10:37:36 -07001174 sound {
1175 compatible = "sandbox,sound";
1176 cpu {
1177 sound-dai = <&i2s 0>;
1178 };
1179
1180 codec {
1181 sound-dai = <&audio 0>;
1182 };
1183 };
1184
Simon Glass25348a42014-10-13 23:42:11 -06001185 spi@0 {
1186 #address-cells = <1>;
1187 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -06001188 reg = <0 1>;
Simon Glass25348a42014-10-13 23:42:11 -06001189 compatible = "sandbox,spi";
Ovidiu Panaitae734732020-12-14 19:06:47 +02001190 cs-gpios = <0>, <0>, <&gpio_a 0>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001191 pinctrl-names = "default";
1192 pinctrl-0 = <&pinmux_spi0_pins>;
1193
Simon Glass25348a42014-10-13 23:42:11 -06001194 spi.bin@0 {
1195 reg = <0>;
Neil Armstronga009fa72019-02-10 10:16:20 +00001196 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass25348a42014-10-13 23:42:11 -06001197 spi-max-frequency = <40000000>;
1198 sandbox,filename = "spi.bin";
1199 };
Ovidiu Panaitae734732020-12-14 19:06:47 +02001200 spi.bin@1 {
1201 reg = <1>;
1202 compatible = "spansion,m25p16", "jedec,spi-nor";
1203 spi-max-frequency = <50000000>;
1204 sandbox,filename = "spi.bin";
1205 spi-cpol;
1206 spi-cpha;
1207 };
Simon Glass25348a42014-10-13 23:42:11 -06001208 };
1209
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001210 syscon0: syscon@0 {
Simon Glasscd556522015-07-06 12:54:35 -06001211 compatible = "sandbox,syscon0";
Mario Sixe3f59f42018-10-04 09:00:40 +02001212 reg = <0x10 16>;
Simon Glasscd556522015-07-06 12:54:35 -06001213 };
1214
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001215 another_system_controller: syscon@1 {
Simon Glasscd556522015-07-06 12:54:35 -06001216 compatible = "sandbox,syscon1";
Simon Glasscf61f742015-07-06 12:54:36 -06001217 reg = <0x20 5
1218 0x28 6
1219 0x30 7
1220 0x38 8>;
Simon Glasscd556522015-07-06 12:54:35 -06001221 };
1222
Patrick Delaunayee010432019-03-07 09:57:13 +01001223 syscon2: syscon@2 {
Masahiro Yamada42ab1072018-04-23 13:26:53 +09001224 compatible = "simple-mfd", "syscon";
1225 reg = <0x40 5
1226 0x48 6
1227 0x50 7
1228 0x58 8>;
1229 };
1230
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +05301231 syscon3: syscon@3 {
1232 compatible = "simple-mfd", "syscon";
1233 reg = <0x000100 0x10>;
1234
1235 muxcontroller0: a-mux-controller {
1236 compatible = "mmio-mux";
1237 #mux-control-cells = <1>;
1238
1239 mux-reg-masks = <0x0 0x30>, /* 0: reg 0x0, bits 5:4 */
1240 <0xc 0x1E>, /* 1: reg 0xc, bits 4:1 */
1241 <0x4 0xFF>; /* 2: reg 0x4, bits 7:0 */
1242 idle-states = <MUX_IDLE_AS_IS>, <0x02>, <0x73>;
1243 u-boot,mux-autoprobe;
1244 };
1245 };
1246
1247 muxcontroller1: emul-mux-controller {
1248 compatible = "mux-emul";
1249 #mux-control-cells = <0>;
1250 u-boot,mux-autoprobe;
1251 idle-state = <0xabcd>;
1252 };
1253
Simon Glass791a17f2020-12-16 21:20:27 -07001254 testfdtm0 {
1255 compatible = "denx,u-boot-fdtm-test";
1256 };
1257
1258 testfdtm1: testfdtm1 {
1259 compatible = "denx,u-boot-fdtm-test";
1260 };
1261
1262 testfdtm2 {
1263 compatible = "denx,u-boot-fdtm-test";
1264 };
1265
Sean Anderson79d3bba2020-09-28 10:52:23 -04001266 timer@0 {
Thomas Chou6f2cfbf2015-12-11 16:27:34 +08001267 compatible = "sandbox,timer";
1268 clock-frequency = <1000000>;
1269 };
1270
Sean Anderson79d3bba2020-09-28 10:52:23 -04001271 timer@1 {
1272 compatible = "sandbox,timer";
1273 sandbox,timebase-frequency-fallback;
1274 };
1275
Miquel Raynal80938c12018-05-15 11:57:27 +02001276 tpm2 {
1277 compatible = "sandbox,tpm2";
1278 };
1279
Simon Glass5b968632015-05-22 15:42:15 -06001280 uart0: serial {
1281 compatible = "sandbox,serial";
1282 u-boot,dm-pre-reloc;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001283 pinctrl-names = "default";
1284 pinctrl-0 = <&pinmux_uart0_pins>;
Joe Hershberger4c197242015-03-22 17:09:15 -05001285 };
1286
Simon Glass31680482015-03-25 12:23:05 -06001287 usb_0: usb@0 {
1288 compatible = "sandbox,usb";
1289 status = "disabled";
1290 hub {
1291 compatible = "sandbox,usb-hub";
1292 #address-cells = <1>;
1293 #size-cells = <0>;
1294 flash-stick {
1295 reg = <0>;
1296 compatible = "sandbox,usb-flash";
1297 };
1298 };
1299 };
1300
1301 usb_1: usb@1 {
1302 compatible = "sandbox,usb";
Mark Kettenis67748ee2021-10-23 16:58:02 +02001303 iommus = <&iommu>;
Simon Glass31680482015-03-25 12:23:05 -06001304 hub {
1305 compatible = "usb-hub";
1306 usb,device-class = <9>;
Michael Walle7c961322020-06-02 01:47:07 +02001307 #address-cells = <1>;
1308 #size-cells = <0>;
Simon Glass31680482015-03-25 12:23:05 -06001309 hub-emul {
1310 compatible = "sandbox,usb-hub";
1311 #address-cells = <1>;
1312 #size-cells = <0>;
Simon Glass4700fe52015-11-08 23:48:01 -07001313 flash-stick@0 {
Simon Glass31680482015-03-25 12:23:05 -06001314 reg = <0>;
1315 compatible = "sandbox,usb-flash";
1316 sandbox,filepath = "testflash.bin";
1317 };
1318
Simon Glass4700fe52015-11-08 23:48:01 -07001319 flash-stick@1 {
1320 reg = <1>;
1321 compatible = "sandbox,usb-flash";
1322 sandbox,filepath = "testflash1.bin";
1323 };
1324
1325 flash-stick@2 {
1326 reg = <2>;
1327 compatible = "sandbox,usb-flash";
1328 sandbox,filepath = "testflash2.bin";
1329 };
1330
Simon Glassc0ccc722015-11-08 23:48:08 -07001331 keyb@3 {
1332 reg = <3>;
1333 compatible = "sandbox,usb-keyb";
1334 };
1335
Simon Glass31680482015-03-25 12:23:05 -06001336 };
Michael Walle7c961322020-06-02 01:47:07 +02001337
1338 usbstor@1 {
1339 reg = <1>;
1340 };
1341 usbstor@3 {
1342 reg = <3>;
1343 };
Simon Glass31680482015-03-25 12:23:05 -06001344 };
1345 };
1346
1347 usb_2: usb@2 {
1348 compatible = "sandbox,usb";
1349 status = "disabled";
1350 };
1351
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001352 spmi: spmi@0 {
1353 compatible = "sandbox,spmi";
1354 #address-cells = <0x1>;
1355 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -06001356 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001357 pm8916@0 {
1358 compatible = "qcom,spmi-pmic";
1359 reg = <0x0 0x1>;
1360 #address-cells = <0x1>;
1361 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -06001362 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001363
1364 spmi_gpios: gpios@c000 {
1365 compatible = "qcom,pm8916-gpio";
1366 reg = <0xc000 0x400>;
1367 gpio-controller;
1368 gpio-count = <4>;
1369 #gpio-cells = <2>;
1370 gpio-bank-name="spmi";
1371 };
1372 };
1373 };
maxims@google.comdaea6d42017-04-17 12:00:21 -07001374
1375 wdt0: wdt@0 {
1376 compatible = "sandbox,wdt";
Rasmus Villemoesf91ff5a2021-08-19 11:57:06 +02001377 hw_margin_ms = <200>;
maxims@google.comdaea6d42017-04-17 12:00:21 -07001378 };
Rob Clarka471b672018-01-10 11:33:30 +01001379
Mario Six95922152018-08-09 14:51:19 +02001380 axi: axi@0 {
1381 compatible = "sandbox,axi";
1382 #address-cells = <0x1>;
1383 #size-cells = <0x1>;
1384 store@0 {
1385 compatible = "sandbox,sandbox_store";
1386 reg = <0x0 0x400>;
1387 };
1388 };
1389
Rob Clarka471b672018-01-10 11:33:30 +01001390 chosen {
Simon Glass305ac9a2018-02-03 10:36:58 -07001391 #address-cells = <1>;
1392 #size-cells = <1>;
Simon Glassf3455962020-01-27 08:49:43 -07001393 setting = "sunrise ohoka";
1394 other-node = "/some-bus/c-test@5";
Simon Glasse09223c2020-01-27 08:49:46 -07001395 int-values = <0x1937 72993>;
Simon Glass3c601b12020-07-07 13:12:06 -06001396 u-boot,acpi-ssdt-order = <&acpi_test2 &acpi_test1>;
Rob Clarka471b672018-01-10 11:33:30 +01001397 chosen-test {
1398 compatible = "denx,u-boot-fdt-test";
1399 reg = <9 1>;
1400 };
Simon Glassc8d37212022-07-30 15:52:34 -06001401
1402 fwupd {
1403 compatible = "simple-bus";
1404 firmware0 {
1405 compatible = "fwupd,vbe-simple";
1406 storage = "mmc1";
1407 area-start = <0x400>;
1408 area-size = <0x1000>;
1409 skip-offset = <0x200>;
1410 state-offset = <0x400>;
1411 state-size = <0x40>;
1412 version-offset = <0x800>;
1413 version-size = <0x100>;
1414 };
1415 };
Rob Clarka471b672018-01-10 11:33:30 +01001416 };
Mario Six35616ef2018-03-12 14:53:33 +01001417
1418 translation-test@8000 {
1419 compatible = "simple-bus";
1420 reg = <0x8000 0x4000>;
1421
1422 #address-cells = <0x2>;
1423 #size-cells = <0x1>;
1424
1425 ranges = <0 0x0 0x8000 0x1000
1426 1 0x100 0x9000 0x1000
1427 2 0x200 0xA000 0x1000
1428 3 0x300 0xB000 0x1000
1429 >;
1430
Fabien Dessenne22236e02019-05-31 15:11:30 +02001431 dma-ranges = <0 0x000 0x10000000 0x1000
1432 1 0x100 0x20000000 0x1000
1433 >;
1434
Mario Six35616ef2018-03-12 14:53:33 +01001435 dev@0,0 {
1436 compatible = "denx,u-boot-fdt-dummy";
1437 reg = <0 0x0 0x1000>;
Álvaro Fernåndez Rojasa3181152018-12-03 19:37:09 +01001438 reg-names = "sandbox-dummy-0";
Mario Six35616ef2018-03-12 14:53:33 +01001439 };
1440
1441 dev@1,100 {
1442 compatible = "denx,u-boot-fdt-dummy";
1443 reg = <1 0x100 0x1000>;
1444
1445 };
1446
1447 dev@2,200 {
1448 compatible = "denx,u-boot-fdt-dummy";
1449 reg = <2 0x200 0x1000>;
1450 };
1451
1452
1453 noxlatebus@3,300 {
1454 compatible = "simple-bus";
1455 reg = <3 0x300 0x1000>;
1456
1457 #address-cells = <0x1>;
1458 #size-cells = <0x0>;
1459
1460 dev@42 {
1461 compatible = "denx,u-boot-fdt-dummy";
1462 reg = <0x42>;
1463 };
1464 };
1465 };
Mario Six02ad6fb2018-09-27 09:19:31 +02001466
1467 osd {
1468 compatible = "sandbox,sandbox_osd";
1469 };
Tom Rinib93eea72018-09-30 18:16:51 -04001470
Jens Wiklander86afaa62018-09-25 16:40:16 +02001471 sandbox_tee {
1472 compatible = "sandbox,tee";
1473 };
Bin Meng1bb290d2018-10-15 02:21:26 -07001474
1475 sandbox_virtio1 {
1476 compatible = "sandbox,virtio1";
1477 };
1478
1479 sandbox_virtio2 {
1480 compatible = "sandbox,virtio2";
1481 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001482
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +02001483 sandbox_scmi {
1484 compatible = "sandbox,scmi-devices";
Etienne Carrierebf1f1322022-02-21 09:22:41 +01001485 clocks = <&clk_scmi 2>, <&clk_scmi 0>;
Etienne Carriere09665cb2022-02-21 09:22:39 +01001486 resets = <&reset_scmi 3>;
1487 regul0-supply = <&regul0_scmi>;
1488 regul1-supply = <&regul1_scmi>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +02001489 };
1490
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001491 pinctrl {
1492 compatible = "sandbox,pinctrl";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001493
Sean Anderson3438e3b2020-09-14 11:01:57 -04001494 pinctrl-names = "default", "alternate";
1495 pinctrl-0 = <&pinctrl_gpios>, <&pinctrl_i2s>;
1496 pinctrl-1 = <&pinctrl_spi>, <&pinctrl_i2c>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001497
Sean Anderson3438e3b2020-09-14 11:01:57 -04001498 pinctrl_gpios: gpios {
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001499 gpio0 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001500 pins = "P5";
1501 function = "GPIO";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001502 bias-pull-up;
1503 input-disable;
1504 };
1505 gpio1 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001506 pins = "P6";
1507 function = "GPIO";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001508 output-high;
1509 drive-open-drain;
1510 };
1511 gpio2 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001512 pinmux = <SANDBOX_PINMUX(7, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001513 bias-pull-down;
1514 input-enable;
1515 };
1516 gpio3 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001517 pinmux = <SANDBOX_PINMUX(8, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001518 bias-disable;
1519 };
1520 };
Sean Anderson3438e3b2020-09-14 11:01:57 -04001521
1522 pinctrl_i2c: i2c {
1523 groups {
1524 groups = "I2C_UART";
1525 function = "I2C";
1526 };
1527
1528 pins {
1529 pins = "P0", "P1";
1530 drive-open-drain;
1531 };
1532 };
1533
1534 pinctrl_i2s: i2s {
1535 groups = "SPI_I2S";
1536 function = "I2S";
1537 };
1538
1539 pinctrl_spi: spi {
1540 groups = "SPI_I2S";
1541 function = "SPI";
1542
1543 cs {
1544 pinmux = <SANDBOX_PINMUX(5, SANDBOX_PINMUX_CS)>,
1545 <SANDBOX_PINMUX(6, SANDBOX_PINMUX_CS)>;
1546 };
1547 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001548 };
Benjamin Gaignarda550b542018-11-27 13:49:50 +01001549
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001550 pinctrl-single-no-width {
1551 compatible = "pinctrl-single";
1552 reg = <0x0000 0x238>;
1553 #pinctrl-cells = <1>;
1554 pinctrl-single,function-mask = <0x7f>;
1555 };
1556
1557 pinctrl-single-pins {
1558 compatible = "pinctrl-single";
1559 reg = <0x0000 0x238>;
1560 #pinctrl-cells = <1>;
1561 pinctrl-single,register-width = <32>;
1562 pinctrl-single,function-mask = <0x7f>;
1563
1564 pinmux_pwm_pins: pinmux_pwm_pins {
1565 pinctrl-single,pins = < 0x48 0x06 >;
1566 };
1567
1568 pinmux_spi0_pins: pinmux_spi0_pins {
1569 pinctrl-single,pins = <
1570 0x190 0x0c
1571 0x194 0x0c
1572 0x198 0x23
1573 0x19c 0x0c
1574 >;
1575 };
1576
1577 pinmux_uart0_pins: pinmux_uart0_pins {
1578 pinctrl-single,pins = <
1579 0x70 0x30
1580 0x74 0x00
1581 >;
1582 };
1583 };
1584
1585 pinctrl-single-bits {
1586 compatible = "pinctrl-single";
1587 reg = <0x0000 0x50>;
1588 #pinctrl-cells = <2>;
1589 pinctrl-single,bit-per-mux;
1590 pinctrl-single,register-width = <32>;
1591 pinctrl-single,function-mask = <0xf>;
1592
1593 pinmux_i2c0_pins: pinmux_i2c0_pins {
1594 pinctrl-single,bits = <
1595 0x10 0x00002200 0x0000ff00
1596 >;
1597 };
1598
1599 pinmux_lcd_pins: pinmux_lcd_pins {
1600 pinctrl-single,bits = <
1601 0x40 0x22222200 0xffffff00
1602 0x44 0x22222222 0xffffffff
1603 0x48 0x00000022 0x000000ff
1604 0x48 0x02000000 0x0f000000
1605 0x4c 0x02000022 0x0f0000ff
1606 >;
1607 };
1608 };
1609
Benjamin Gaignarda550b542018-11-27 13:49:50 +01001610 hwspinlock@0 {
1611 compatible = "sandbox,hwspinlock";
1612 };
Grygorii Strashko19ebf0b2018-11-28 19:17:51 +01001613
1614 dma: dma {
1615 compatible = "sandbox,dma";
1616 #dma-cells = <1>;
1617
1618 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
1619 dma-names = "m2m", "tx0", "rx0";
1620 };
Alex Marginean0daa53a2019-06-03 19:12:28 +03001621
Alex Marginean0649be52019-07-12 10:13:53 +03001622 /*
1623 * keep mdio-mux ahead of mdio so that the mux is removed first at the
1624 * end of the test. If parent mdio is removed first, clean-up of the
1625 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
1626 * active at the end of the test. That it turn doesn't allow the mdio
1627 * class to be destroyed, triggering an error.
1628 */
1629 mdio-mux-test {
1630 compatible = "sandbox,mdio-mux";
1631 #address-cells = <1>;
1632 #size-cells = <0>;
1633 mdio-parent-bus = <&mdio>;
1634
1635 mdio-ch-test@0 {
1636 reg = <0>;
1637 };
1638 mdio-ch-test@1 {
1639 reg = <1>;
1640 };
1641 };
1642
1643 mdio: mdio-test {
Alex Marginean0daa53a2019-06-03 19:12:28 +03001644 compatible = "sandbox,mdio";
Marek BehĂșnf4f1ddc2022-04-07 00:32:57 +02001645 #address-cells = <1>;
1646 #size-cells = <0>;
1647
1648 ethphy1: ethernet-phy@1 {
1649 reg = <1>;
1650 };
Alex Marginean0daa53a2019-06-03 19:12:28 +03001651 };
Sean Andersonb7860542020-06-24 06:41:12 -04001652
1653 pm-bus-test {
1654 compatible = "simple-pm-bus";
1655 clocks = <&clk_sandbox 4>;
1656 power-domains = <&pwrdom 1>;
1657 };
Sean Anderson0c1f6bf2020-06-24 06:41:14 -04001658
1659 resetc2: syscon-reset {
1660 compatible = "syscon-reset";
1661 #reset-cells = <1>;
1662 regmap = <&syscon0>;
1663 offset = <1>;
1664 mask = <0x27FFFFFF>;
1665 assert-high = <0>;
1666 };
1667
1668 syscon-reset-test {
1669 compatible = "sandbox,misc_sandbox";
1670 resets = <&resetc2 15>, <&resetc2 30>, <&resetc2 60>;
1671 reset-names = "valid", "no_mask", "out_of_range";
1672 };
Jean-Jacques Hiblot0b89fc52020-09-24 10:04:18 +05301673
Simon Glass458b66a2020-11-05 06:32:05 -07001674 sysinfo {
1675 compatible = "sandbox,sysinfo-sandbox";
1676 };
1677
Sean Anderson1c830672021-04-20 10:50:58 -04001678 sysinfo-gpio {
1679 compatible = "gpio-sysinfo";
1680 gpios = <&gpio_a 15>, <&gpio_a 16>, <&gpio_a 17>;
1681 revisions = <19>, <5>;
1682 names = "rev_a", "foo";
1683 };
1684
Jean-Jacques Hiblot0b89fc52020-09-24 10:04:18 +05301685 some_regmapped-bus {
1686 #address-cells = <0x1>;
1687 #size-cells = <0x1>;
1688
1689 ranges = <0x0 0x0 0x10>;
1690 compatible = "simple-bus";
1691
1692 regmap-test_0 {
1693 reg = <0 0x10>;
1694 compatible = "sandbox,regmap_test";
1695 };
1696 };
Simon Glassb2c1cac2014-02-26 15:59:21 -07001697};
Przemyslaw Marczak77bee052015-05-13 13:38:35 +02001698
1699#include "sandbox_pmic.dtsi"
Heinrich Schuchardte24fdef2021-02-18 13:01:35 +01001700#include "cros-ec-keyboard.dtsi"