blob: 155aece4c314dc05cc15c01a185b2c288e594794 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Pavel Machek5e2d70a2014-09-08 14:08:45 +02002/*
3 * Copyright (C) 2012 Altera Corporation <www.altera.com>
Pavel Machek5e2d70a2014-09-08 14:08:45 +02004 */
Dinh Nguyenf593acd2015-12-03 16:05:59 -06005#ifndef __CONFIG_SOCFPGA_COMMON_H__
6#define __CONFIG_SOCFPGA_COMMON_H__
Pavel Machek5e2d70a2014-09-08 14:08:45 +02007
Simon Glassfb64e362020-05-10 11:40:09 -06008#include <linux/stringify.h>
9
Pavel Machek5e2d70a2014-09-08 14:08:45 +020010/*
11 * High level configuration
12 */
Pavel Machek5e2d70a2014-09-08 14:08:45 +020013#define CONFIG_CLOCKS
14
Pavel Machek5e2d70a2014-09-08 14:08:45 +020015#define CONFIG_TIMESTAMP /* Print image info with timestamp */
16
17/*
18 * Memory configurations
19 */
Pavel Machek5e2d70a2014-09-08 14:08:45 +020020#define PHYS_SDRAM_1 0x0
Ley Foon Tan10b69642017-04-26 02:44:46 +080021#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
Pavel Machek5e2d70a2014-09-08 14:08:45 +020022#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
Ley Foon Tane62883b2020-03-06 16:55:19 +080023#define CONFIG_SYS_INIT_RAM_SIZE SOCFPGA_PHYS_OCRAM_SIZE
Ley Foon Tanc28cb932020-12-22 09:53:25 +080024#define CONFIG_SPL_PAD_TO 0x10000
Ley Foon Tan10b69642017-04-26 02:44:46 +080025#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
26#define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000
Ley Foon Tanc28cb932020-12-22 09:53:25 +080027#define CONFIG_SPL_PAD_TO 0x40000
Simon Goldschmidtfb2965c2019-04-09 21:02:04 +020028/* SPL memory allocation configuration, this is for FAT implementation */
29#ifndef CONFIG_SYS_SPL_MALLOC_SIZE
30#define CONFIG_SYS_SPL_MALLOC_SIZE 0x10000
31#endif
Ley Foon Tane62883b2020-03-06 16:55:19 +080032#define CONFIG_SYS_INIT_RAM_SIZE (SOCFPGA_PHYS_OCRAM_SIZE - \
33 CONFIG_SYS_SPL_MALLOC_SIZE)
Simon Goldschmidtfb2965c2019-04-09 21:02:04 +020034#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_INIT_RAM_ADDR + \
35 CONFIG_SYS_INIT_RAM_SIZE)
Ley Foon Tan10b69642017-04-26 02:44:46 +080036#endif
Stefan Roesead4105f2018-10-30 10:00:22 +010037
38/*
39 * Some boards (e.g. socfpga_sr1500) use 8 bytes at the end of the internal
40 * SRAM as bootcounter storage. Make sure to not put the stack directly
41 * at this address to not overwrite the bootcounter by checking, if the
42 * bootcounter address is located in the internal SRAM.
43 */
44#if ((CONFIG_SYS_BOOTCOUNT_ADDR > CONFIG_SYS_INIT_RAM_ADDR) && \
45 (CONFIG_SYS_BOOTCOUNT_ADDR < (CONFIG_SYS_INIT_RAM_ADDR + \
46 CONFIG_SYS_INIT_RAM_SIZE)))
Simon Goldschmidtfb2965c2019-04-09 21:02:04 +020047#define CONFIG_SPL_STACK CONFIG_SYS_BOOTCOUNT_ADDR
Stefan Roesead4105f2018-10-30 10:00:22 +010048#else
Simon Goldschmidtfb2965c2019-04-09 21:02:04 +020049#define CONFIG_SPL_STACK \
Marek Vasutbb45f272018-04-26 22:23:05 +020050 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
Stefan Roesead4105f2018-10-30 10:00:22 +010051#endif
Pavel Machek5e2d70a2014-09-08 14:08:45 +020052
Simon Goldschmidtfb2965c2019-04-09 21:02:04 +020053/*
54 * U-Boot stack setup: if SPL post-reloc uses DDR stack, use it in pre-reloc
55 * phase of U-Boot, too. This prevents overwriting SPL data if stack/heap usage
56 * in U-Boot pre-reloc is higher than in SPL.
57 */
58#if defined(CONFIG_SPL_STACK_R_ADDR) && CONFIG_SPL_STACK_R_ADDR
59#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK_R_ADDR
60#else
61#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK
62#endif
63
Pavel Machek5e2d70a2014-09-08 14:08:45 +020064#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
Pavel Machek5e2d70a2014-09-08 14:08:45 +020065
66/*
67 * U-Boot general configurations
68 */
Pavel Machek5e2d70a2014-09-08 14:08:45 +020069#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
Pavel Machek5e2d70a2014-09-08 14:08:45 +020070 /* Print buffer size */
71#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
72#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
73 /* Boot argument buffer size */
Pavel Machek5e2d70a2014-09-08 14:08:45 +020074
75/*
76 * Cache
77 */
Pavel Machek5e2d70a2014-09-08 14:08:45 +020078#define CONFIG_SYS_L2_PL310
79#define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS
80
81/*
82 * Ethernet on SoC (EMAC)
83 */
Marek Vasut0d5abc92018-04-23 01:26:10 +020084#ifdef CONFIG_CMD_NET
Pavel Machek5e2d70a2014-09-08 14:08:45 +020085#define CONFIG_DW_ALTDESCRIPTOR
Pavel Machek5e2d70a2014-09-08 14:08:45 +020086#endif
87
88/*
89 * FPGA Driver
90 */
91#ifdef CONFIG_CMD_FPGA
Pavel Machek5e2d70a2014-09-08 14:08:45 +020092#define CONFIG_FPGA_COUNT 1
93#endif
Tien Fong Cheec5b16e12017-07-26 13:05:44 +080094
Pavel Machek5e2d70a2014-09-08 14:08:45 +020095/*
96 * L4 OSC1 Timer 0
97 */
Marek Vasutaaa40e72018-08-18 16:00:31 +020098#ifndef CONFIG_TIMER
Pavel Machek5e2d70a2014-09-08 14:08:45 +020099#define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
100#define CONFIG_SYS_TIMER_COUNTS_DOWN
101#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)
Marek Vasut979de712020-02-15 14:10:02 +0100102#ifndef CONFIG_SYS_TIMER_RATE
Pavel Machek5e2d70a2014-09-08 14:08:45 +0200103#define CONFIG_SYS_TIMER_RATE 25000000
Marek Vasutaaa40e72018-08-18 16:00:31 +0200104#endif
Marek Vasut979de712020-02-15 14:10:02 +0100105#endif
Pavel Machek5e2d70a2014-09-08 14:08:45 +0200106
107/*
108 * L4 Watchdog
109 */
Pavel Machek5e2d70a2014-09-08 14:08:45 +0200110#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
111#define CONFIG_DW_WDT_CLOCK_KHZ 25000
Pavel Machek5e2d70a2014-09-08 14:08:45 +0200112
113/*
114 * MMC Driver
115 */
116#ifdef CONFIG_CMD_MMC
Pavel Machek5e2d70a2014-09-08 14:08:45 +0200117/* FIXME */
118/* using smaller max blk cnt to avoid flooding the limited stack we have */
119#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */
120#endif
121
Stefan Roese9a468c02014-11-07 12:37:52 +0100122/*
Marek Vasut7e442d92015-12-20 04:00:46 +0100123 * NAND Support
124 */
125#ifdef CONFIG_NAND_DENALI
126#define CONFIG_SYS_MAX_NAND_DEVICE 1
Marek Vasut7e442d92015-12-20 04:00:46 +0100127#define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS
128#define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS
Marek Vasut7e442d92015-12-20 04:00:46 +0100129#endif
130
131/*
Stefan Roese9a468c02014-11-07 12:37:52 +0100132 * QSPI support
133 */
Stefan Roese9a468c02014-11-07 12:37:52 +0100134/* QSPI reference clock */
135#ifndef __ASSEMBLY__
136unsigned int cm_get_qspi_controller_clk_hz(void);
137#define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz()
138#endif
Stefan Roese9a468c02014-11-07 12:37:52 +0100139
Marek Vasutcabc3b42015-08-19 23:23:53 +0200140/*
Marek Vasut9f193122014-10-24 23:34:25 +0200141 * USB
142 */
Marek Vasut9f193122014-10-24 23:34:25 +0200143
144/*
Marek Vasut40f1d6b2014-11-04 04:25:09 +0100145 * USB Gadget (DFU, UMS)
146 */
147#if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
Marek Vasut40f1d6b2014-11-04 04:25:09 +0100148#define DFU_DEFAULT_POLL_TIMEOUT 300
149
150/* USB IDs */
Sam Protsenkob706ffd2016-04-13 14:20:30 +0300151#define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525
152#define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5
Marek Vasut40f1d6b2014-11-04 04:25:09 +0100153#endif
154
155/*
Pavel Machek5e2d70a2014-09-08 14:08:45 +0200156 * U-Boot environment
157 */
Pavel Machek5e2d70a2014-09-08 14:08:45 +0200158
Chin Liang Seefb73f6d2015-12-21 21:02:45 +0800159/* Environment for SDMMC boot */
Chin Liang Seefb73f6d2015-12-21 21:02:45 +0800160
Chin Liang See713e5b12016-02-24 16:50:22 +0800161/* Environment for QSPI boot */
Chin Liang See713e5b12016-02-24 16:50:22 +0800162
Pavel Machek5e2d70a2014-09-08 14:08:45 +0200163/*
164 * SPL
Marek Vasutea0123c2014-10-16 12:25:40 +0200165 *
Tien Fong Chee200ae352017-12-05 15:58:04 +0800166 * SRAM Memory layout for gen 5:
Marek Vasutea0123c2014-10-16 12:25:40 +0200167 *
168 * 0xFFFF_0000 ...... Start of SRAM
169 * 0xFFFF_xxxx ...... Top of stack (grows down)
Simon Goldschmidta3e50262019-04-09 21:02:03 +0200170 * 0xFFFF_yyyy ...... Global Data
171 * 0xFFFF_zzzz ...... Malloc area
172 * 0xFFFF_FFFF ...... End of SRAM
Tien Fong Chee200ae352017-12-05 15:58:04 +0800173 *
174 * SRAM Memory layout for Arria 10:
175 * 0xFFE0_0000 ...... Start of SRAM (bottom)
176 * 0xFFEx_xxxx ...... Top of stack (grows down to bottom)
177 * 0xFFEy_yyyy ...... Global Data
178 * 0xFFEz_zzzz ...... Malloc area (grows up to top)
179 * 0xFFE3_FFFF ...... End of SRAM (top)
Pavel Machek5e2d70a2014-09-08 14:08:45 +0200180 */
Simon Goldschmidt376a8f82019-03-15 20:44:32 +0100181#ifndef CONFIG_SPL_TEXT_BASE
Ley Foon Tan10b69642017-04-26 02:44:46 +0800182#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE
Simon Goldschmidt376a8f82019-03-15 20:44:32 +0100183#endif
Pavel Machek5e2d70a2014-09-08 14:08:45 +0200184
Marek Vasut1029caf2015-07-10 00:04:23 +0200185/* SPL SDMMC boot support */
Simon Glassb58bfe02021-08-08 12:20:09 -0600186#ifdef CONFIG_SPL_MMC
Tien Fong Chee6091dd12019-01-23 14:20:05 +0800187#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
Dalon Westergreen7c4c0c32019-08-07 10:37:36 -0700188#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
Dalon Westergreenbfd74c62017-04-13 07:30:29 -0700189#endif
Marek Vasut1029caf2015-07-10 00:04:23 +0200190#endif
Pavel Machek5e2d70a2014-09-08 14:08:45 +0200191
Marek Vasutcadf2f92015-07-21 07:50:03 +0200192/* SPL QSPI boot support */
Marek Vasutcadf2f92015-07-21 07:50:03 +0200193
Marek Vasut7e442d92015-12-20 04:00:46 +0100194/* SPL NAND boot support */
Marek Vasut7e442d92015-12-20 04:00:46 +0100195
Dalon Westergreenbfd74c62017-04-13 07:30:29 -0700196/* Extra Environment */
197#ifndef CONFIG_SPL_BUILD
Dalon Westergreenbfd74c62017-04-13 07:30:29 -0700198
Simon Goldschmidt2e5d9a62018-01-25 07:18:27 +0100199#ifdef CONFIG_CMD_DHCP
200#define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na)
201#else
202#define BOOT_TARGET_DEVICES_DHCP(func)
203#endif
204
Joe Hershberger8e8594f2018-04-13 15:26:40 -0500205#if defined(CONFIG_CMD_PXE) && defined(CONFIG_CMD_DHCP)
Dalon Westergreenbfd74c62017-04-13 07:30:29 -0700206#define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na)
207#else
208#define BOOT_TARGET_DEVICES_PXE(func)
209#endif
210
211#ifdef CONFIG_CMD_MMC
212#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
213#else
214#define BOOT_TARGET_DEVICES_MMC(func)
215#endif
216
217#define BOOT_TARGET_DEVICES(func) \
218 BOOT_TARGET_DEVICES_MMC(func) \
219 BOOT_TARGET_DEVICES_PXE(func) \
Simon Goldschmidt2e5d9a62018-01-25 07:18:27 +0100220 BOOT_TARGET_DEVICES_DHCP(func)
Dalon Westergreenbfd74c62017-04-13 07:30:29 -0700221
222#include <config_distro_bootcmd.h>
223
224#ifndef CONFIG_EXTRA_ENV_SETTINGS
225#define CONFIG_EXTRA_ENV_SETTINGS \
226 "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
227 "bootm_size=0xa000000\0" \
228 "kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \
229 "fdt_addr_r=0x02000000\0" \
230 "scriptaddr=0x02100000\0" \
231 "pxefile_addr_r=0x02200000\0" \
232 "ramdisk_addr_r=0x02300000\0" \
Simon Goldschmidt0de397b2019-03-01 20:12:31 +0100233 "socfpga_legacy_reset_compat=1\0" \
Dalon Westergreenbfd74c62017-04-13 07:30:29 -0700234 BOOTENV
235
236#endif
237#endif
238
Dinh Nguyenf593acd2015-12-03 16:05:59 -0600239#endif /* __CONFIG_SOCFPGA_COMMON_H__ */