blob: b5754e6c0bb1d62651f41a6bc5073036901e88c1 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Michal Simekaf482d52012-09-28 09:56:37 +00002/*
3 * (C) Copyright 2012 Michal Simek <monstr@monstr.eu>
Michal Simek98d0f1f2018-01-17 07:37:47 +01004 * (C) Copyright 2013 - 2018 Xilinx, Inc.
Michal Simekaf482d52012-09-28 09:56:37 +00005 */
6
Tom Rinidec7ea02024-05-20 13:35:03 -06007#include <config.h>
Algapally Santosh Sagar25903c52023-06-14 03:03:59 -06008#include <debug_uart.h>
9#include <dfu.h>
Michal Simek806be2d2025-02-26 16:35:45 -060010#include <efi_loader.h>
Simon Glassa7b51302019-11-14 12:57:46 -070011#include <init.h>
Michal Simekbab07b62020-07-28 12:45:47 +020012#include <log.h>
Michal Simek309ef802018-02-21 17:04:28 +010013#include <dm/uclass.h>
Simon Glass5e6201b2019-08-01 09:46:51 -060014#include <env.h>
Ashok Reddy Soma909546d2021-02-23 08:07:45 -070015#include <env_internal.h>
Michal Simek65ef52f2014-02-24 11:16:32 +010016#include <fdtdec.h>
Michal Simek0f796702014-04-25 13:51:17 +020017#include <fpga.h>
Siva Durga Prasad Paladugubd75bc12019-01-25 17:06:06 +053018#include <malloc.h>
Michal Simek2a7d9522021-08-27 12:53:32 +020019#include <memalign.h>
Michal Simek0f796702014-04-25 13:51:17 +020020#include <mmc.h>
Michal Simekc07b2252018-06-08 13:45:14 +020021#include <watchdog.h>
Michal Simek309ef802018-02-21 17:04:28 +010022#include <wdt.h>
Michal Simek15d654c2013-04-22 15:43:02 +020023#include <zynqpl.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060024#include <asm/global_data.h>
Michal Simek242192b2013-04-12 16:33:08 +020025#include <asm/arch/hardware.h>
26#include <asm/arch/sys_proto.h>
Michal Simek705d44a2020-03-31 12:39:37 +020027#include "../common/board.h"
Michal Simekaf482d52012-09-28 09:56:37 +000028
29DECLARE_GLOBAL_DATA_PTR;
30
Simon Glass49c24a82024-09-29 19:49:47 -060031#if !defined(CONFIG_XPL_BUILD) && defined(CONFIG_DEBUG_UART_BOARD_INIT)
Michal Simek7659fe42022-02-17 14:28:41 +010032void board_debug_uart_init(void)
33{
34 /* Add initialization sequence if UART is not configured */
35}
36#endif
37
Michal Simekaf482d52012-09-28 09:56:37 +000038int board_init(void)
39{
Simon Glass49c24a82024-09-29 19:49:47 -060040 if (IS_ENABLED(CONFIG_XPL_BUILD))
Michal Simekae9dc112021-02-02 16:34:48 +010041 printf("Silicon version:\t%d\n", zynq_get_silicon_version());
42
Michal Simek1eb7b222022-09-27 09:55:46 +020043 if (CONFIG_IS_ENABLED(DM_I2C) && CONFIG_IS_ENABLED(I2C_EEPROM))
44 xilinx_read_eeprom();
45
Michal Simekaf482d52012-09-28 09:56:37 +000046 return 0;
47}
48
Jagannadha Sutradharudu Teki11704c22014-01-09 01:48:21 +053049int board_late_init(void)
50{
Siva Durga Prasad Paladugubd75bc12019-01-25 17:06:06 +053051 int env_targets_len = 0;
52 const char *mode;
53 char *new_targets;
54 char *env_targets;
55
Michal Simekbab07b62020-07-28 12:45:47 +020056 if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
57 debug("Saved variables - Skipping\n");
58 return 0;
59 }
60
Simon Glass094778f2023-02-05 15:39:49 -070061 if (!IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG))
Michal Simekbab07b62020-07-28 12:45:47 +020062 return 0;
63
Jagannadha Sutradharudu Teki11704c22014-01-09 01:48:21 +053064 switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
Michal Simek19356712016-12-16 13:16:14 +010065 case ZYNQ_BM_QSPI:
Siva Durga Prasad Paladugubd75bc12019-01-25 17:06:06 +053066 mode = "qspi";
Simon Glass6a38e412017-08-03 12:22:09 -060067 env_set("modeboot", "qspiboot");
Michal Simek19356712016-12-16 13:16:14 +010068 break;
69 case ZYNQ_BM_NAND:
Siva Durga Prasad Paladugubd75bc12019-01-25 17:06:06 +053070 mode = "nand";
Simon Glass6a38e412017-08-03 12:22:09 -060071 env_set("modeboot", "nandboot");
Michal Simek19356712016-12-16 13:16:14 +010072 break;
Jagannadha Sutradharudu Teki11704c22014-01-09 01:48:21 +053073 case ZYNQ_BM_NOR:
Siva Durga Prasad Paladugubd75bc12019-01-25 17:06:06 +053074 mode = "nor";
Simon Glass6a38e412017-08-03 12:22:09 -060075 env_set("modeboot", "norboot");
Jagannadha Sutradharudu Teki11704c22014-01-09 01:48:21 +053076 break;
77 case ZYNQ_BM_SD:
Michal Simek9541d0b2019-09-11 12:51:49 +020078 mode = "mmc0";
Simon Glass6a38e412017-08-03 12:22:09 -060079 env_set("modeboot", "sdboot");
Jagannadha Sutradharudu Teki11704c22014-01-09 01:48:21 +053080 break;
81 case ZYNQ_BM_JTAG:
T Karthik Reddy6c28c292019-11-13 21:13:44 -070082 mode = "jtag pxe dhcp";
Simon Glass6a38e412017-08-03 12:22:09 -060083 env_set("modeboot", "jtagboot");
Jagannadha Sutradharudu Teki11704c22014-01-09 01:48:21 +053084 break;
85 default:
Siva Durga Prasad Paladugubd75bc12019-01-25 17:06:06 +053086 mode = "";
Simon Glass6a38e412017-08-03 12:22:09 -060087 env_set("modeboot", "");
Jagannadha Sutradharudu Teki11704c22014-01-09 01:48:21 +053088 break;
89 }
90
Siva Durga Prasad Paladugubd75bc12019-01-25 17:06:06 +053091 /*
92 * One terminating char + one byte for space between mode
93 * and default boot_targets
94 */
95 env_targets = env_get("boot_targets");
96 if (env_targets)
97 env_targets_len = strlen(env_targets);
98
99 new_targets = calloc(1, strlen(mode) + env_targets_len + 2);
100 if (!new_targets)
101 return -ENOMEM;
102
103 sprintf(new_targets, "%s %s", mode,
104 env_targets ? env_targets : "");
105
106 env_set("boot_targets", new_targets);
107
Michal Simek705d44a2020-03-31 12:39:37 +0200108 return board_late_init_xilinx();
Jagannadha Sutradharudu Teki11704c22014-01-09 01:48:21 +0530109}
Michal Simekaf482d52012-09-28 09:56:37 +0000110
Tom Rinibb4dd962022-11-16 13:10:37 -0500111#if !defined(CFG_SYS_SDRAM_BASE) && !defined(CFG_SYS_SDRAM_SIZE)
Simon Glass2f949c32017-03-31 08:40:32 -0600112int dram_init_banksize(void)
Nathan Rossic12892b2016-12-04 19:33:22 +1000113{
Michal Simekd5b7de62017-11-03 15:25:51 +0100114 return fdtdec_setup_memory_banksize();
Tom Riniedcfdbd2016-12-09 07:56:54 -0500115}
Michal Simekf4780a72016-04-01 15:56:33 +0200116
Tom Riniedcfdbd2016-12-09 07:56:54 -0500117int dram_init(void)
118{
Siva Durga Prasad Paladugub3d55ea2018-07-16 15:56:11 +0530119 if (fdtdec_setup_mem_size_base() != 0)
Nathan Rossi58ea0d82016-12-19 00:03:34 +1000120 return -EINVAL;
Tom Riniedcfdbd2016-12-09 07:56:54 -0500121
122 zynq_ddrc_init();
123
124 return 0;
Michal Simekf4780a72016-04-01 15:56:33 +0200125}
Michal Simekf4780a72016-04-01 15:56:33 +0200126#else
127int dram_init(void)
128{
Tom Rinibb4dd962022-11-16 13:10:37 -0500129 gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
130 CFG_SYS_SDRAM_SIZE);
Michal Simekf4780a72016-04-01 15:56:33 +0200131
Michal Simekf5ff7bc2013-06-17 14:37:01 +0200132 zynq_ddrc_init();
133
Michal Simekaf482d52012-09-28 09:56:37 +0000134 return 0;
135}
Michal Simekf4780a72016-04-01 15:56:33 +0200136#endif
Ashok Reddy Soma909546d2021-02-23 08:07:45 -0700137
138enum env_location env_get_location(enum env_operation op, int prio)
139{
140 u32 bootmode = zynq_slcr_get_boot_mode() & ZYNQ_BM_MASK;
141
142 if (prio)
143 return ENVL_UNKNOWN;
144
145 switch (bootmode) {
146 case ZYNQ_BM_SD:
147 if (IS_ENABLED(CONFIG_ENV_IS_IN_FAT))
148 return ENVL_FAT;
149 if (IS_ENABLED(CONFIG_ENV_IS_IN_EXT4))
150 return ENVL_EXT4;
Mike Looijmans682cf082021-07-02 10:28:36 +0200151 return ENVL_NOWHERE;
Ashok Reddy Soma909546d2021-02-23 08:07:45 -0700152 case ZYNQ_BM_NAND:
153 if (IS_ENABLED(CONFIG_ENV_IS_IN_NAND))
154 return ENVL_NAND;
155 if (IS_ENABLED(CONFIG_ENV_IS_IN_UBI))
156 return ENVL_UBI;
Mike Looijmans682cf082021-07-02 10:28:36 +0200157 return ENVL_NOWHERE;
Ashok Reddy Soma909546d2021-02-23 08:07:45 -0700158 case ZYNQ_BM_NOR:
159 case ZYNQ_BM_QSPI:
160 if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH))
161 return ENVL_SPI_FLASH;
Mike Looijmans682cf082021-07-02 10:28:36 +0200162 return ENVL_NOWHERE;
Ashok Reddy Soma909546d2021-02-23 08:07:45 -0700163 case ZYNQ_BM_JTAG:
164 default:
165 return ENVL_NOWHERE;
166 }
167}
Michal Simek2a7d9522021-08-27 12:53:32 +0200168
169#if defined(CONFIG_SET_DFU_ALT_INFO)
170
171#define DFU_ALT_BUF_LEN SZ_1K
172
173void set_dfu_alt_info(char *interface, char *devstr)
174{
175 ALLOC_CACHE_ALIGN_BUFFER(char, buf, DFU_ALT_BUF_LEN);
176
Michal Simekf0d6f462022-08-09 16:32:52 +0200177 if (env_get("dfu_alt_info"))
Michal Simek2a7d9522021-08-27 12:53:32 +0200178 return;
179
180 memset(buf, 0, sizeof(buf));
181
182 switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
Michal Simekd9e4c472025-02-07 07:43:23 +0100183#if defined(CONFIG_SPL_FS_LOAD_PAYLOAD_NAME)
Michal Simek2a7d9522021-08-27 12:53:32 +0200184 case ZYNQ_BM_SD:
185 snprintf(buf, DFU_ALT_BUF_LEN,
Michal Simek3e09d192022-08-09 16:32:54 +0200186 "mmc 0=boot.bin fat 0 1;"
Michal Simekca1b5d02022-08-09 16:32:53 +0200187 "%s fat 0 1", CONFIG_SPL_FS_LOAD_PAYLOAD_NAME);
Michal Simek2a7d9522021-08-27 12:53:32 +0200188 break;
Michal Simekd26c7ef2023-11-13 10:05:27 +0100189#if defined(CONFIG_SPL_SPI_LOAD)
Michal Simek2a7d9522021-08-27 12:53:32 +0200190 case ZYNQ_BM_QSPI:
191 snprintf(buf, DFU_ALT_BUF_LEN,
192 "sf 0:0=boot.bin raw 0 0x1500000;"
Michal Simekca1b5d02022-08-09 16:32:53 +0200193 "%s raw 0x%x 0x500000",
194 CONFIG_SPL_FS_LOAD_PAYLOAD_NAME,
Michal Simek2a7d9522021-08-27 12:53:32 +0200195 CONFIG_SYS_SPI_U_BOOT_OFFS);
196 break;
Michal Simekd26c7ef2023-11-13 10:05:27 +0100197#endif
Michal Simekd9e4c472025-02-07 07:43:23 +0100198#endif
Michal Simek2a7d9522021-08-27 12:53:32 +0200199 default:
200 return;
201 }
202
203 env_set("dfu_alt_info", buf);
204 puts("DFU alt info setting: done\n");
Michal Simek806be2d2025-02-26 16:35:45 -0600205 update_info.dfu_string = strdup(buf);
206 debug("Capsule DFU: %s\n", update_info.dfu_string);
Michal Simek2a7d9522021-08-27 12:53:32 +0200207}
208#endif