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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Michal Simekaf482d52012-09-28 09:56:37 +00002/*
3 * (C) Copyright 2012 Michal Simek <monstr@monstr.eu>
Michal Simek98d0f1f2018-01-17 07:37:47 +01004 * (C) Copyright 2013 - 2018 Xilinx, Inc.
Michal Simekaf482d52012-09-28 09:56:37 +00005 */
6
7#include <common.h>
Simon Glassa7b51302019-11-14 12:57:46 -07008#include <init.h>
Michal Simekbab07b62020-07-28 12:45:47 +02009#include <log.h>
Michal Simek309ef802018-02-21 17:04:28 +010010#include <dm/uclass.h>
Simon Glass5e6201b2019-08-01 09:46:51 -060011#include <env.h>
Ashok Reddy Soma909546d2021-02-23 08:07:45 -070012#include <env_internal.h>
Michal Simek65ef52f2014-02-24 11:16:32 +010013#include <fdtdec.h>
Michal Simek0f796702014-04-25 13:51:17 +020014#include <fpga.h>
Siva Durga Prasad Paladugubd75bc12019-01-25 17:06:06 +053015#include <malloc.h>
Michal Simek2a7d9522021-08-27 12:53:32 +020016#include <memalign.h>
Michal Simek0f796702014-04-25 13:51:17 +020017#include <mmc.h>
Michal Simekc07b2252018-06-08 13:45:14 +020018#include <watchdog.h>
Michal Simek309ef802018-02-21 17:04:28 +010019#include <wdt.h>
Michal Simek15d654c2013-04-22 15:43:02 +020020#include <zynqpl.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060021#include <asm/global_data.h>
Michal Simek242192b2013-04-12 16:33:08 +020022#include <asm/arch/hardware.h>
23#include <asm/arch/sys_proto.h>
Michal Simek705d44a2020-03-31 12:39:37 +020024#include "../common/board.h"
Michal Simekaf482d52012-09-28 09:56:37 +000025
26DECLARE_GLOBAL_DATA_PTR;
27
Michal Simek7659fe42022-02-17 14:28:41 +010028#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_DEBUG_UART_BOARD_INIT)
29void board_debug_uart_init(void)
30{
31 /* Add initialization sequence if UART is not configured */
32}
33#endif
34
Michal Simekaf482d52012-09-28 09:56:37 +000035int board_init(void)
36{
Michal Simekae9dc112021-02-02 16:34:48 +010037 if (IS_ENABLED(CONFIG_SPL_BUILD))
38 printf("Silicon version:\t%d\n", zynq_get_silicon_version());
39
Michal Simek1eb7b222022-09-27 09:55:46 +020040 if (CONFIG_IS_ENABLED(DM_I2C) && CONFIG_IS_ENABLED(I2C_EEPROM))
41 xilinx_read_eeprom();
42
Michal Simekaf482d52012-09-28 09:56:37 +000043 return 0;
44}
45
Jagannadha Sutradharudu Teki11704c22014-01-09 01:48:21 +053046int board_late_init(void)
47{
Siva Durga Prasad Paladugubd75bc12019-01-25 17:06:06 +053048 int env_targets_len = 0;
49 const char *mode;
50 char *new_targets;
51 char *env_targets;
52
Michal Simekbab07b62020-07-28 12:45:47 +020053 if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
54 debug("Saved variables - Skipping\n");
55 return 0;
56 }
57
58 if (!CONFIG_IS_ENABLED(ENV_VARS_UBOOT_RUNTIME_CONFIG))
59 return 0;
60
Jagannadha Sutradharudu Teki11704c22014-01-09 01:48:21 +053061 switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
Michal Simek19356712016-12-16 13:16:14 +010062 case ZYNQ_BM_QSPI:
Siva Durga Prasad Paladugubd75bc12019-01-25 17:06:06 +053063 mode = "qspi";
Simon Glass6a38e412017-08-03 12:22:09 -060064 env_set("modeboot", "qspiboot");
Michal Simek19356712016-12-16 13:16:14 +010065 break;
66 case ZYNQ_BM_NAND:
Siva Durga Prasad Paladugubd75bc12019-01-25 17:06:06 +053067 mode = "nand";
Simon Glass6a38e412017-08-03 12:22:09 -060068 env_set("modeboot", "nandboot");
Michal Simek19356712016-12-16 13:16:14 +010069 break;
Jagannadha Sutradharudu Teki11704c22014-01-09 01:48:21 +053070 case ZYNQ_BM_NOR:
Siva Durga Prasad Paladugubd75bc12019-01-25 17:06:06 +053071 mode = "nor";
Simon Glass6a38e412017-08-03 12:22:09 -060072 env_set("modeboot", "norboot");
Jagannadha Sutradharudu Teki11704c22014-01-09 01:48:21 +053073 break;
74 case ZYNQ_BM_SD:
Michal Simek9541d0b2019-09-11 12:51:49 +020075 mode = "mmc0";
Simon Glass6a38e412017-08-03 12:22:09 -060076 env_set("modeboot", "sdboot");
Jagannadha Sutradharudu Teki11704c22014-01-09 01:48:21 +053077 break;
78 case ZYNQ_BM_JTAG:
T Karthik Reddy6c28c292019-11-13 21:13:44 -070079 mode = "jtag pxe dhcp";
Simon Glass6a38e412017-08-03 12:22:09 -060080 env_set("modeboot", "jtagboot");
Jagannadha Sutradharudu Teki11704c22014-01-09 01:48:21 +053081 break;
82 default:
Siva Durga Prasad Paladugubd75bc12019-01-25 17:06:06 +053083 mode = "";
Simon Glass6a38e412017-08-03 12:22:09 -060084 env_set("modeboot", "");
Jagannadha Sutradharudu Teki11704c22014-01-09 01:48:21 +053085 break;
86 }
87
Siva Durga Prasad Paladugubd75bc12019-01-25 17:06:06 +053088 /*
89 * One terminating char + one byte for space between mode
90 * and default boot_targets
91 */
92 env_targets = env_get("boot_targets");
93 if (env_targets)
94 env_targets_len = strlen(env_targets);
95
96 new_targets = calloc(1, strlen(mode) + env_targets_len + 2);
97 if (!new_targets)
98 return -ENOMEM;
99
100 sprintf(new_targets, "%s %s", mode,
101 env_targets ? env_targets : "");
102
103 env_set("boot_targets", new_targets);
104
Michal Simek705d44a2020-03-31 12:39:37 +0200105 return board_late_init_xilinx();
Jagannadha Sutradharudu Teki11704c22014-01-09 01:48:21 +0530106}
Michal Simekaf482d52012-09-28 09:56:37 +0000107
Michal Simekf4780a72016-04-01 15:56:33 +0200108#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
Simon Glass2f949c32017-03-31 08:40:32 -0600109int dram_init_banksize(void)
Nathan Rossic12892b2016-12-04 19:33:22 +1000110{
Michal Simekd5b7de62017-11-03 15:25:51 +0100111 return fdtdec_setup_memory_banksize();
Tom Riniedcfdbd2016-12-09 07:56:54 -0500112}
Michal Simekf4780a72016-04-01 15:56:33 +0200113
Tom Riniedcfdbd2016-12-09 07:56:54 -0500114int dram_init(void)
115{
Siva Durga Prasad Paladugub3d55ea2018-07-16 15:56:11 +0530116 if (fdtdec_setup_mem_size_base() != 0)
Nathan Rossi58ea0d82016-12-19 00:03:34 +1000117 return -EINVAL;
Tom Riniedcfdbd2016-12-09 07:56:54 -0500118
119 zynq_ddrc_init();
120
121 return 0;
Michal Simekf4780a72016-04-01 15:56:33 +0200122}
Michal Simekf4780a72016-04-01 15:56:33 +0200123#else
124int dram_init(void)
125{
Michal Simek1b846212018-04-11 16:12:28 +0200126 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
127 CONFIG_SYS_SDRAM_SIZE);
Michal Simekf4780a72016-04-01 15:56:33 +0200128
Michal Simekf5ff7bc2013-06-17 14:37:01 +0200129 zynq_ddrc_init();
130
Michal Simekaf482d52012-09-28 09:56:37 +0000131 return 0;
132}
Michal Simekf4780a72016-04-01 15:56:33 +0200133#endif
Ashok Reddy Soma909546d2021-02-23 08:07:45 -0700134
135enum env_location env_get_location(enum env_operation op, int prio)
136{
137 u32 bootmode = zynq_slcr_get_boot_mode() & ZYNQ_BM_MASK;
138
139 if (prio)
140 return ENVL_UNKNOWN;
141
142 switch (bootmode) {
143 case ZYNQ_BM_SD:
144 if (IS_ENABLED(CONFIG_ENV_IS_IN_FAT))
145 return ENVL_FAT;
146 if (IS_ENABLED(CONFIG_ENV_IS_IN_EXT4))
147 return ENVL_EXT4;
Mike Looijmans682cf082021-07-02 10:28:36 +0200148 return ENVL_NOWHERE;
Ashok Reddy Soma909546d2021-02-23 08:07:45 -0700149 case ZYNQ_BM_NAND:
150 if (IS_ENABLED(CONFIG_ENV_IS_IN_NAND))
151 return ENVL_NAND;
152 if (IS_ENABLED(CONFIG_ENV_IS_IN_UBI))
153 return ENVL_UBI;
Mike Looijmans682cf082021-07-02 10:28:36 +0200154 return ENVL_NOWHERE;
Ashok Reddy Soma909546d2021-02-23 08:07:45 -0700155 case ZYNQ_BM_NOR:
156 case ZYNQ_BM_QSPI:
157 if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH))
158 return ENVL_SPI_FLASH;
Mike Looijmans682cf082021-07-02 10:28:36 +0200159 return ENVL_NOWHERE;
Ashok Reddy Soma909546d2021-02-23 08:07:45 -0700160 case ZYNQ_BM_JTAG:
161 default:
162 return ENVL_NOWHERE;
163 }
164}
Michal Simek2a7d9522021-08-27 12:53:32 +0200165
166#if defined(CONFIG_SET_DFU_ALT_INFO)
167
168#define DFU_ALT_BUF_LEN SZ_1K
169
170void set_dfu_alt_info(char *interface, char *devstr)
171{
172 ALLOC_CACHE_ALIGN_BUFFER(char, buf, DFU_ALT_BUF_LEN);
173
Michal Simekf0d6f462022-08-09 16:32:52 +0200174 if (env_get("dfu_alt_info"))
Michal Simek2a7d9522021-08-27 12:53:32 +0200175 return;
176
177 memset(buf, 0, sizeof(buf));
178
179 switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
180 case ZYNQ_BM_SD:
181 snprintf(buf, DFU_ALT_BUF_LEN,
Michal Simek3e09d192022-08-09 16:32:54 +0200182 "mmc 0=boot.bin fat 0 1;"
Michal Simekca1b5d02022-08-09 16:32:53 +0200183 "%s fat 0 1", CONFIG_SPL_FS_LOAD_PAYLOAD_NAME);
Michal Simek2a7d9522021-08-27 12:53:32 +0200184 break;
185 case ZYNQ_BM_QSPI:
186 snprintf(buf, DFU_ALT_BUF_LEN,
187 "sf 0:0=boot.bin raw 0 0x1500000;"
Michal Simekca1b5d02022-08-09 16:32:53 +0200188 "%s raw 0x%x 0x500000",
189 CONFIG_SPL_FS_LOAD_PAYLOAD_NAME,
Michal Simek2a7d9522021-08-27 12:53:32 +0200190 CONFIG_SYS_SPI_U_BOOT_OFFS);
191 break;
192 default:
193 return;
194 }
195
196 env_set("dfu_alt_info", buf);
197 puts("DFU alt info setting: done\n");
198}
199#endif