Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Michal Simek | af482d5 | 2012-09-28 09:56:37 +0000 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2012 Michal Simek <monstr@monstr.eu> |
Michal Simek | 98d0f1f | 2018-01-17 07:37:47 +0100 | [diff] [blame] | 4 | * (C) Copyright 2013 - 2018 Xilinx, Inc. |
Michal Simek | af482d5 | 2012-09-28 09:56:37 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #include <common.h> |
Simon Glass | a7b5130 | 2019-11-14 12:57:46 -0700 | [diff] [blame] | 8 | #include <init.h> |
Michal Simek | bab07b6 | 2020-07-28 12:45:47 +0200 | [diff] [blame] | 9 | #include <log.h> |
Michal Simek | 309ef80 | 2018-02-21 17:04:28 +0100 | [diff] [blame] | 10 | #include <dm/uclass.h> |
Simon Glass | 5e6201b | 2019-08-01 09:46:51 -0600 | [diff] [blame] | 11 | #include <env.h> |
Ashok Reddy Soma | 909546d | 2021-02-23 08:07:45 -0700 | [diff] [blame] | 12 | #include <env_internal.h> |
Michal Simek | 65ef52f | 2014-02-24 11:16:32 +0100 | [diff] [blame] | 13 | #include <fdtdec.h> |
Michal Simek | 0f79670 | 2014-04-25 13:51:17 +0200 | [diff] [blame] | 14 | #include <fpga.h> |
Siva Durga Prasad Paladugu | bd75bc1 | 2019-01-25 17:06:06 +0530 | [diff] [blame] | 15 | #include <malloc.h> |
Michal Simek | 2a7d952 | 2021-08-27 12:53:32 +0200 | [diff] [blame] | 16 | #include <memalign.h> |
Michal Simek | 0f79670 | 2014-04-25 13:51:17 +0200 | [diff] [blame] | 17 | #include <mmc.h> |
Michal Simek | c07b225 | 2018-06-08 13:45:14 +0200 | [diff] [blame] | 18 | #include <watchdog.h> |
Michal Simek | 309ef80 | 2018-02-21 17:04:28 +0100 | [diff] [blame] | 19 | #include <wdt.h> |
Michal Simek | 15d654c | 2013-04-22 15:43:02 +0200 | [diff] [blame] | 20 | #include <zynqpl.h> |
Simon Glass | 3ba929a | 2020-10-30 21:38:53 -0600 | [diff] [blame] | 21 | #include <asm/global_data.h> |
Michal Simek | 242192b | 2013-04-12 16:33:08 +0200 | [diff] [blame] | 22 | #include <asm/arch/hardware.h> |
| 23 | #include <asm/arch/sys_proto.h> |
Michal Simek | 705d44a | 2020-03-31 12:39:37 +0200 | [diff] [blame] | 24 | #include "../common/board.h" |
Michal Simek | af482d5 | 2012-09-28 09:56:37 +0000 | [diff] [blame] | 25 | |
| 26 | DECLARE_GLOBAL_DATA_PTR; |
| 27 | |
Michal Simek | 7659fe4 | 2022-02-17 14:28:41 +0100 | [diff] [blame] | 28 | #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_DEBUG_UART_BOARD_INIT) |
| 29 | void board_debug_uart_init(void) |
| 30 | { |
| 31 | /* Add initialization sequence if UART is not configured */ |
| 32 | } |
| 33 | #endif |
| 34 | |
Michal Simek | af482d5 | 2012-09-28 09:56:37 +0000 | [diff] [blame] | 35 | int board_init(void) |
| 36 | { |
Michal Simek | ae9dc11 | 2021-02-02 16:34:48 +0100 | [diff] [blame] | 37 | if (IS_ENABLED(CONFIG_SPL_BUILD)) |
| 38 | printf("Silicon version:\t%d\n", zynq_get_silicon_version()); |
| 39 | |
Michal Simek | 1eb7b22 | 2022-09-27 09:55:46 +0200 | [diff] [blame^] | 40 | if (CONFIG_IS_ENABLED(DM_I2C) && CONFIG_IS_ENABLED(I2C_EEPROM)) |
| 41 | xilinx_read_eeprom(); |
| 42 | |
Michal Simek | af482d5 | 2012-09-28 09:56:37 +0000 | [diff] [blame] | 43 | return 0; |
| 44 | } |
| 45 | |
Jagannadha Sutradharudu Teki | 11704c2 | 2014-01-09 01:48:21 +0530 | [diff] [blame] | 46 | int board_late_init(void) |
| 47 | { |
Siva Durga Prasad Paladugu | bd75bc1 | 2019-01-25 17:06:06 +0530 | [diff] [blame] | 48 | int env_targets_len = 0; |
| 49 | const char *mode; |
| 50 | char *new_targets; |
| 51 | char *env_targets; |
| 52 | |
Michal Simek | bab07b6 | 2020-07-28 12:45:47 +0200 | [diff] [blame] | 53 | if (!(gd->flags & GD_FLG_ENV_DEFAULT)) { |
| 54 | debug("Saved variables - Skipping\n"); |
| 55 | return 0; |
| 56 | } |
| 57 | |
| 58 | if (!CONFIG_IS_ENABLED(ENV_VARS_UBOOT_RUNTIME_CONFIG)) |
| 59 | return 0; |
| 60 | |
Jagannadha Sutradharudu Teki | 11704c2 | 2014-01-09 01:48:21 +0530 | [diff] [blame] | 61 | switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) { |
Michal Simek | 1935671 | 2016-12-16 13:16:14 +0100 | [diff] [blame] | 62 | case ZYNQ_BM_QSPI: |
Siva Durga Prasad Paladugu | bd75bc1 | 2019-01-25 17:06:06 +0530 | [diff] [blame] | 63 | mode = "qspi"; |
Simon Glass | 6a38e41 | 2017-08-03 12:22:09 -0600 | [diff] [blame] | 64 | env_set("modeboot", "qspiboot"); |
Michal Simek | 1935671 | 2016-12-16 13:16:14 +0100 | [diff] [blame] | 65 | break; |
| 66 | case ZYNQ_BM_NAND: |
Siva Durga Prasad Paladugu | bd75bc1 | 2019-01-25 17:06:06 +0530 | [diff] [blame] | 67 | mode = "nand"; |
Simon Glass | 6a38e41 | 2017-08-03 12:22:09 -0600 | [diff] [blame] | 68 | env_set("modeboot", "nandboot"); |
Michal Simek | 1935671 | 2016-12-16 13:16:14 +0100 | [diff] [blame] | 69 | break; |
Jagannadha Sutradharudu Teki | 11704c2 | 2014-01-09 01:48:21 +0530 | [diff] [blame] | 70 | case ZYNQ_BM_NOR: |
Siva Durga Prasad Paladugu | bd75bc1 | 2019-01-25 17:06:06 +0530 | [diff] [blame] | 71 | mode = "nor"; |
Simon Glass | 6a38e41 | 2017-08-03 12:22:09 -0600 | [diff] [blame] | 72 | env_set("modeboot", "norboot"); |
Jagannadha Sutradharudu Teki | 11704c2 | 2014-01-09 01:48:21 +0530 | [diff] [blame] | 73 | break; |
| 74 | case ZYNQ_BM_SD: |
Michal Simek | 9541d0b | 2019-09-11 12:51:49 +0200 | [diff] [blame] | 75 | mode = "mmc0"; |
Simon Glass | 6a38e41 | 2017-08-03 12:22:09 -0600 | [diff] [blame] | 76 | env_set("modeboot", "sdboot"); |
Jagannadha Sutradharudu Teki | 11704c2 | 2014-01-09 01:48:21 +0530 | [diff] [blame] | 77 | break; |
| 78 | case ZYNQ_BM_JTAG: |
T Karthik Reddy | 6c28c29 | 2019-11-13 21:13:44 -0700 | [diff] [blame] | 79 | mode = "jtag pxe dhcp"; |
Simon Glass | 6a38e41 | 2017-08-03 12:22:09 -0600 | [diff] [blame] | 80 | env_set("modeboot", "jtagboot"); |
Jagannadha Sutradharudu Teki | 11704c2 | 2014-01-09 01:48:21 +0530 | [diff] [blame] | 81 | break; |
| 82 | default: |
Siva Durga Prasad Paladugu | bd75bc1 | 2019-01-25 17:06:06 +0530 | [diff] [blame] | 83 | mode = ""; |
Simon Glass | 6a38e41 | 2017-08-03 12:22:09 -0600 | [diff] [blame] | 84 | env_set("modeboot", ""); |
Jagannadha Sutradharudu Teki | 11704c2 | 2014-01-09 01:48:21 +0530 | [diff] [blame] | 85 | break; |
| 86 | } |
| 87 | |
Siva Durga Prasad Paladugu | bd75bc1 | 2019-01-25 17:06:06 +0530 | [diff] [blame] | 88 | /* |
| 89 | * One terminating char + one byte for space between mode |
| 90 | * and default boot_targets |
| 91 | */ |
| 92 | env_targets = env_get("boot_targets"); |
| 93 | if (env_targets) |
| 94 | env_targets_len = strlen(env_targets); |
| 95 | |
| 96 | new_targets = calloc(1, strlen(mode) + env_targets_len + 2); |
| 97 | if (!new_targets) |
| 98 | return -ENOMEM; |
| 99 | |
| 100 | sprintf(new_targets, "%s %s", mode, |
| 101 | env_targets ? env_targets : ""); |
| 102 | |
| 103 | env_set("boot_targets", new_targets); |
| 104 | |
Michal Simek | 705d44a | 2020-03-31 12:39:37 +0200 | [diff] [blame] | 105 | return board_late_init_xilinx(); |
Jagannadha Sutradharudu Teki | 11704c2 | 2014-01-09 01:48:21 +0530 | [diff] [blame] | 106 | } |
Michal Simek | af482d5 | 2012-09-28 09:56:37 +0000 | [diff] [blame] | 107 | |
Michal Simek | f4780a7 | 2016-04-01 15:56:33 +0200 | [diff] [blame] | 108 | #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE) |
Simon Glass | 2f949c3 | 2017-03-31 08:40:32 -0600 | [diff] [blame] | 109 | int dram_init_banksize(void) |
Nathan Rossi | c12892b | 2016-12-04 19:33:22 +1000 | [diff] [blame] | 110 | { |
Michal Simek | d5b7de6 | 2017-11-03 15:25:51 +0100 | [diff] [blame] | 111 | return fdtdec_setup_memory_banksize(); |
Tom Rini | edcfdbd | 2016-12-09 07:56:54 -0500 | [diff] [blame] | 112 | } |
Michal Simek | f4780a7 | 2016-04-01 15:56:33 +0200 | [diff] [blame] | 113 | |
Tom Rini | edcfdbd | 2016-12-09 07:56:54 -0500 | [diff] [blame] | 114 | int dram_init(void) |
| 115 | { |
Siva Durga Prasad Paladugu | b3d55ea | 2018-07-16 15:56:11 +0530 | [diff] [blame] | 116 | if (fdtdec_setup_mem_size_base() != 0) |
Nathan Rossi | 58ea0d8 | 2016-12-19 00:03:34 +1000 | [diff] [blame] | 117 | return -EINVAL; |
Tom Rini | edcfdbd | 2016-12-09 07:56:54 -0500 | [diff] [blame] | 118 | |
| 119 | zynq_ddrc_init(); |
| 120 | |
| 121 | return 0; |
Michal Simek | f4780a7 | 2016-04-01 15:56:33 +0200 | [diff] [blame] | 122 | } |
Michal Simek | f4780a7 | 2016-04-01 15:56:33 +0200 | [diff] [blame] | 123 | #else |
| 124 | int dram_init(void) |
| 125 | { |
Michal Simek | 1b84621 | 2018-04-11 16:12:28 +0200 | [diff] [blame] | 126 | gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, |
| 127 | CONFIG_SYS_SDRAM_SIZE); |
Michal Simek | f4780a7 | 2016-04-01 15:56:33 +0200 | [diff] [blame] | 128 | |
Michal Simek | f5ff7bc | 2013-06-17 14:37:01 +0200 | [diff] [blame] | 129 | zynq_ddrc_init(); |
| 130 | |
Michal Simek | af482d5 | 2012-09-28 09:56:37 +0000 | [diff] [blame] | 131 | return 0; |
| 132 | } |
Michal Simek | f4780a7 | 2016-04-01 15:56:33 +0200 | [diff] [blame] | 133 | #endif |
Ashok Reddy Soma | 909546d | 2021-02-23 08:07:45 -0700 | [diff] [blame] | 134 | |
| 135 | enum env_location env_get_location(enum env_operation op, int prio) |
| 136 | { |
| 137 | u32 bootmode = zynq_slcr_get_boot_mode() & ZYNQ_BM_MASK; |
| 138 | |
| 139 | if (prio) |
| 140 | return ENVL_UNKNOWN; |
| 141 | |
| 142 | switch (bootmode) { |
| 143 | case ZYNQ_BM_SD: |
| 144 | if (IS_ENABLED(CONFIG_ENV_IS_IN_FAT)) |
| 145 | return ENVL_FAT; |
| 146 | if (IS_ENABLED(CONFIG_ENV_IS_IN_EXT4)) |
| 147 | return ENVL_EXT4; |
Mike Looijmans | 682cf08 | 2021-07-02 10:28:36 +0200 | [diff] [blame] | 148 | return ENVL_NOWHERE; |
Ashok Reddy Soma | 909546d | 2021-02-23 08:07:45 -0700 | [diff] [blame] | 149 | case ZYNQ_BM_NAND: |
| 150 | if (IS_ENABLED(CONFIG_ENV_IS_IN_NAND)) |
| 151 | return ENVL_NAND; |
| 152 | if (IS_ENABLED(CONFIG_ENV_IS_IN_UBI)) |
| 153 | return ENVL_UBI; |
Mike Looijmans | 682cf08 | 2021-07-02 10:28:36 +0200 | [diff] [blame] | 154 | return ENVL_NOWHERE; |
Ashok Reddy Soma | 909546d | 2021-02-23 08:07:45 -0700 | [diff] [blame] | 155 | case ZYNQ_BM_NOR: |
| 156 | case ZYNQ_BM_QSPI: |
| 157 | if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH)) |
| 158 | return ENVL_SPI_FLASH; |
Mike Looijmans | 682cf08 | 2021-07-02 10:28:36 +0200 | [diff] [blame] | 159 | return ENVL_NOWHERE; |
Ashok Reddy Soma | 909546d | 2021-02-23 08:07:45 -0700 | [diff] [blame] | 160 | case ZYNQ_BM_JTAG: |
| 161 | default: |
| 162 | return ENVL_NOWHERE; |
| 163 | } |
| 164 | } |
Michal Simek | 2a7d952 | 2021-08-27 12:53:32 +0200 | [diff] [blame] | 165 | |
| 166 | #if defined(CONFIG_SET_DFU_ALT_INFO) |
| 167 | |
| 168 | #define DFU_ALT_BUF_LEN SZ_1K |
| 169 | |
| 170 | void set_dfu_alt_info(char *interface, char *devstr) |
| 171 | { |
| 172 | ALLOC_CACHE_ALIGN_BUFFER(char, buf, DFU_ALT_BUF_LEN); |
| 173 | |
Michal Simek | f0d6f46 | 2022-08-09 16:32:52 +0200 | [diff] [blame] | 174 | if (env_get("dfu_alt_info")) |
Michal Simek | 2a7d952 | 2021-08-27 12:53:32 +0200 | [diff] [blame] | 175 | return; |
| 176 | |
| 177 | memset(buf, 0, sizeof(buf)); |
| 178 | |
| 179 | switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) { |
| 180 | case ZYNQ_BM_SD: |
| 181 | snprintf(buf, DFU_ALT_BUF_LEN, |
Michal Simek | 3e09d19 | 2022-08-09 16:32:54 +0200 | [diff] [blame] | 182 | "mmc 0=boot.bin fat 0 1;" |
Michal Simek | ca1b5d0 | 2022-08-09 16:32:53 +0200 | [diff] [blame] | 183 | "%s fat 0 1", CONFIG_SPL_FS_LOAD_PAYLOAD_NAME); |
Michal Simek | 2a7d952 | 2021-08-27 12:53:32 +0200 | [diff] [blame] | 184 | break; |
| 185 | case ZYNQ_BM_QSPI: |
| 186 | snprintf(buf, DFU_ALT_BUF_LEN, |
| 187 | "sf 0:0=boot.bin raw 0 0x1500000;" |
Michal Simek | ca1b5d0 | 2022-08-09 16:32:53 +0200 | [diff] [blame] | 188 | "%s raw 0x%x 0x500000", |
| 189 | CONFIG_SPL_FS_LOAD_PAYLOAD_NAME, |
Michal Simek | 2a7d952 | 2021-08-27 12:53:32 +0200 | [diff] [blame] | 190 | CONFIG_SYS_SPI_U_BOOT_OFFS); |
| 191 | break; |
| 192 | default: |
| 193 | return; |
| 194 | } |
| 195 | |
| 196 | env_set("dfu_alt_info", buf); |
| 197 | puts("DFU alt info setting: done\n"); |
| 198 | } |
| 199 | #endif |