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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Michal Simekaf482d52012-09-28 09:56:37 +00002/*
3 * (C) Copyright 2012 Michal Simek <monstr@monstr.eu>
Michal Simek98d0f1f2018-01-17 07:37:47 +01004 * (C) Copyright 2013 - 2018 Xilinx, Inc.
Michal Simekaf482d52012-09-28 09:56:37 +00005 */
6
7#include <common.h>
Simon Glassa7b51302019-11-14 12:57:46 -07008#include <init.h>
Michal Simek309ef802018-02-21 17:04:28 +01009#include <dm/uclass.h>
Simon Glass5e6201b2019-08-01 09:46:51 -060010#include <env.h>
Michal Simek65ef52f2014-02-24 11:16:32 +010011#include <fdtdec.h>
Michal Simek0f796702014-04-25 13:51:17 +020012#include <fpga.h>
Siva Durga Prasad Paladugubd75bc12019-01-25 17:06:06 +053013#include <malloc.h>
Michal Simek0f796702014-04-25 13:51:17 +020014#include <mmc.h>
Michal Simekc07b2252018-06-08 13:45:14 +020015#include <watchdog.h>
Michal Simek309ef802018-02-21 17:04:28 +010016#include <wdt.h>
Michal Simek15d654c2013-04-22 15:43:02 +020017#include <zynqpl.h>
Michal Simek242192b2013-04-12 16:33:08 +020018#include <asm/arch/hardware.h>
19#include <asm/arch/sys_proto.h>
Michal Simekaf482d52012-09-28 09:56:37 +000020
21DECLARE_GLOBAL_DATA_PTR;
22
23int board_init(void)
24{
Michal Simekaf482d52012-09-28 09:56:37 +000025 return 0;
26}
27
Jagannadha Sutradharudu Teki11704c22014-01-09 01:48:21 +053028int board_late_init(void)
29{
Siva Durga Prasad Paladugubd75bc12019-01-25 17:06:06 +053030 int env_targets_len = 0;
31 const char *mode;
32 char *new_targets;
33 char *env_targets;
34
Jagannadha Sutradharudu Teki11704c22014-01-09 01:48:21 +053035 switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
Michal Simek19356712016-12-16 13:16:14 +010036 case ZYNQ_BM_QSPI:
Siva Durga Prasad Paladugubd75bc12019-01-25 17:06:06 +053037 mode = "qspi";
Simon Glass6a38e412017-08-03 12:22:09 -060038 env_set("modeboot", "qspiboot");
Michal Simek19356712016-12-16 13:16:14 +010039 break;
40 case ZYNQ_BM_NAND:
Siva Durga Prasad Paladugubd75bc12019-01-25 17:06:06 +053041 mode = "nand";
Simon Glass6a38e412017-08-03 12:22:09 -060042 env_set("modeboot", "nandboot");
Michal Simek19356712016-12-16 13:16:14 +010043 break;
Jagannadha Sutradharudu Teki11704c22014-01-09 01:48:21 +053044 case ZYNQ_BM_NOR:
Siva Durga Prasad Paladugubd75bc12019-01-25 17:06:06 +053045 mode = "nor";
Simon Glass6a38e412017-08-03 12:22:09 -060046 env_set("modeboot", "norboot");
Jagannadha Sutradharudu Teki11704c22014-01-09 01:48:21 +053047 break;
48 case ZYNQ_BM_SD:
Michal Simek9541d0b2019-09-11 12:51:49 +020049 mode = "mmc0";
Simon Glass6a38e412017-08-03 12:22:09 -060050 env_set("modeboot", "sdboot");
Jagannadha Sutradharudu Teki11704c22014-01-09 01:48:21 +053051 break;
52 case ZYNQ_BM_JTAG:
T Karthik Reddy6c28c292019-11-13 21:13:44 -070053 mode = "jtag pxe dhcp";
Simon Glass6a38e412017-08-03 12:22:09 -060054 env_set("modeboot", "jtagboot");
Jagannadha Sutradharudu Teki11704c22014-01-09 01:48:21 +053055 break;
56 default:
Siva Durga Prasad Paladugubd75bc12019-01-25 17:06:06 +053057 mode = "";
Simon Glass6a38e412017-08-03 12:22:09 -060058 env_set("modeboot", "");
Jagannadha Sutradharudu Teki11704c22014-01-09 01:48:21 +053059 break;
60 }
61
Siva Durga Prasad Paladugubd75bc12019-01-25 17:06:06 +053062 /*
63 * One terminating char + one byte for space between mode
64 * and default boot_targets
65 */
66 env_targets = env_get("boot_targets");
67 if (env_targets)
68 env_targets_len = strlen(env_targets);
69
70 new_targets = calloc(1, strlen(mode) + env_targets_len + 2);
71 if (!new_targets)
72 return -ENOMEM;
73
74 sprintf(new_targets, "%s %s", mode,
75 env_targets ? env_targets : "");
76
77 env_set("boot_targets", new_targets);
78
T Karthik Reddy5fa6c1e2019-12-18 03:34:41 -070079 env_set_hex("script_offset_f", CONFIG_BOOT_SCRIPT_OFFSET);
80
Jagannadha Sutradharudu Teki11704c22014-01-09 01:48:21 +053081 return 0;
82}
Michal Simekaf482d52012-09-28 09:56:37 +000083
Michal Simekf4780a72016-04-01 15:56:33 +020084#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
Simon Glass2f949c32017-03-31 08:40:32 -060085int dram_init_banksize(void)
Nathan Rossic12892b2016-12-04 19:33:22 +100086{
Michal Simekd5b7de62017-11-03 15:25:51 +010087 return fdtdec_setup_memory_banksize();
Tom Riniedcfdbd2016-12-09 07:56:54 -050088}
Michal Simekf4780a72016-04-01 15:56:33 +020089
Tom Riniedcfdbd2016-12-09 07:56:54 -050090int dram_init(void)
91{
Siva Durga Prasad Paladugub3d55ea2018-07-16 15:56:11 +053092 if (fdtdec_setup_mem_size_base() != 0)
Nathan Rossi58ea0d82016-12-19 00:03:34 +100093 return -EINVAL;
Tom Riniedcfdbd2016-12-09 07:56:54 -050094
95 zynq_ddrc_init();
96
97 return 0;
Michal Simekf4780a72016-04-01 15:56:33 +020098}
Michal Simekf4780a72016-04-01 15:56:33 +020099#else
100int dram_init(void)
101{
Michal Simek1b846212018-04-11 16:12:28 +0200102 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
103 CONFIG_SYS_SDRAM_SIZE);
Michal Simekf4780a72016-04-01 15:56:33 +0200104
Michal Simekf5ff7bc2013-06-17 14:37:01 +0200105 zynq_ddrc_init();
106
Michal Simekaf482d52012-09-28 09:56:37 +0000107 return 0;
108}
Michal Simekf4780a72016-04-01 15:56:33 +0200109#endif