Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Michal Simek | af482d5 | 2012-09-28 09:56:37 +0000 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2012 Michal Simek <monstr@monstr.eu> |
Michal Simek | 98d0f1f | 2018-01-17 07:37:47 +0100 | [diff] [blame] | 4 | * (C) Copyright 2013 - 2018 Xilinx, Inc. |
Michal Simek | af482d5 | 2012-09-28 09:56:37 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #include <common.h> |
Simon Glass | a7b5130 | 2019-11-14 12:57:46 -0700 | [diff] [blame] | 8 | #include <init.h> |
Michal Simek | 309ef80 | 2018-02-21 17:04:28 +0100 | [diff] [blame] | 9 | #include <dm/uclass.h> |
Simon Glass | 5e6201b | 2019-08-01 09:46:51 -0600 | [diff] [blame] | 10 | #include <env.h> |
Michal Simek | 65ef52f | 2014-02-24 11:16:32 +0100 | [diff] [blame] | 11 | #include <fdtdec.h> |
Michal Simek | 0f79670 | 2014-04-25 13:51:17 +0200 | [diff] [blame] | 12 | #include <fpga.h> |
Siva Durga Prasad Paladugu | bd75bc1 | 2019-01-25 17:06:06 +0530 | [diff] [blame] | 13 | #include <malloc.h> |
Michal Simek | 0f79670 | 2014-04-25 13:51:17 +0200 | [diff] [blame] | 14 | #include <mmc.h> |
Michal Simek | c07b225 | 2018-06-08 13:45:14 +0200 | [diff] [blame] | 15 | #include <watchdog.h> |
Michal Simek | 309ef80 | 2018-02-21 17:04:28 +0100 | [diff] [blame] | 16 | #include <wdt.h> |
Michal Simek | 15d654c | 2013-04-22 15:43:02 +0200 | [diff] [blame] | 17 | #include <zynqpl.h> |
Michal Simek | 242192b | 2013-04-12 16:33:08 +0200 | [diff] [blame] | 18 | #include <asm/arch/hardware.h> |
| 19 | #include <asm/arch/sys_proto.h> |
Michal Simek | af482d5 | 2012-09-28 09:56:37 +0000 | [diff] [blame] | 20 | |
| 21 | DECLARE_GLOBAL_DATA_PTR; |
| 22 | |
| 23 | int board_init(void) |
| 24 | { |
Michal Simek | af482d5 | 2012-09-28 09:56:37 +0000 | [diff] [blame] | 25 | return 0; |
| 26 | } |
| 27 | |
Jagannadha Sutradharudu Teki | 11704c2 | 2014-01-09 01:48:21 +0530 | [diff] [blame] | 28 | int board_late_init(void) |
| 29 | { |
Siva Durga Prasad Paladugu | bd75bc1 | 2019-01-25 17:06:06 +0530 | [diff] [blame] | 30 | int env_targets_len = 0; |
| 31 | const char *mode; |
| 32 | char *new_targets; |
| 33 | char *env_targets; |
| 34 | |
Jagannadha Sutradharudu Teki | 11704c2 | 2014-01-09 01:48:21 +0530 | [diff] [blame] | 35 | switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) { |
Michal Simek | 1935671 | 2016-12-16 13:16:14 +0100 | [diff] [blame] | 36 | case ZYNQ_BM_QSPI: |
Siva Durga Prasad Paladugu | bd75bc1 | 2019-01-25 17:06:06 +0530 | [diff] [blame] | 37 | mode = "qspi"; |
Simon Glass | 6a38e41 | 2017-08-03 12:22:09 -0600 | [diff] [blame] | 38 | env_set("modeboot", "qspiboot"); |
Michal Simek | 1935671 | 2016-12-16 13:16:14 +0100 | [diff] [blame] | 39 | break; |
| 40 | case ZYNQ_BM_NAND: |
Siva Durga Prasad Paladugu | bd75bc1 | 2019-01-25 17:06:06 +0530 | [diff] [blame] | 41 | mode = "nand"; |
Simon Glass | 6a38e41 | 2017-08-03 12:22:09 -0600 | [diff] [blame] | 42 | env_set("modeboot", "nandboot"); |
Michal Simek | 1935671 | 2016-12-16 13:16:14 +0100 | [diff] [blame] | 43 | break; |
Jagannadha Sutradharudu Teki | 11704c2 | 2014-01-09 01:48:21 +0530 | [diff] [blame] | 44 | case ZYNQ_BM_NOR: |
Siva Durga Prasad Paladugu | bd75bc1 | 2019-01-25 17:06:06 +0530 | [diff] [blame] | 45 | mode = "nor"; |
Simon Glass | 6a38e41 | 2017-08-03 12:22:09 -0600 | [diff] [blame] | 46 | env_set("modeboot", "norboot"); |
Jagannadha Sutradharudu Teki | 11704c2 | 2014-01-09 01:48:21 +0530 | [diff] [blame] | 47 | break; |
| 48 | case ZYNQ_BM_SD: |
Michal Simek | 9541d0b | 2019-09-11 12:51:49 +0200 | [diff] [blame] | 49 | mode = "mmc0"; |
Simon Glass | 6a38e41 | 2017-08-03 12:22:09 -0600 | [diff] [blame] | 50 | env_set("modeboot", "sdboot"); |
Jagannadha Sutradharudu Teki | 11704c2 | 2014-01-09 01:48:21 +0530 | [diff] [blame] | 51 | break; |
| 52 | case ZYNQ_BM_JTAG: |
T Karthik Reddy | 6c28c29 | 2019-11-13 21:13:44 -0700 | [diff] [blame^] | 53 | mode = "jtag pxe dhcp"; |
Simon Glass | 6a38e41 | 2017-08-03 12:22:09 -0600 | [diff] [blame] | 54 | env_set("modeboot", "jtagboot"); |
Jagannadha Sutradharudu Teki | 11704c2 | 2014-01-09 01:48:21 +0530 | [diff] [blame] | 55 | break; |
| 56 | default: |
Siva Durga Prasad Paladugu | bd75bc1 | 2019-01-25 17:06:06 +0530 | [diff] [blame] | 57 | mode = ""; |
Simon Glass | 6a38e41 | 2017-08-03 12:22:09 -0600 | [diff] [blame] | 58 | env_set("modeboot", ""); |
Jagannadha Sutradharudu Teki | 11704c2 | 2014-01-09 01:48:21 +0530 | [diff] [blame] | 59 | break; |
| 60 | } |
| 61 | |
Siva Durga Prasad Paladugu | bd75bc1 | 2019-01-25 17:06:06 +0530 | [diff] [blame] | 62 | /* |
| 63 | * One terminating char + one byte for space between mode |
| 64 | * and default boot_targets |
| 65 | */ |
| 66 | env_targets = env_get("boot_targets"); |
| 67 | if (env_targets) |
| 68 | env_targets_len = strlen(env_targets); |
| 69 | |
| 70 | new_targets = calloc(1, strlen(mode) + env_targets_len + 2); |
| 71 | if (!new_targets) |
| 72 | return -ENOMEM; |
| 73 | |
| 74 | sprintf(new_targets, "%s %s", mode, |
| 75 | env_targets ? env_targets : ""); |
| 76 | |
| 77 | env_set("boot_targets", new_targets); |
| 78 | |
T Karthik Reddy | 5fa6c1e | 2019-12-18 03:34:41 -0700 | [diff] [blame] | 79 | env_set_hex("script_offset_f", CONFIG_BOOT_SCRIPT_OFFSET); |
| 80 | |
Jagannadha Sutradharudu Teki | 11704c2 | 2014-01-09 01:48:21 +0530 | [diff] [blame] | 81 | return 0; |
| 82 | } |
Michal Simek | af482d5 | 2012-09-28 09:56:37 +0000 | [diff] [blame] | 83 | |
Michal Simek | f4780a7 | 2016-04-01 15:56:33 +0200 | [diff] [blame] | 84 | #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE) |
Simon Glass | 2f949c3 | 2017-03-31 08:40:32 -0600 | [diff] [blame] | 85 | int dram_init_banksize(void) |
Nathan Rossi | c12892b | 2016-12-04 19:33:22 +1000 | [diff] [blame] | 86 | { |
Michal Simek | d5b7de6 | 2017-11-03 15:25:51 +0100 | [diff] [blame] | 87 | return fdtdec_setup_memory_banksize(); |
Tom Rini | edcfdbd | 2016-12-09 07:56:54 -0500 | [diff] [blame] | 88 | } |
Michal Simek | f4780a7 | 2016-04-01 15:56:33 +0200 | [diff] [blame] | 89 | |
Tom Rini | edcfdbd | 2016-12-09 07:56:54 -0500 | [diff] [blame] | 90 | int dram_init(void) |
| 91 | { |
Siva Durga Prasad Paladugu | b3d55ea | 2018-07-16 15:56:11 +0530 | [diff] [blame] | 92 | if (fdtdec_setup_mem_size_base() != 0) |
Nathan Rossi | 58ea0d8 | 2016-12-19 00:03:34 +1000 | [diff] [blame] | 93 | return -EINVAL; |
Tom Rini | edcfdbd | 2016-12-09 07:56:54 -0500 | [diff] [blame] | 94 | |
| 95 | zynq_ddrc_init(); |
| 96 | |
| 97 | return 0; |
Michal Simek | f4780a7 | 2016-04-01 15:56:33 +0200 | [diff] [blame] | 98 | } |
Michal Simek | f4780a7 | 2016-04-01 15:56:33 +0200 | [diff] [blame] | 99 | #else |
| 100 | int dram_init(void) |
| 101 | { |
Michal Simek | 1b84621 | 2018-04-11 16:12:28 +0200 | [diff] [blame] | 102 | gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, |
| 103 | CONFIG_SYS_SDRAM_SIZE); |
Michal Simek | f4780a7 | 2016-04-01 15:56:33 +0200 | [diff] [blame] | 104 | |
Michal Simek | f5ff7bc | 2013-06-17 14:37:01 +0200 | [diff] [blame] | 105 | zynq_ddrc_init(); |
| 106 | |
Michal Simek | af482d5 | 2012-09-28 09:56:37 +0000 | [diff] [blame] | 107 | return 0; |
| 108 | } |
Michal Simek | f4780a7 | 2016-04-01 15:56:33 +0200 | [diff] [blame] | 109 | #endif |