blob: 7ac069aaafdf26685ae554120b742302ddcd3abb [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Michal Simekaf482d52012-09-28 09:56:37 +00002/*
3 * (C) Copyright 2012 Michal Simek <monstr@monstr.eu>
Michal Simek98d0f1f2018-01-17 07:37:47 +01004 * (C) Copyright 2013 - 2018 Xilinx, Inc.
Michal Simekaf482d52012-09-28 09:56:37 +00005 */
6
7#include <common.h>
Simon Glassa7b51302019-11-14 12:57:46 -07008#include <init.h>
Michal Simekbab07b62020-07-28 12:45:47 +02009#include <log.h>
Michal Simek309ef802018-02-21 17:04:28 +010010#include <dm/uclass.h>
Simon Glass5e6201b2019-08-01 09:46:51 -060011#include <env.h>
Michal Simek65ef52f2014-02-24 11:16:32 +010012#include <fdtdec.h>
Michal Simek0f796702014-04-25 13:51:17 +020013#include <fpga.h>
Siva Durga Prasad Paladugubd75bc12019-01-25 17:06:06 +053014#include <malloc.h>
Michal Simek0f796702014-04-25 13:51:17 +020015#include <mmc.h>
Michal Simekc07b2252018-06-08 13:45:14 +020016#include <watchdog.h>
Michal Simek309ef802018-02-21 17:04:28 +010017#include <wdt.h>
Michal Simek15d654c2013-04-22 15:43:02 +020018#include <zynqpl.h>
Michal Simek242192b2013-04-12 16:33:08 +020019#include <asm/arch/hardware.h>
20#include <asm/arch/sys_proto.h>
Michal Simek705d44a2020-03-31 12:39:37 +020021#include "../common/board.h"
Michal Simekaf482d52012-09-28 09:56:37 +000022
23DECLARE_GLOBAL_DATA_PTR;
24
25int board_init(void)
26{
Michal Simekaf482d52012-09-28 09:56:37 +000027 return 0;
28}
29
Jagannadha Sutradharudu Teki11704c22014-01-09 01:48:21 +053030int board_late_init(void)
31{
Siva Durga Prasad Paladugubd75bc12019-01-25 17:06:06 +053032 int env_targets_len = 0;
33 const char *mode;
34 char *new_targets;
35 char *env_targets;
36
Michal Simekbab07b62020-07-28 12:45:47 +020037 if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
38 debug("Saved variables - Skipping\n");
39 return 0;
40 }
41
42 if (!CONFIG_IS_ENABLED(ENV_VARS_UBOOT_RUNTIME_CONFIG))
43 return 0;
44
Jagannadha Sutradharudu Teki11704c22014-01-09 01:48:21 +053045 switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
Michal Simek19356712016-12-16 13:16:14 +010046 case ZYNQ_BM_QSPI:
Siva Durga Prasad Paladugubd75bc12019-01-25 17:06:06 +053047 mode = "qspi";
Simon Glass6a38e412017-08-03 12:22:09 -060048 env_set("modeboot", "qspiboot");
Michal Simek19356712016-12-16 13:16:14 +010049 break;
50 case ZYNQ_BM_NAND:
Siva Durga Prasad Paladugubd75bc12019-01-25 17:06:06 +053051 mode = "nand";
Simon Glass6a38e412017-08-03 12:22:09 -060052 env_set("modeboot", "nandboot");
Michal Simek19356712016-12-16 13:16:14 +010053 break;
Jagannadha Sutradharudu Teki11704c22014-01-09 01:48:21 +053054 case ZYNQ_BM_NOR:
Siva Durga Prasad Paladugubd75bc12019-01-25 17:06:06 +053055 mode = "nor";
Simon Glass6a38e412017-08-03 12:22:09 -060056 env_set("modeboot", "norboot");
Jagannadha Sutradharudu Teki11704c22014-01-09 01:48:21 +053057 break;
58 case ZYNQ_BM_SD:
Michal Simek9541d0b2019-09-11 12:51:49 +020059 mode = "mmc0";
Simon Glass6a38e412017-08-03 12:22:09 -060060 env_set("modeboot", "sdboot");
Jagannadha Sutradharudu Teki11704c22014-01-09 01:48:21 +053061 break;
62 case ZYNQ_BM_JTAG:
T Karthik Reddy6c28c292019-11-13 21:13:44 -070063 mode = "jtag pxe dhcp";
Simon Glass6a38e412017-08-03 12:22:09 -060064 env_set("modeboot", "jtagboot");
Jagannadha Sutradharudu Teki11704c22014-01-09 01:48:21 +053065 break;
66 default:
Siva Durga Prasad Paladugubd75bc12019-01-25 17:06:06 +053067 mode = "";
Simon Glass6a38e412017-08-03 12:22:09 -060068 env_set("modeboot", "");
Jagannadha Sutradharudu Teki11704c22014-01-09 01:48:21 +053069 break;
70 }
71
Siva Durga Prasad Paladugubd75bc12019-01-25 17:06:06 +053072 /*
73 * One terminating char + one byte for space between mode
74 * and default boot_targets
75 */
76 env_targets = env_get("boot_targets");
77 if (env_targets)
78 env_targets_len = strlen(env_targets);
79
80 new_targets = calloc(1, strlen(mode) + env_targets_len + 2);
81 if (!new_targets)
82 return -ENOMEM;
83
84 sprintf(new_targets, "%s %s", mode,
85 env_targets ? env_targets : "");
86
87 env_set("boot_targets", new_targets);
88
Michal Simek705d44a2020-03-31 12:39:37 +020089 return board_late_init_xilinx();
Jagannadha Sutradharudu Teki11704c22014-01-09 01:48:21 +053090}
Michal Simekaf482d52012-09-28 09:56:37 +000091
Michal Simekf4780a72016-04-01 15:56:33 +020092#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
Simon Glass2f949c32017-03-31 08:40:32 -060093int dram_init_banksize(void)
Nathan Rossic12892b2016-12-04 19:33:22 +100094{
Michal Simekd5b7de62017-11-03 15:25:51 +010095 return fdtdec_setup_memory_banksize();
Tom Riniedcfdbd2016-12-09 07:56:54 -050096}
Michal Simekf4780a72016-04-01 15:56:33 +020097
Tom Riniedcfdbd2016-12-09 07:56:54 -050098int dram_init(void)
99{
Siva Durga Prasad Paladugub3d55ea2018-07-16 15:56:11 +0530100 if (fdtdec_setup_mem_size_base() != 0)
Nathan Rossi58ea0d82016-12-19 00:03:34 +1000101 return -EINVAL;
Tom Riniedcfdbd2016-12-09 07:56:54 -0500102
103 zynq_ddrc_init();
104
105 return 0;
Michal Simekf4780a72016-04-01 15:56:33 +0200106}
Michal Simekf4780a72016-04-01 15:56:33 +0200107#else
108int dram_init(void)
109{
Michal Simek1b846212018-04-11 16:12:28 +0200110 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
111 CONFIG_SYS_SDRAM_SIZE);
Michal Simekf4780a72016-04-01 15:56:33 +0200112
Michal Simekf5ff7bc2013-06-17 14:37:01 +0200113 zynq_ddrc_init();
114
Michal Simekaf482d52012-09-28 09:56:37 +0000115 return 0;
116}
Michal Simekf4780a72016-04-01 15:56:33 +0200117#endif