Steve Sakoman | 1ad2158 | 2010-06-08 13:07:46 -0700 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2010 |
| 3 | * Texas Instruments, <www.ti.com> |
| 4 | * |
| 5 | * Authors: |
| 6 | * Aneesh V <aneesh@ti.com> |
Sricharan | 9310ff7 | 2011-11-15 09:49:55 -0500 | [diff] [blame] | 7 | * Sricharan R <r.sricharan@ti.com> |
Steve Sakoman | 1ad2158 | 2010-06-08 13:07:46 -0700 | [diff] [blame] | 8 | * |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 9 | * SPDX-License-Identifier: GPL-2.0+ |
Steve Sakoman | 1ad2158 | 2010-06-08 13:07:46 -0700 | [diff] [blame] | 10 | */ |
| 11 | |
Sricharan | 9310ff7 | 2011-11-15 09:49:55 -0500 | [diff] [blame] | 12 | #ifndef _OMAP5_H_ |
| 13 | #define _OMAP5_H_ |
Steve Sakoman | 1ad2158 | 2010-06-08 13:07:46 -0700 | [diff] [blame] | 14 | |
| 15 | #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) |
| 16 | #include <asm/types.h> |
| 17 | #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ |
| 18 | |
Tom Rini | cfff4aa | 2016-08-26 13:30:43 -0400 | [diff] [blame] | 19 | #include <linux/sizes.h> |
| 20 | |
Steve Sakoman | 1ad2158 | 2010-06-08 13:07:46 -0700 | [diff] [blame] | 21 | /* |
| 22 | * L4 Peripherals - L4 Wakeup and L4 Core now |
| 23 | */ |
Sricharan | 9310ff7 | 2011-11-15 09:49:55 -0500 | [diff] [blame] | 24 | #define OMAP54XX_L4_CORE_BASE 0x4A000000 |
| 25 | #define OMAP54XX_L4_WKUP_BASE 0x4Ae00000 |
| 26 | #define OMAP54XX_L4_PER_BASE 0x48000000 |
Steve Sakoman | 1ad2158 | 2010-06-08 13:07:46 -0700 | [diff] [blame] | 27 | |
Lokesh Vutla | bd1f0df | 2013-05-30 03:19:28 +0000 | [diff] [blame] | 28 | /* CONTROL ID CODE */ |
| 29 | #define CONTROL_CORE_ID_CODE 0x4A002204 |
| 30 | #define CONTROL_WKUP_ID_CODE 0x4AE0C204 |
Steve Sakoman | 1ad2158 | 2010-06-08 13:07:46 -0700 | [diff] [blame] | 31 | |
Nishanth Menon | 813fe9d | 2016-11-29 15:22:00 +0530 | [diff] [blame] | 32 | #if defined(CONFIG_DRA7XX) |
Lokesh Vutla | bd1f0df | 2013-05-30 03:19:28 +0000 | [diff] [blame] | 33 | #define CONTROL_ID_CODE CONTROL_WKUP_ID_CODE |
| 34 | #else |
| 35 | #define CONTROL_ID_CODE CONTROL_CORE_ID_CODE |
| 36 | #endif |
Aneesh V | 162ced3 | 2011-07-21 09:10:04 -0400 | [diff] [blame] | 37 | |
Nishanth Menon | 813fe9d | 2016-11-29 15:22:00 +0530 | [diff] [blame] | 38 | #if defined(CONFIG_DRA7XX) |
Kishon Vijay Abraham I | ce61fd7 | 2015-02-23 18:40:19 +0530 | [diff] [blame] | 39 | #define DRA7_USB_OTG_SS1_BASE 0x48890000 |
| 40 | #define DRA7_USB_OTG_SS1_GLUE_BASE 0x48880000 |
| 41 | #define DRA7_USB3_PHY1_PLL_CTRL 0x4A084C00 |
| 42 | #define DRA7_USB3_PHY1_POWER 0x4A002370 |
| 43 | #define DRA7_USB2_PHY1_POWER 0x4A002300 |
| 44 | |
| 45 | #define DRA7_USB_OTG_SS2_BASE 0x488D0000 |
| 46 | #define DRA7_USB_OTG_SS2_GLUE_BASE 0x488C0000 |
| 47 | #define DRA7_USB2_PHY2_POWER 0x4A002E74 |
Kishon Vijay Abraham I | 5a3e062 | 2015-08-19 14:13:20 +0530 | [diff] [blame] | 48 | #else |
| 49 | #define OMAP5XX_USB_OTG_SS_BASE 0x4A030000 |
| 50 | #define OMAP5XX_USB_OTG_SS_GLUE_BASE 0x4A020000 |
| 51 | #define OMAP5XX_USB3_PHY_PLL_CTRL 0x4A084C00 |
| 52 | #define OMAP5XX_USB3_PHY_POWER 0x4A002370 |
| 53 | #define OMAP5XX_USB2_PHY_POWER 0x4A002300 |
Kishon Vijay Abraham I | ce61fd7 | 2015-02-23 18:40:19 +0530 | [diff] [blame] | 54 | #endif |
| 55 | |
Sricharan | 9310ff7 | 2011-11-15 09:49:55 -0500 | [diff] [blame] | 56 | /* To be verified */ |
Lokesh Vutla | 20507ab | 2012-05-22 00:03:22 +0000 | [diff] [blame] | 57 | #define OMAP5430_CONTROL_ID_CODE_ES1_0 0x0B94202F |
SRICHARAN R | cf85056 | 2013-02-12 01:33:41 +0000 | [diff] [blame] | 58 | #define OMAP5430_CONTROL_ID_CODE_ES2_0 0x1B94202F |
Lokesh Vutla | 20507ab | 2012-05-22 00:03:22 +0000 | [diff] [blame] | 59 | #define OMAP5432_CONTROL_ID_CODE_ES1_0 0x0B99802F |
SRICHARAN R | cf85056 | 2013-02-12 01:33:41 +0000 | [diff] [blame] | 60 | #define OMAP5432_CONTROL_ID_CODE_ES2_0 0x1B99802F |
Praneeth Bajjuri | 9b21ff4 | 2017-08-21 12:50:52 +0530 | [diff] [blame] | 61 | #define DRA762_CONTROL_ID_CODE_ES1_0 0x0BB5002F |
Lokesh Vutla | 43c296f | 2013-02-12 21:29:03 +0000 | [diff] [blame] | 62 | #define DRA752_CONTROL_ID_CODE_ES1_0 0x0B99002F |
Nishanth Menon | 60475ff | 2014-01-14 10:54:42 -0600 | [diff] [blame] | 63 | #define DRA752_CONTROL_ID_CODE_ES1_1 0x1B99002F |
Nishanth Menon | 4de1668 | 2015-08-13 09:50:58 -0500 | [diff] [blame] | 64 | #define DRA752_CONTROL_ID_CODE_ES2_0 0x2B99002F |
Lokesh Vutla | 7572549 | 2014-05-15 11:08:38 +0530 | [diff] [blame] | 65 | #define DRA722_CONTROL_ID_CODE_ES1_0 0x0B9BC02F |
Ravi Babu | af9af44 | 2016-03-15 18:09:11 -0500 | [diff] [blame] | 66 | #define DRA722_CONTROL_ID_CODE_ES2_0 0x1B9BC02F |
Vishal Mahaveer | 42d25eb | 2017-08-26 16:51:22 -0500 | [diff] [blame] | 67 | #define DRA722_CONTROL_ID_CODE_ES2_1 0x2B9BC02F |
Aneesh V | 162ced3 | 2011-07-21 09:10:04 -0400 | [diff] [blame] | 68 | |
Lokesh Vutla | 69483e6 | 2017-12-29 11:47:51 +0530 | [diff] [blame] | 69 | #define DRA762_ABZ_PACKAGE 0x2 |
| 70 | #define DRA762_ACD_PACKAGE 0x3 |
| 71 | |
Steve Sakoman | 1ad2158 | 2010-06-08 13:07:46 -0700 | [diff] [blame] | 72 | /* UART */ |
Sricharan | 9310ff7 | 2011-11-15 09:49:55 -0500 | [diff] [blame] | 73 | #define UART1_BASE (OMAP54XX_L4_PER_BASE + 0x6a000) |
| 74 | #define UART2_BASE (OMAP54XX_L4_PER_BASE + 0x6c000) |
| 75 | #define UART3_BASE (OMAP54XX_L4_PER_BASE + 0x20000) |
Dmitry Lifshitz | ca96944 | 2014-04-27 13:17:25 +0300 | [diff] [blame] | 76 | #define UART4_BASE (OMAP54XX_L4_PER_BASE + 0x6e000) |
Steve Sakoman | 1ad2158 | 2010-06-08 13:07:46 -0700 | [diff] [blame] | 77 | |
| 78 | /* General Purpose Timers */ |
Sricharan | 9310ff7 | 2011-11-15 09:49:55 -0500 | [diff] [blame] | 79 | #define GPT1_BASE (OMAP54XX_L4_WKUP_BASE + 0x18000) |
| 80 | #define GPT2_BASE (OMAP54XX_L4_PER_BASE + 0x32000) |
| 81 | #define GPT3_BASE (OMAP54XX_L4_PER_BASE + 0x34000) |
Steve Sakoman | 1ad2158 | 2010-06-08 13:07:46 -0700 | [diff] [blame] | 82 | |
| 83 | /* Watchdog Timer2 - MPU watchdog */ |
Sricharan | 9310ff7 | 2011-11-15 09:49:55 -0500 | [diff] [blame] | 84 | #define WDT2_BASE (OMAP54XX_L4_WKUP_BASE + 0x14000) |
Steve Sakoman | 1ad2158 | 2010-06-08 13:07:46 -0700 | [diff] [blame] | 85 | |
Matt Porter | 3074626 | 2013-10-07 15:52:59 +0530 | [diff] [blame] | 86 | /* QSPI */ |
| 87 | #define QSPI_BASE 0x4B300000 |
| 88 | |
Roger Quadros | d50e63d | 2013-11-11 16:56:40 +0200 | [diff] [blame] | 89 | /* SATA */ |
| 90 | #define DWC_AHSATA_BASE 0x4A140000 |
| 91 | |
Steve Sakoman | 1ad2158 | 2010-06-08 13:07:46 -0700 | [diff] [blame] | 92 | /* |
| 93 | * Hardware Register Details |
| 94 | */ |
| 95 | |
| 96 | /* Watchdog Timer */ |
| 97 | #define WD_UNLOCK1 0xAAAA |
| 98 | #define WD_UNLOCK2 0x5555 |
| 99 | |
| 100 | /* GP Timer */ |
| 101 | #define TCLR_ST (0x1 << 0) |
| 102 | #define TCLR_AR (0x1 << 1) |
| 103 | #define TCLR_PRE (0x1 << 5) |
| 104 | |
Aneesh V | b35f7cb | 2011-09-08 11:05:56 -0400 | [diff] [blame] | 105 | /* Control Module */ |
| 106 | #define LDOSRAM_ACTMODE_VSET_IN_MASK (0x1F << 5) |
| 107 | #define LDOSRAM_VOLT_CTRL_OVERRIDE 0x0401040f |
| 108 | #define CONTROL_EFUSE_1_OVERRIDE 0x1C4D0110 |
| 109 | #define CONTROL_EFUSE_2_OVERRIDE 0x00084000 |
| 110 | |
| 111 | /* LPDDR2 IO regs */ |
| 112 | #define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN 0x1C1C1C1C |
| 113 | #define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER 0x9E9E9E9E |
| 114 | #define CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN 0x7C7C7C7C |
| 115 | #define LPDDR2IO_GR10_WD_MASK (3 << 17) |
| 116 | #define CONTROL_LPDDR2IO_3_VAL 0xA0888C00 |
| 117 | |
| 118 | /* CONTROL_EFUSE_2 */ |
| 119 | #define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000 |
| 120 | |
Balaji T K | 8372baf | 2013-06-06 05:04:32 +0000 | [diff] [blame] | 121 | #define SDCARD_BIAS_PWRDNZ (1 << 27) |
Balaji T K | d9cf836 | 2012-03-12 02:25:49 +0000 | [diff] [blame] | 122 | #define SDCARD_PWRDNZ (1 << 26) |
| 123 | #define SDCARD_BIAS_HIZ_MODE (1 << 25) |
Balaji T K | d9cf836 | 2012-03-12 02:25:49 +0000 | [diff] [blame] | 124 | #define SDCARD_PBIASLITE_VMODE (1 << 21) |
Balaji T K | f843d33 | 2011-09-08 06:34:57 +0000 | [diff] [blame] | 125 | |
Steve Sakoman | 1ad2158 | 2010-06-08 13:07:46 -0700 | [diff] [blame] | 126 | #ifndef __ASSEMBLY__ |
| 127 | |
| 128 | struct s32ktimer { |
| 129 | unsigned char res[0x10]; |
| 130 | unsigned int s32k_cr; /* 0x10 */ |
| 131 | }; |
| 132 | |
SRICHARAN R | 36c366f | 2012-03-12 02:25:43 +0000 | [diff] [blame] | 133 | #define DEVICE_TYPE_SHIFT 0x6 |
| 134 | #define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT) |
SRICHARAN R | 36c366f | 2012-03-12 02:25:43 +0000 | [diff] [blame] | 135 | |
SRICHARAN R | 8ec587d | 2012-03-12 02:25:36 +0000 | [diff] [blame] | 136 | /* Output impedance control */ |
| 137 | #define ds_120_ohm 0x0 |
| 138 | #define ds_60_ohm 0x1 |
| 139 | #define ds_45_ohm 0x2 |
| 140 | #define ds_30_ohm 0x3 |
| 141 | #define ds_mask 0x3 |
| 142 | |
| 143 | /* Slew rate control */ |
| 144 | #define sc_slow 0x0 |
| 145 | #define sc_medium 0x1 |
| 146 | #define sc_fast 0x2 |
| 147 | #define sc_na 0x3 |
| 148 | #define sc_mask 0x3 |
| 149 | |
| 150 | /* Target capacitance control */ |
| 151 | #define lb_5_12_pf 0x0 |
| 152 | #define lb_12_25_pf 0x1 |
| 153 | #define lb_25_50_pf 0x2 |
| 154 | #define lb_50_80_pf 0x3 |
| 155 | #define lb_mask 0x3 |
| 156 | |
| 157 | #define usb_i_mask 0x7 |
| 158 | |
| 159 | #define DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN 0x80828082 |
| 160 | #define DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN 0x82828200 |
| 161 | #define DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL 0x8421 |
| 162 | #define DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL 0x8421084 |
| 163 | #define DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL 0x8421000 |
| 164 | |
Lokesh Vutla | ff7b2a9 | 2012-05-22 00:03:23 +0000 | [diff] [blame] | 165 | #define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL 0x7C7C7C6C |
| 166 | #define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL 0x64646464 |
| 167 | #define DDR_IO_0_VREF_CELLS_DDR3_VALUE 0xBAE8C631 |
| 168 | #define DDR_IO_1_VREF_CELLS_DDR3_VALUE 0xBC6318DC |
| 169 | #define DDR_IO_2_VREF_CELLS_DDR3_VALUE 0x0 |
| 170 | |
Lokesh Vutla | 79a9ec7 | 2013-02-12 01:33:44 +0000 | [diff] [blame] | 171 | #define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x7C7C7C7C |
SRICHARAN R | aff6757 | 2013-10-17 16:35:38 +0530 | [diff] [blame] | 172 | #define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x64646464 |
Lokesh Vutla | 79a9ec7 | 2013-02-12 01:33:44 +0000 | [diff] [blame] | 173 | #define DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2 0xBAE8C631 |
SRICHARAN R | aff6757 | 2013-10-17 16:35:38 +0530 | [diff] [blame] | 174 | #define DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2 0xBC6318DC |
Lokesh Vutla | 79a9ec7 | 2013-02-12 01:33:44 +0000 | [diff] [blame] | 175 | #define DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2 0x84210000 |
| 176 | |
SRICHARAN R | 8ec587d | 2012-03-12 02:25:36 +0000 | [diff] [blame] | 177 | #define EFUSE_1 0x45145100 |
| 178 | #define EFUSE_2 0x45145100 |
| 179 | #define EFUSE_3 0x45145100 |
| 180 | #define EFUSE_4 0x45145100 |
Steve Sakoman | 1ad2158 | 2010-06-08 13:07:46 -0700 | [diff] [blame] | 181 | #endif /* __ASSEMBLY__ */ |
| 182 | |
Tom Rini | f787568 | 2013-08-20 08:53:45 -0400 | [diff] [blame] | 183 | /* |
| 184 | * In all cases, the TRM defines the RAM Memory Map for the processor |
| 185 | * and indicates the area for the downloaded image. We use all of that |
| 186 | * space for download and once up and running may use other parts of the |
| 187 | * map for our needs. We set a scratch space that is at the end of the |
| 188 | * OMAP5 download area, but within the DRA7xx download area (as it is |
| 189 | * much larger) and do not, at this time, make use of the additional |
| 190 | * space. |
| 191 | */ |
Nishanth Menon | 813fe9d | 2016-11-29 15:22:00 +0530 | [diff] [blame] | 192 | #if defined(CONFIG_DRA7XX) |
Sricharan R | cdb9619 | 2013-05-30 03:19:35 +0000 | [diff] [blame] | 193 | #define NON_SECURE_SRAM_START 0x40300000 |
| 194 | #define NON_SECURE_SRAM_END 0x40380000 /* Not inclusive */ |
Andrew F. Davis | 4bcc6a5 | 2017-02-15 09:16:53 -0600 | [diff] [blame] | 195 | #define NON_SECURE_SRAM_IMG_END 0x4037C000 |
Sricharan R | cdb9619 | 2013-05-30 03:19:35 +0000 | [diff] [blame] | 196 | #else |
SRICHARAN R | d47786c | 2012-03-12 02:25:41 +0000 | [diff] [blame] | 197 | #define NON_SECURE_SRAM_START 0x40300000 |
Sricharan | 9310ff7 | 2011-11-15 09:49:55 -0500 | [diff] [blame] | 198 | #define NON_SECURE_SRAM_END 0x40320000 /* Not inclusive */ |
Tom Rini | cfff4aa | 2016-08-26 13:30:43 -0400 | [diff] [blame] | 199 | #define NON_SECURE_SRAM_IMG_END 0x4031E000 |
Sricharan R | cdb9619 | 2013-05-30 03:19:35 +0000 | [diff] [blame] | 200 | #endif |
Tom Rini | cfff4aa | 2016-08-26 13:30:43 -0400 | [diff] [blame] | 201 | #define SRAM_SCRATCH_SPACE_ADDR (NON_SECURE_SRAM_IMG_END - SZ_1K) |
Sricharan R | cdb9619 | 2013-05-30 03:19:35 +0000 | [diff] [blame] | 202 | |
Steve Sakoman | 1ad2158 | 2010-06-08 13:07:46 -0700 | [diff] [blame] | 203 | /* base address for indirect vectors (internal boot mode) */ |
Sricharan | 9310ff7 | 2011-11-15 09:49:55 -0500 | [diff] [blame] | 204 | #define SRAM_ROM_VECT_BASE 0x4031F000 |
Sricharan | 9310ff7 | 2011-11-15 09:49:55 -0500 | [diff] [blame] | 205 | |
Lokesh Vutla | 2804963 | 2013-02-12 01:33:45 +0000 | [diff] [blame] | 206 | /* CONTROL_SRCOMP_XXX_SIDE */ |
| 207 | #define OVERRIDE_XS_SHIFT 30 |
| 208 | #define OVERRIDE_XS_MASK (1 << 30) |
| 209 | #define SRCODE_READ_XS_SHIFT 12 |
| 210 | #define SRCODE_READ_XS_MASK (0xff << 12) |
| 211 | #define PWRDWN_XS_SHIFT 11 |
| 212 | #define PWRDWN_XS_MASK (1 << 11) |
| 213 | #define DIVIDE_FACTOR_XS_SHIFT 4 |
| 214 | #define DIVIDE_FACTOR_XS_MASK (0x7f << 4) |
| 215 | #define MULTIPLY_FACTOR_XS_SHIFT 1 |
| 216 | #define MULTIPLY_FACTOR_XS_MASK (0x7 << 1) |
| 217 | #define SRCODE_OVERRIDE_SEL_XS_SHIFT 0 |
| 218 | #define SRCODE_OVERRIDE_SEL_XS_MASK (1 << 0) |
| 219 | |
Andrii Tseglytskyi | 28095da | 2013-05-20 22:42:08 +0000 | [diff] [blame] | 220 | /* ABB settings */ |
| 221 | #define OMAP_ABB_SETTLING_TIME 50 |
| 222 | #define OMAP_ABB_CLOCK_CYCLES 16 |
| 223 | |
| 224 | /* ABB tranxdone mask */ |
| 225 | #define OMAP_ABB_MPU_TXDONE_MASK (0x1 << 7) |
Nishanth Menon | 07be757 | 2016-04-21 14:34:24 -0500 | [diff] [blame] | 226 | #define OMAP_ABB_MM_TXDONE_MASK (0x1 << 31) |
Nishanth Menon | 59b92af | 2016-04-21 14:34:25 -0500 | [diff] [blame] | 227 | #define OMAP_ABB_IVA_TXDONE_MASK (0x1 << 30) |
| 228 | #define OMAP_ABB_EVE_TXDONE_MASK (0x1 << 29) |
| 229 | #define OMAP_ABB_GPU_TXDONE_MASK (0x1 << 28) |
Andrii Tseglytskyi | 28095da | 2013-05-20 22:42:08 +0000 | [diff] [blame] | 230 | |
| 231 | /* ABB efuse masks */ |
Nishanth Menon | 159a21f | 2017-08-04 21:42:09 -0500 | [diff] [blame] | 232 | #define OMAP5_PROD_ABB_FUSE_VSET_MASK (0x1F << 20) |
| 233 | #define OMAP5_PROD_ABB_FUSE_ENABLE_MASK (0x1 << 25) |
Nishanth Menon | 22737ab | 2014-01-14 12:27:29 -0600 | [diff] [blame] | 234 | #define DRA7_ABB_FUSE_VSET_MASK (0x1F << 20) |
| 235 | #define DRA7_ABB_FUSE_ENABLE_MASK (0x1 << 25) |
Andrii Tseglytskyi | 28095da | 2013-05-20 22:42:08 +0000 | [diff] [blame] | 236 | #define OMAP5_ABB_LDOVBBMPU_MUX_CTRL_MASK (0x1 << 10) |
| 237 | #define OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK (0x1f << 0) |
| 238 | |
Sricharan | 308fe92 | 2011-11-15 09:50:03 -0500 | [diff] [blame] | 239 | #ifndef __ASSEMBLY__ |
Lokesh Vutla | 2804963 | 2013-02-12 01:33:45 +0000 | [diff] [blame] | 240 | struct srcomp_params { |
| 241 | s8 divide_factor; |
| 242 | s8 multiply_factor; |
| 243 | }; |
| 244 | |
Lokesh Vutla | d8ac050 | 2013-02-04 04:22:05 +0000 | [diff] [blame] | 245 | struct ctrl_ioregs { |
| 246 | u32 ctrl_ddrch; |
| 247 | u32 ctrl_lpddr2ch; |
| 248 | u32 ctrl_ddr3ch; |
| 249 | u32 ctrl_ddrio_0; |
| 250 | u32 ctrl_ddrio_1; |
| 251 | u32 ctrl_ddrio_2; |
| 252 | u32 ctrl_emif_sdram_config_ext; |
SRICHARAN R | e02f5f8 | 2013-11-08 17:40:37 +0530 | [diff] [blame] | 253 | u32 ctrl_emif_sdram_config_ext_final; |
Sricharan R | ffa9818 | 2013-05-30 03:19:39 +0000 | [diff] [blame] | 254 | u32 ctrl_ddr_ctrl_ext_0; |
Lokesh Vutla | d8ac050 | 2013-02-04 04:22:05 +0000 | [diff] [blame] | 255 | }; |
Mugunthan V N | ab48f78 | 2013-07-08 16:04:41 +0530 | [diff] [blame] | 256 | |
Nishanth Menon | be3a553 | 2015-08-13 09:51:00 -0500 | [diff] [blame] | 257 | void clrset_spare_register(u8 spare_type, u32 clear_bits, u32 set_bits); |
| 258 | |
Sricharan | 308fe92 | 2011-11-15 09:50:03 -0500 | [diff] [blame] | 259 | #endif /* __ASSEMBLY__ */ |
Paul Kocialkowski | d5b7624 | 2015-07-15 16:02:19 +0200 | [diff] [blame] | 260 | |
| 261 | /* Boot parameters */ |
| 262 | #ifndef __ASSEMBLY__ |
| 263 | struct omap_boot_parameters { |
| 264 | unsigned int boot_message; |
| 265 | unsigned int boot_device_descriptor; |
| 266 | unsigned char boot_device; |
| 267 | unsigned char reset_reason; |
| 268 | unsigned char ch_flags; |
| 269 | }; |
| 270 | #endif |
| 271 | |
Steve Sakoman | 1ad2158 | 2010-06-08 13:07:46 -0700 | [diff] [blame] | 272 | #endif |