commit 79a9ec780dff8075ee83e35f6c84b5dfaedf8bfe
author Lokesh Vutla <lokeshvutla@ti.com> Tue Feb 12 01:33:44 2013 +0000
committer Tom Rini <trini@ti.com> Mon Mar 11 11:06:10 2013 -0400
tree 5bbadfcd754737a33219e857e46f34e73cb0563a
parent a04ed14b235e3f3c2a751b698f43bc6a97b7b1bf

ARM: OMAP5: Add DDR changes required for OMAP543X ES2.0 SOCs

Add pre calculated timing settings of LPDDR2 and DDR3 memories
present in OMAP5430 and OMAP5432 ES2.0 versions.

Also adding the DDR pad io settings required for
OMAP543X SOCs here.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
Cc: Tom Rini <trini@ti.com>

arch/arm/include/asm/arch-omap5/omap.h

diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h
index 71935d8..ba2775b 100644
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -168,6 +168,12 @@
 #define DDR_IO_1_VREF_CELLS_DDR3_VALUE				0xBC6318DC
 #define DDR_IO_2_VREF_CELLS_DDR3_VALUE				0x0
 
+#define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x7C7C7C7C
+#define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x64656465
+#define DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2 0xBAE8C631
+#define DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2 0xB46318D8
+#define DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2 0x84210000
+
 #define EFUSE_1 0x45145100
 #define EFUSE_2 0x45145100
 #define EFUSE_3 0x45145100