blob: 10a973c1edb1d1e2fcbac7841cdd997c3c2d8323 [file] [log] [blame]
Steve Sakoman1ad21582010-06-08 13:07:46 -07001/*
2 * (C) Copyright 2010
3 * Texas Instruments, <www.ti.com>
4 *
5 * Authors:
6 * Aneesh V <aneesh@ti.com>
Sricharan9310ff72011-11-15 09:49:55 -05007 * Sricharan R <r.sricharan@ti.com>
Steve Sakoman1ad21582010-06-08 13:07:46 -07008 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
Sricharan9310ff72011-11-15 09:49:55 -050028#ifndef _OMAP5_H_
29#define _OMAP5_H_
Steve Sakoman1ad21582010-06-08 13:07:46 -070030
31#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
32#include <asm/types.h>
33#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
34
35/*
36 * L4 Peripherals - L4 Wakeup and L4 Core now
37 */
Sricharan9310ff72011-11-15 09:49:55 -050038#define OMAP54XX_L4_CORE_BASE 0x4A000000
39#define OMAP54XX_L4_WKUP_BASE 0x4Ae00000
40#define OMAP54XX_L4_PER_BASE 0x48000000
Steve Sakoman1ad21582010-06-08 13:07:46 -070041
Sricharan9310ff72011-11-15 09:49:55 -050042#define OMAP54XX_DRAM_ADDR_SPACE_START 0x80000000
43#define OMAP54XX_DRAM_ADDR_SPACE_END 0xD0000000
44#define DRAM_ADDR_SPACE_START OMAP54XX_DRAM_ADDR_SPACE_START
45#define DRAM_ADDR_SPACE_END OMAP54XX_DRAM_ADDR_SPACE_END
Aneesh V04bd2b92010-09-12 10:32:55 +053046
Steve Sakoman1ad21582010-06-08 13:07:46 -070047/* CONTROL */
Sricharan9310ff72011-11-15 09:49:55 -050048#define CTRL_BASE (OMAP54XX_L4_CORE_BASE + 0x2000)
49#define CONTROL_PADCONF_CORE (CTRL_BASE + 0x0800)
50#define CONTROL_PADCONF_WKUP (OMAP54XX_L4_WKUP_BASE + 0xc800)
Steve Sakoman1ad21582010-06-08 13:07:46 -070051
Sricharan9310ff72011-11-15 09:49:55 -050052/* LPDDR2 IO regs. To be verified */
Aneesh Vcc565582011-07-21 09:10:09 -040053#define LPDDR2_IO_REGS_BASE 0x4A100638
54
Aneesh V162ced32011-07-21 09:10:04 -040055/* CONTROL_ID_CODE */
Sricharan9310ff72011-11-15 09:49:55 -050056#define CONTROL_ID_CODE (CTRL_BASE + 0x204)
Aneesh V162ced32011-07-21 09:10:04 -040057
Sricharan9310ff72011-11-15 09:49:55 -050058/* To be verified */
59#define OMAP5_CONTROL_ID_CODE_ES1_0 0x0B85202F
Aneesh V162ced32011-07-21 09:10:04 -040060
Sricharan9310ff72011-11-15 09:49:55 -050061/* STD_FUSE_PROD_ID_1 */
62#define STD_FUSE_PROD_ID_1 (CTRL_BASE + 0x218)
63#define PROD_ID_1_SILICON_TYPE_SHIFT 16
64#define PROD_ID_1_SILICON_TYPE_MASK (3 << 16)
Ricardo Salveti de Araujof79be102011-09-21 10:17:30 +000065
Steve Sakoman1ad21582010-06-08 13:07:46 -070066/* UART */
Sricharan9310ff72011-11-15 09:49:55 -050067#define UART1_BASE (OMAP54XX_L4_PER_BASE + 0x6a000)
68#define UART2_BASE (OMAP54XX_L4_PER_BASE + 0x6c000)
69#define UART3_BASE (OMAP54XX_L4_PER_BASE + 0x20000)
Steve Sakoman1ad21582010-06-08 13:07:46 -070070
71/* General Purpose Timers */
Sricharan9310ff72011-11-15 09:49:55 -050072#define GPT1_BASE (OMAP54XX_L4_WKUP_BASE + 0x18000)
73#define GPT2_BASE (OMAP54XX_L4_PER_BASE + 0x32000)
74#define GPT3_BASE (OMAP54XX_L4_PER_BASE + 0x34000)
Steve Sakoman1ad21582010-06-08 13:07:46 -070075
76/* Watchdog Timer2 - MPU watchdog */
Sricharan9310ff72011-11-15 09:49:55 -050077#define WDT2_BASE (OMAP54XX_L4_WKUP_BASE + 0x14000)
Steve Sakoman1ad21582010-06-08 13:07:46 -070078
79/* 32KTIMER */
Sricharan9310ff72011-11-15 09:49:55 -050080#define SYNC_32KTIMER_BASE (OMAP54XX_L4_WKUP_BASE + 0x4000)
Steve Sakoman1ad21582010-06-08 13:07:46 -070081
82/* GPMC */
Sricharan9310ff72011-11-15 09:49:55 -050083#define OMAP54XX_GPMC_BASE 0x50000000
Steve Sakoman1ad21582010-06-08 13:07:46 -070084
Aneesh Vb35f7cb2011-09-08 11:05:56 -040085/* SYSTEM CONTROL MODULE */
86#define SYSCTRL_GENERAL_CORE_BASE 0x4A002000
87
Steve Sakoman1ad21582010-06-08 13:07:46 -070088/*
89 * Hardware Register Details
90 */
91
92/* Watchdog Timer */
93#define WD_UNLOCK1 0xAAAA
94#define WD_UNLOCK2 0x5555
95
96/* GP Timer */
97#define TCLR_ST (0x1 << 0)
98#define TCLR_AR (0x1 << 1)
99#define TCLR_PRE (0x1 << 5)
100
101/*
102 * PRCM
103 */
104
105/* PRM */
Sricharan9310ff72011-11-15 09:49:55 -0500106#define PRM_BASE 0x4AE06000
Steve Sakoman1ad21582010-06-08 13:07:46 -0700107#define PRM_DEVICE_BASE (PRM_BASE + 0x1B00)
108
109#define PRM_RSTCTRL PRM_DEVICE_BASE
Steve Sakoman96b4a892010-08-25 13:22:44 -0700110#define PRM_RSTCTRL_RESET 0x01
Steve Sakoman1ad21582010-06-08 13:07:46 -0700111
Aneesh Vb35f7cb2011-09-08 11:05:56 -0400112/* Control Module */
113#define LDOSRAM_ACTMODE_VSET_IN_MASK (0x1F << 5)
114#define LDOSRAM_VOLT_CTRL_OVERRIDE 0x0401040f
115#define CONTROL_EFUSE_1_OVERRIDE 0x1C4D0110
116#define CONTROL_EFUSE_2_OVERRIDE 0x00084000
117
118/* LPDDR2 IO regs */
119#define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN 0x1C1C1C1C
120#define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER 0x9E9E9E9E
121#define CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN 0x7C7C7C7C
122#define LPDDR2IO_GR10_WD_MASK (3 << 17)
123#define CONTROL_LPDDR2IO_3_VAL 0xA0888C00
124
125/* CONTROL_EFUSE_2 */
126#define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000
127
Balaji T Kf843d332011-09-08 06:34:57 +0000128#define MMC1_PWRDNZ (1 << 26)
129#define MMC1_PBIASLITE_PWRDNZ (1 << 22)
130#define MMC1_PBIASLITE_VMODE (1 << 21)
131
Steve Sakoman1ad21582010-06-08 13:07:46 -0700132#ifndef __ASSEMBLY__
133
134struct s32ktimer {
135 unsigned char res[0x10];
136 unsigned int s32k_cr; /* 0x10 */
137};
138
SRICHARAN R8ec587d2012-03-12 02:25:36 +0000139#define OMAP5_IOREGS_BASE 0x4A002DA0
Aneesh Vb35f7cb2011-09-08 11:05:56 -0400140
SRICHARAN R8ec587d2012-03-12 02:25:36 +0000141struct omap5_sys_ctrl_regs {
142 u32 control_paconf_global; /* 0x4A002DA0 */
143 u32 control_paconf_mode; /* 0x4A002DA4 */
144 u32 control_smart1io_padconf_0; /* 0x4A002DA8 */
145 u32 control_smart1io_padconf_1; /* 0x4A002DAC */
146 u32 control_smart1io_padconf_2; /* 0x4A002DB0 */
147 u32 control_smart2io_padconf_0; /* 0x4A002DB4 */
148 u32 control_smart2io_padconf_1; /* 0x4A002DB8 */
149 u32 control_smart2io_padconf_2; /* 0x4A002DBC */
150 u32 control_smart3io_padconf_0; /* 0x4A002DC0 */
151 u32 control_smart3io_padconf_1; /* 0x4A002DC4 */
152 u32 pad1[14];
153 u32 control_pbias; /* 0x4A002E00 */
154 u32 control_i2c_0; /* 0x4A002E04 */
155 u32 control_camera_rx; /* 0x4A002E08 */
156 u32 control_hdmi_tx_phy; /* 0x4A002E0C */
157 u32 control_uniportm; /* 0x4A002E10 */
158 u32 control_dsiphy; /* 0x4A002E14 */
159 u32 control_mcbsplp; /* 0x4A002E18 */
160 u32 control_usb2phycore; /* 0x4A002E1C */
161 u32 control_hdmi_1; /*0x4A002E20*/
162 u32 control_hsi; /*0x4A002E24*/
163 u32 pad2[2];
164 u32 control_ddr3ch1_0; /*0x4A002E30*/
165 u32 control_ddr3ch2_0; /*0x4A002E34*/
166 u32 control_ddrch1_0; /*0x4A002E38*/
167 u32 control_ddrch1_1; /*0x4A002E3C*/
168 u32 control_ddrch2_0; /*0x4A002E40*/
169 u32 control_ddrch2_1; /*0x4A002E44*/
170 u32 control_lpddr2ch1_0; /*0x4A002E48*/
171 u32 control_lpddr2ch1_1; /*0x4A002E4C*/
172 u32 control_ddrio_0; /*0x4A002E50*/
173 u32 control_ddrio_1; /*0x4A002E54*/
174 u32 control_ddrio_2; /*0x4A002E58*/
175 u32 control_hyst_1; /*0x4A002E5C*/
176 u32 control_usbb_hsic_control; /*0x4A002E60*/
177 u32 control_c2c; /*0x4A002E64*/
178 u32 control_core_control_spare_rw; /*0x4A002E68*/
179 u32 control_core_control_spare_r; /*0x4A002E6C*/
180 u32 control_core_control_spare_r_c0; /*0x4A002E70*/
181 u32 control_srcomp_north_side; /*0x4A002E74*/
182 u32 control_srcomp_south_side; /*0x4A002E78*/
183 u32 control_srcomp_east_side; /*0x4A002E7C*/
184 u32 control_srcomp_west_side; /*0x4A002E80*/
185 u32 control_srcomp_code_latch; /*0x4A002E84*/
186 u32 pad3[3680198];
187 u32 control_smart1nopmio_padconf_0; /* 0x4AE0CDA0 */
188 u32 control_smart1nopmio_padconf_1; /* 0x4AE0CDA4 */
189 u32 control_padconf_mode; /* 0x4AE0CDA8 */
190 u32 control_xtal_oscillator; /* 0x4AE0CDAC */
191 u32 control_i2c_2; /* 0x4AE0CDB0 */
192 u32 control_ckobuffer; /* 0x4AE0CDB4 */
193 u32 control_wkup_control_spare_rw; /* 0x4AE0CDB8 */
194 u32 control_wkup_control_spare_r; /* 0x4AE0CDBC */
195 u32 control_wkup_control_spare_r_c0; /* 0x4AE0CDC0 */
196 u32 control_srcomp_east_side_wkup; /* 0x4AE0CDC4 */
197 u32 control_efuse_1; /* 0x4AE0CDC8 */
198 u32 control_efuse_2; /* 0x4AE0CDCC */
199 u32 control_efuse_3; /* 0x4AE0CDD0 */
200 u32 control_efuse_4; /* 0x4AE0CDD4 */
201 u32 control_efuse_5; /* 0x4AE0CDD8 */
202 u32 control_efuse_6; /* 0x4AE0CDDC */
203 u32 control_efuse_7; /* 0x4AE0CDE0 */
204 u32 control_efuse_8; /* 0x4AE0CDE4 */
205 u32 control_efuse_9; /* 0x4AE0CDE8 */
206 u32 control_efuse_10; /* 0x4AE0CDEC */
207 u32 control_efuse_11; /* 0x4AE0CDF0 */
208 u32 control_efuse_12; /* 0x4AE0CDF4 */
209 u32 control_efuse_13; /* 0x4AE0CDF8 */
Aneesh Vb35f7cb2011-09-08 11:05:56 -0400210};
SRICHARAN R8ec587d2012-03-12 02:25:36 +0000211
212/* Output impedance control */
213#define ds_120_ohm 0x0
214#define ds_60_ohm 0x1
215#define ds_45_ohm 0x2
216#define ds_30_ohm 0x3
217#define ds_mask 0x3
218
219/* Slew rate control */
220#define sc_slow 0x0
221#define sc_medium 0x1
222#define sc_fast 0x2
223#define sc_na 0x3
224#define sc_mask 0x3
225
226/* Target capacitance control */
227#define lb_5_12_pf 0x0
228#define lb_12_25_pf 0x1
229#define lb_25_50_pf 0x2
230#define lb_50_80_pf 0x3
231#define lb_mask 0x3
232
233#define usb_i_mask 0x7
234
235#define DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN 0x80828082
236#define DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN 0x82828200
237#define DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL 0x8421
238#define DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL 0x8421084
239#define DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL 0x8421000
240
241#define EFUSE_1 0x45145100
242#define EFUSE_2 0x45145100
243#define EFUSE_3 0x45145100
244#define EFUSE_4 0x45145100
Steve Sakoman1ad21582010-06-08 13:07:46 -0700245#endif /* __ASSEMBLY__ */
246
247/*
248 * Non-secure SRAM Addresses
249 * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE
250 * at 0x40304000(EMU base) so that our code works for both EMU and GP
251 */
SRICHARAN Rd47786c2012-03-12 02:25:41 +0000252#define NON_SECURE_SRAM_START 0x40300000
Sricharan9310ff72011-11-15 09:49:55 -0500253#define NON_SECURE_SRAM_END 0x40320000 /* Not inclusive */
Steve Sakoman1ad21582010-06-08 13:07:46 -0700254/* base address for indirect vectors (internal boot mode) */
Sricharan9310ff72011-11-15 09:49:55 -0500255#define SRAM_ROM_VECT_BASE 0x4031F000
Steve Sakoman1ad21582010-06-08 13:07:46 -0700256/* Temporary SRAM stack used while low level init is done */
Sricharan9310ff72011-11-15 09:49:55 -0500257#define LOW_LEVEL_SRAM_STACK NON_SECURE_SRAM_END
258
Aneesh V162ced32011-07-21 09:10:04 -0400259#define SRAM_SCRATCH_SPACE_ADDR NON_SECURE_SRAM_START
Sricharan9310ff72011-11-15 09:49:55 -0500260/*
261 * SRAM scratch space entries
262 */
263#define OMAP5_SRAM_SCRATCH_OMAP5_REV SRAM_SCRATCH_SPACE_ADDR
264#define OMAP5_SRAM_SCRATCH_EMIF_SIZE (SRAM_SCRATCH_SPACE_ADDR + 0x4)
265#define OMAP5_SRAM_SCRATCH_EMIF_T_NUM (SRAM_SCRATCH_SPACE_ADDR + 0xC)
266#define OMAP5_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10)
267#define OMAP5_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x14)
Steve Sakoman1ad21582010-06-08 13:07:46 -0700268
Aneesh V162ced32011-07-21 09:10:04 -0400269/* Silicon revisions */
270#define OMAP4430_SILICON_ID_INVALID 0xFFFFFFFF
271#define OMAP4430_ES1_0 0x44300100
272#define OMAP4430_ES2_0 0x44300200
273#define OMAP4430_ES2_1 0x44300210
274#define OMAP4430_ES2_2 0x44300220
275#define OMAP4430_ES2_3 0x44300230
Aneesh V0b92f092011-07-21 09:29:23 -0400276#define OMAP4460_ES1_0 0x44600100
Ricardo Salveti de Araujof79be102011-09-21 10:17:30 +0000277#define OMAP4460_ES1_1 0x44600110
Steve Sakoman1ad21582010-06-08 13:07:46 -0700278
Aneesh V13a74c12011-07-21 09:10:27 -0400279/* ROM code defines */
280/* Boot device */
281#define BOOT_DEVICE_MASK 0xFF
282#define BOOT_DEVICE_OFFSET 0x8
283#define DEV_DESC_PTR_OFFSET 0x4
284#define DEV_DATA_PTR_OFFSET 0x18
285#define BOOT_MODE_OFFSET 0x8
Sricharan308fe922011-11-15 09:50:03 -0500286#define RESET_REASON_OFFSET 0x9
287#define CH_FLAGS_OFFSET 0xA
288
289#define CH_FLAGS_CHSETTINGS (0x1 << 0)
290#define CH_FLAGS_CHRAM (0x1 << 1)
291#define CH_FLAGS_CHFLASH (0x1 << 2)
292#define CH_FLAGS_CHMMCSD (0x1 << 3)
Aneesh V13a74c12011-07-21 09:10:27 -0400293
Sricharan308fe922011-11-15 09:50:03 -0500294#ifndef __ASSEMBLY__
295struct omap_boot_parameters {
296 char *boot_message;
297 unsigned int mem_boot_descriptor;
298 unsigned char omap_bootdevice;
299 unsigned char reset_reason;
300 unsigned char ch_flags;
301};
302#endif /* __ASSEMBLY__ */
Steve Sakoman1ad21582010-06-08 13:07:46 -0700303#endif