| Steve Sakoman | 1ad2158 | 2010-06-08 13:07:46 -0700 | [diff] [blame^] | 1 | /* |
| 2 | * (C) Copyright 2010 |
| 3 | * Texas Instruments, <www.ti.com> |
| 4 | * |
| 5 | * Authors: |
| 6 | * Aneesh V <aneesh@ti.com> |
| 7 | * |
| 8 | * Derived from OMAP3 work by |
| 9 | * Richard Woodruff <r-woodruff2@ti.com> |
| 10 | * Syed Mohammed Khasim <x0khasim@ti.com> |
| 11 | * |
| 12 | * See file CREDITS for list of people who contributed to this |
| 13 | * project. |
| 14 | * |
| 15 | * This program is free software; you can redistribute it and/or |
| 16 | * modify it under the terms of the GNU General Public License as |
| 17 | * published by the Free Software Foundation; either version 2 of |
| 18 | * the License, or (at your option) any later version. |
| 19 | * |
| 20 | * This program is distributed in the hope that it will be useful, |
| 21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 23 | * GNU General Public License for more details. |
| 24 | * |
| 25 | * You should have received a copy of the GNU General Public License |
| 26 | * along with this program; if not, write to the Free Software |
| 27 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 28 | * MA 02111-1307 USA |
| 29 | */ |
| 30 | |
| 31 | #ifndef _OMAP4_H_ |
| 32 | #define _OMAP4_H_ |
| 33 | |
| 34 | #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) |
| 35 | #include <asm/types.h> |
| 36 | #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ |
| 37 | |
| 38 | /* |
| 39 | * L4 Peripherals - L4 Wakeup and L4 Core now |
| 40 | */ |
| 41 | #define OMAP44XX_L4_CORE_BASE 0x4A000000 |
| 42 | #define OMAP44XX_L4_WKUP_BASE 0x4A300000 |
| 43 | #define OMAP44XX_L4_PER_BASE 0x48000000 |
| 44 | |
| 45 | /* CONTROL */ |
| 46 | #define CTRL_BASE (OMAP44XX_L4_CORE_BASE + 0x2000) |
| 47 | |
| 48 | /* UART */ |
| 49 | #define UART1_BASE (OMAP44XX_L4_PER_BASE + 0x6a000) |
| 50 | #define UART2_BASE (OMAP44XX_L4_PER_BASE + 0x6c000) |
| 51 | #define UART3_BASE (OMAP44XX_L4_PER_BASE + 0x20000) |
| 52 | |
| 53 | /* General Purpose Timers */ |
| 54 | #define GPT1_BASE (OMAP44XX_L4_WKUP_BASE + 0x18000) |
| 55 | #define GPT2_BASE (OMAP44XX_L4_PER_BASE + 0x32000) |
| 56 | #define GPT3_BASE (OMAP44XX_L4_PER_BASE + 0x34000) |
| 57 | |
| 58 | /* Watchdog Timer2 - MPU watchdog */ |
| 59 | #define WDT2_BASE (OMAP44XX_L4_WKUP_BASE + 0x14000) |
| 60 | |
| 61 | /* 32KTIMER */ |
| 62 | #define SYNC_32KTIMER_BASE (OMAP44XX_L4_WKUP_BASE + 0x4000) |
| 63 | |
| 64 | /* GPMC */ |
| 65 | #define GPMC_BASE 0x50000000 |
| 66 | |
| 67 | /* |
| 68 | * Hardware Register Details |
| 69 | */ |
| 70 | |
| 71 | /* Watchdog Timer */ |
| 72 | #define WD_UNLOCK1 0xAAAA |
| 73 | #define WD_UNLOCK2 0x5555 |
| 74 | |
| 75 | /* GP Timer */ |
| 76 | #define TCLR_ST (0x1 << 0) |
| 77 | #define TCLR_AR (0x1 << 1) |
| 78 | #define TCLR_PRE (0x1 << 5) |
| 79 | |
| 80 | /* |
| 81 | * PRCM |
| 82 | */ |
| 83 | |
| 84 | /* PRM */ |
| 85 | #define PRM_BASE 0x4A306000 |
| 86 | #define PRM_DEVICE_BASE (PRM_BASE + 0x1B00) |
| 87 | |
| 88 | #define PRM_RSTCTRL PRM_DEVICE_BASE |
| 89 | |
| 90 | #ifndef __ASSEMBLY__ |
| 91 | |
| 92 | struct s32ktimer { |
| 93 | unsigned char res[0x10]; |
| 94 | unsigned int s32k_cr; /* 0x10 */ |
| 95 | }; |
| 96 | |
| 97 | #endif /* __ASSEMBLY__ */ |
| 98 | |
| 99 | /* |
| 100 | * Non-secure SRAM Addresses |
| 101 | * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE |
| 102 | * at 0x40304000(EMU base) so that our code works for both EMU and GP |
| 103 | */ |
| 104 | #define NON_SECURE_SRAM_START 0x40304000 |
| 105 | #define NON_SECURE_SRAM_END 0x4030E000 /* Not inclusive */ |
| 106 | /* base address for indirect vectors (internal boot mode) */ |
| 107 | #define SRAM_ROM_VECT_BASE 0x4030D000 |
| 108 | /* Temporary SRAM stack used while low level init is done */ |
| 109 | #define LOW_LEVEL_SRAM_STACK NON_SECURE_SRAM_END |
| 110 | |
| 111 | /* |
| 112 | * OMAP4 real hardware: |
| 113 | * TODO: Change this to the IDCODE in the hw regsiter |
| 114 | */ |
| 115 | #define CPU_OMAP4430_ES10 1 |
| 116 | #define CPU_OMAP4430_ES20 2 |
| 117 | |
| 118 | #endif |