blob: 4ee471238eebe99c7c31e7b26c4931b69cea8363 [file] [log] [blame]
Simon Glass4cc43bf2021-08-18 21:40:25 -06001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Devicetree file for running sandbox tests
4 *
5 * This includes lots of extra devices used by various tests.
6 *
7 * Note that SPL use the main sandbox.dts file
8 */
9
Simon Glassb2c1cac2014-02-26 15:59:21 -070010/dts-v1/;
11
Patrick Delaunay23aee612020-01-13 11:35:13 +010012#include <dt-bindings/gpio/gpio.h>
13#include <dt-bindings/gpio/sandbox-gpio.h>
Marek Szyprowskiad398592021-02-18 11:33:18 +010014#include <dt-bindings/input/input.h>
Sean Anderson3438e3b2020-09-14 11:01:57 -040015#include <dt-bindings/pinctrl/sandbox-pinmux.h>
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +053016#include <dt-bindings/mux/mux.h>
Patrick Delaunay23aee612020-01-13 11:35:13 +010017
Simon Glassb2c1cac2014-02-26 15:59:21 -070018/ {
19 model = "sandbox";
20 compatible = "sandbox";
21 #address-cells = <1>;
Simon Glasscf61f742015-07-06 12:54:36 -060022 #size-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -070023
Simon Glassfef72b72014-07-23 06:55:03 -060024 aliases {
25 console = &uart0;
Michael Walle7efcdfd2021-02-25 16:51:11 +010026 ethernet0 = "/eth@10002000";
27 ethernet2 = &swp_0;
28 ethernet3 = &eth_3;
29 ethernet4 = &dsa_eth0;
30 ethernet5 = &eth_5;
Sean Anderson67d93a42022-05-05 13:11:30 -040031 ethernet6 = "/eth@10004000";
32 ethernet7 = &swp_1;
33 ethernet8 = &phy_eth0;
Simon Glass5620cf82018-10-01 12:22:40 -060034 gpio1 = &gpio_a;
35 gpio2 = &gpio_b;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +010036 gpio3 = &gpio_c;
Simon Glass0ccb0972015-01-25 08:27:05 -070037 i2c0 = "/i2c@0";
Simon Glasse4fef742017-04-23 20:02:07 -060038 mmc0 = "/mmc0";
39 mmc1 = "/mmc1";
Bin Meng408e5902018-08-03 01:14:41 -070040 pci0 = &pci0;
41 pci1 = &pci1;
Bin Meng510dddb2018-08-03 01:14:50 -070042 pci2 = &pci2;
Michael Walle7c41a222020-06-02 01:47:09 +020043 remoteproc0 = &rproc_1;
44 remoteproc1 = &rproc_2;
Simon Glass336b2952015-05-22 15:42:17 -060045 rtc0 = &rtc_0;
46 rtc1 = &rtc_1;
Simon Glass5b968632015-05-22 15:42:15 -060047 spi0 = "/spi@0";
Przemyslaw Marczak3dbb55e2015-05-13 13:38:34 +020048 testfdt6 = "/e-test";
Simon Glass0ccb0972015-01-25 08:27:05 -070049 testbus3 = "/some-bus";
50 testfdt0 = "/some-bus/c-test@0";
Simon Glass7d5e4112020-12-16 21:20:26 -070051 testfdt12 = "/some-bus/c-test@1";
Simon Glass0ccb0972015-01-25 08:27:05 -070052 testfdt3 = "/b-test";
53 testfdt5 = "/some-bus/c-test@5";
54 testfdt8 = "/a-test";
Simon Glass791a17f2020-12-16 21:20:27 -070055 testfdtm1 = &testfdtm1;
Eugeniu Rosca5ba71e52018-05-19 14:13:55 +020056 fdt-dummy0 = "/translation-test@8000/dev@0,0";
57 fdt-dummy1 = "/translation-test@8000/dev@1,100";
58 fdt-dummy2 = "/translation-test@8000/dev@2,200";
59 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glass31680482015-03-25 12:23:05 -060060 usb0 = &usb_0;
61 usb1 = &usb_1;
62 usb2 = &usb_2;
Mario Six95922152018-08-09 14:51:19 +020063 axi0 = &axi;
Mario Six02ad6fb2018-09-27 09:19:31 +020064 osd0 = "/osd";
Simon Glassfef72b72014-07-23 06:55:03 -060065 };
66
Philippe Reynes462d1632022-03-28 22:56:53 +020067 binman {
68 };
69
Rasmus Villemoes30d4d2b2021-04-21 11:06:55 +020070 config {
Simon Glass0034d962021-08-07 07:24:01 -060071 testing-bool;
72 testing-int = <123>;
73 testing-str = "testing";
Rasmus Villemoes30d4d2b2021-04-21 11:06:55 +020074 environment {
75 from_fdt = "yes";
76 fdt_env_path = "";
77 };
78 };
79
Simon Glassb255efc2022-04-24 23:31:24 -060080 bootstd {
81 compatible = "u-boot,boot-std";
82
83 filename-prefixes = "/", "/boot/";
84 bootdev-order = "mmc2", "mmc1";
85
86 syslinux {
87 compatible = "u-boot,distro-syslinux";
88 };
89
90 efi {
91 compatible = "u-boot,distro-efi";
92 };
93 };
94
Andrew Scull451b8b12022-05-30 10:00:12 +000095 fuzzing-engine {
96 compatible = "sandbox,fuzzing-engine";
97 };
98
Nandor Han6521e5d2021-06-10 16:56:44 +030099 reboot-mode0 {
100 compatible = "reboot-mode-gpio";
101 gpios = <&gpio_c 0 GPIO_ACTIVE_HIGH>, <&gpio_c 1 GPIO_ACTIVE_HIGH>;
102 u-boot,env-variable = "bootstatus";
103 mode-test = <0x01>;
104 mode-download = <0x03>;
105 };
106
Nandor Han7e4067a2021-06-10 16:56:45 +0300107 reboot_mode1: reboot-mode@14 {
108 compatible = "reboot-mode-rtc";
109 rtc = <&rtc_0>;
110 reg = <0x30 4>;
111 u-boot,env-variable = "bootstatus";
112 big-endian;
113 mode-test = <0x21969147>;
114 mode-download = <0x51939147>;
115 };
116
Simon Glassed96cde2018-12-10 10:37:33 -0700117 audio: audio-codec {
118 compatible = "sandbox,audio-codec";
119 #sound-dai-cells = <1>;
120 };
121
Philippe Reynes1ee26482020-07-24 18:19:51 +0200122 buttons {
123 compatible = "gpio-keys";
124
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200125 btn1 {
Philippe Reynes1ee26482020-07-24 18:19:51 +0200126 gpios = <&gpio_a 3 0>;
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200127 label = "button1";
Philippe Reynes1ee26482020-07-24 18:19:51 +0200128 };
129
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200130 btn2 {
Philippe Reynes1ee26482020-07-24 18:19:51 +0200131 gpios = <&gpio_a 4 0>;
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200132 label = "button2";
Philippe Reynes1ee26482020-07-24 18:19:51 +0200133 };
134 };
135
Marek Szyprowskiad398592021-02-18 11:33:18 +0100136 buttons2 {
137 compatible = "adc-keys";
138 io-channels = <&adc 3>;
139 keyup-threshold-microvolt = <3000000>;
140
141 button-up {
142 label = "button3";
143 linux,code = <KEY_F3>;
144 press-threshold-microvolt = <1500000>;
145 };
146
147 button-down {
148 label = "button4";
149 linux,code = <KEY_F4>;
150 press-threshold-microvolt = <1000000>;
151 };
152
153 button-enter {
154 label = "button5";
155 linux,code = <KEY_F5>;
156 press-threshold-microvolt = <500000>;
157 };
158 };
159
Simon Glassc953aaf2018-12-10 10:37:34 -0700160 cros_ec: cros-ec {
Simon Glass699c9ca2018-10-01 12:22:08 -0600161 reg = <0 0>;
162 compatible = "google,cros-ec-sandbox";
163
164 /*
165 * This describes the flash memory within the EC. Note
166 * that the STM32L flash erases to 0, not 0xff.
167 */
168 flash {
169 image-pos = <0x08000000>;
170 size = <0x20000>;
171 erase-value = <0>;
172
173 /* Information for sandbox */
174 ro {
175 image-pos = <0>;
176 size = <0xf000>;
177 };
178 wp-ro {
179 image-pos = <0xf000>;
180 size = <0x1000>;
Simon Glassbf0a6922021-01-21 13:57:14 -0700181 used = <0x884>;
182 compress = "lz4";
183 uncomp-size = <0xcf8>;
184 hash {
185 algo = "sha256";
186 value = [00 01 02 03 04 05 06 07
187 08 09 0a 0b 0c 0d 0e 0f
188 10 11 12 13 14 15 16 17
189 18 19 1a 1b 1c 1d 1e 1f];
190 };
Simon Glass699c9ca2018-10-01 12:22:08 -0600191 };
192 rw {
193 image-pos = <0x10000>;
194 size = <0x10000>;
195 };
196 };
Alper Nebi Yasak8a8cd4f2021-05-19 19:33:31 +0300197
198 cros_ec_pwm: cros-ec-pwm {
199 compatible = "google,cros-ec-pwm";
200 #pwm-cells = <1>;
201 };
202
Simon Glass699c9ca2018-10-01 12:22:08 -0600203 };
204
Yannick Fertré9712c822019-10-07 15:29:05 +0200205 dsi_host: dsi_host {
206 compatible = "sandbox,dsi-host";
207 };
208
Simon Glassb2c1cac2014-02-26 15:59:21 -0700209 a-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600210 reg = <0 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700211 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600212 ping-expect = <0>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700213 ping-add = <0>;
Simon Glassfef72b72014-07-23 06:55:03 -0600214 u-boot,dm-pre-reloc;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100215 test-gpios = <&gpio_a 1>, <&gpio_a 4>,
216 <&gpio_b 5 GPIO_ACTIVE_HIGH 3 2 1>,
Simon Glass16e10402015-01-05 20:05:29 -0700217 <0>, <&gpio_a 12>;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100218 test2-gpios = <&gpio_a 1>, <&gpio_a 4>,
219 <&gpio_b 6 GPIO_ACTIVE_LOW 3 2 1>,
220 <&gpio_b 7 GPIO_IN 3 2 1>,
221 <&gpio_b 8 GPIO_OUT 3 2 1>,
222 <&gpio_b 9 (GPIO_OUT|GPIO_OUT_ACTIVE) 3 2 1>;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100223 test3-gpios =
224 <&gpio_c 0 (GPIO_OUT|GPIO_OPEN_DRAIN)>,
225 <&gpio_c 1 (GPIO_OUT|GPIO_OPEN_SOURCE)>,
226 <&gpio_c 2 GPIO_OUT>,
227 <&gpio_c 3 (GPIO_IN|GPIO_PULL_UP)>,
228 <&gpio_c 4 (GPIO_IN|GPIO_PULL_DOWN)>,
Neil Armstrong643778b2020-05-05 10:43:18 +0200229 <&gpio_c 5 GPIO_IN>,
230 <&gpio_c 6 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_DRAIN)>,
231 <&gpio_c 7 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_SOURCE)>;
Jean-Jacques Hiblot73873402020-09-11 13:43:35 +0530232 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
233 test5-gpios = <&gpio_a 19>;
234
Simon Glass73025392021-10-23 17:26:04 -0600235 bool-value;
Stefan Herbrechtsmeier1b090e62022-06-14 15:21:30 +0200236 int8-value = /bits/ 8 <0x12>;
237 int16-value = /bits/ 16 <0x1234>;
Simon Glass6df01f92018-12-10 10:37:37 -0700238 int-value = <1234>;
239 uint-value = <(-1234)>;
Dario Binacchi421e81e2020-03-29 18:04:40 +0200240 int64-value = /bits/ 64 <0x1111222233334444>;
Dario Binacchi81d80b52020-03-29 18:04:41 +0200241 int-array = <5678 9123 4567>;
Simon Glassdd0ed902020-07-07 13:11:58 -0600242 str-value = "test string";
Simon Glass515dcff2020-02-06 09:55:00 -0700243 interrupts-extended = <&irq 3 0>;
Simon Glass09642392020-07-07 13:12:11 -0600244 acpi,name = "GHIJ";
Patrick Delaunay8cd28012020-09-25 09:41:16 +0200245 phandle-value = <&gpio_c 10>, <0xFFFFFFFF 20>, <&gpio_a 30>;
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530246
247 mux-controls = <&muxcontroller0 0>, <&muxcontroller0 1>,
248 <&muxcontroller0 2>, <&muxcontroller0 3>,
249 <&muxcontroller1>;
250 mux-control-names = "mux0", "mux1", "mux2", "mux3", "mux4";
251 mux-syscon = <&syscon3>;
Dario Binacchi836cc9d2020-12-30 00:16:26 +0100252 display-timings {
253 timing0: 240x320 {
254 clock-frequency = <6500000>;
255 hactive = <240>;
256 vactive = <320>;
257 hfront-porch = <6>;
258 hback-porch = <7>;
259 hsync-len = <1>;
260 vback-porch = <5>;
261 vfront-porch = <8>;
262 vsync-len = <2>;
263 hsync-active = <1>;
264 vsync-active = <0>;
265 de-active = <1>;
266 pixelclk-active = <1>;
267 interlaced;
268 doublescan;
269 doubleclk;
270 };
271 timing1: 480x800 {
272 clock-frequency = <9000000>;
273 hactive = <480>;
274 vactive = <800>;
275 hfront-porch = <10>;
276 hback-porch = <59>;
277 hsync-len = <12>;
278 vback-porch = <15>;
279 vfront-porch = <17>;
280 vsync-len = <16>;
281 hsync-active = <0>;
282 vsync-active = <1>;
283 de-active = <0>;
284 pixelclk-active = <0>;
285 };
286 timing2: 800x480 {
287 clock-frequency = <33500000>;
288 hactive = <800>;
289 vactive = <480>;
290 hback-porch = <89>;
291 hfront-porch = <164>;
292 vback-porch = <23>;
293 vfront-porch = <10>;
294 hsync-len = <11>;
295 vsync-len = <13>;
296 };
297 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700298 };
299
300 junk {
Simon Glasscf61f742015-07-06 12:54:36 -0600301 reg = <1 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700302 compatible = "not,compatible";
303 };
304
305 no-compatible {
Simon Glasscf61f742015-07-06 12:54:36 -0600306 reg = <2 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700307 };
308
Simon Glass5620cf82018-10-01 12:22:40 -0600309 backlight: backlight {
310 compatible = "pwm-backlight";
311 enable-gpios = <&gpio_a 1>;
312 power-supply = <&ldo_1>;
313 pwms = <&pwm 0 1000>;
314 default-brightness-level = <5>;
315 brightness-levels = <0 16 32 64 128 170 202 234 255>;
316 };
317
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200318 bind-test {
Patrice Chotard7b7f9392020-07-28 09:13:33 +0200319 compatible = "simple-bus";
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200320 bind-test-child1 {
321 compatible = "sandbox,phy";
322 #phy-cells = <1>;
323 };
324
325 bind-test-child2 {
326 compatible = "simple-bus";
327 };
328 };
329
Simon Glassb2c1cac2014-02-26 15:59:21 -0700330 b-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600331 reg = <3 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700332 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600333 ping-expect = <3>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700334 ping-add = <3>;
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530335
336 mux-controls = <&muxcontroller0 0>;
337 mux-control-names = "mux0";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700338 };
339
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200340 phy_provider0: gen_phy@0 {
341 compatible = "sandbox,phy";
342 #phy-cells = <1>;
343 };
344
345 phy_provider1: gen_phy@1 {
346 compatible = "sandbox,phy";
347 #phy-cells = <0>;
348 broken;
349 };
350
developer71092972020-05-02 11:35:12 +0200351 phy_provider2: gen_phy@2 {
352 compatible = "sandbox,phy";
353 #phy-cells = <0>;
354 };
355
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200356 gen_phy_user: gen_phy_user {
357 compatible = "simple-bus";
358 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
359 phy-names = "phy1", "phy2", "phy3";
360 };
361
developer71092972020-05-02 11:35:12 +0200362 gen_phy_user1: gen_phy_user1 {
363 compatible = "simple-bus";
364 phys = <&phy_provider0 0>, <&phy_provider2>;
365 phy-names = "phy1", "phy2";
366 };
367
Simon Glassb2c1cac2014-02-26 15:59:21 -0700368 some-bus {
369 #address-cells = <1>;
370 #size-cells = <0>;
Simon Glass40717422014-07-23 06:55:18 -0600371 compatible = "denx,u-boot-test-bus";
Simon Glasscf61f742015-07-06 12:54:36 -0600372 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600373 ping-expect = <4>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700374 ping-add = <4>;
Simon Glass40717422014-07-23 06:55:18 -0600375 c-test@5 {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700376 compatible = "denx,u-boot-fdt-test";
377 reg = <5>;
Simon Glass40717422014-07-23 06:55:18 -0600378 ping-expect = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700379 ping-add = <5>;
380 };
Simon Glass40717422014-07-23 06:55:18 -0600381 c-test@0 {
382 compatible = "denx,u-boot-fdt-test";
383 reg = <0>;
384 ping-expect = <6>;
385 ping-add = <6>;
386 };
387 c-test@1 {
388 compatible = "denx,u-boot-fdt-test";
389 reg = <1>;
390 ping-expect = <7>;
391 ping-add = <7>;
392 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700393 };
394
395 d-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600396 reg = <3 1>;
Simon Glassdb6f0202014-07-23 06:55:12 -0600397 ping-expect = <6>;
398 ping-add = <6>;
399 compatible = "google,another-fdt-test";
400 };
401
402 e-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600403 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600404 ping-expect = <6>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700405 ping-add = <6>;
406 compatible = "google,another-fdt-test";
407 };
408
Simon Glass0ccb0972015-01-25 08:27:05 -0700409 f-test {
410 compatible = "denx,u-boot-fdt-test";
411 };
412
413 g-test {
414 compatible = "denx,u-boot-fdt-test";
415 };
416
Bin Mengd9d24782018-10-10 22:07:01 -0700417 h-test {
418 compatible = "denx,u-boot-fdt-test1";
419 };
420
developercf8bc132020-05-02 11:35:10 +0200421 i-test {
422 compatible = "mediatek,u-boot-fdt-test";
423 #address-cells = <1>;
424 #size-cells = <0>;
425
426 subnode@0 {
427 reg = <0>;
428 };
429
430 subnode@1 {
431 reg = <1>;
432 };
433
434 subnode@2 {
435 reg = <2>;
436 };
437 };
438
Simon Glass204675c2019-12-29 21:19:25 -0700439 devres-test {
440 compatible = "denx,u-boot-devres-test";
441 };
442
Jean-Jacques Hiblot73873402020-09-11 13:43:35 +0530443 another-test {
444 reg = <0 2>;
445 compatible = "denx,u-boot-fdt-test";
446 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
447 test5-gpios = <&gpio_a 19>;
448 };
449
Nicolas Saenz Julienne22b7f7e2021-01-12 13:55:23 +0100450 mmio-bus@0 {
451 #address-cells = <1>;
452 #size-cells = <1>;
453 compatible = "denx,u-boot-test-bus";
454 dma-ranges = <0x10000000 0x00000000 0x00040000>;
455
456 subnode@0 {
457 compatible = "denx,u-boot-fdt-test";
458 };
459 };
460
461 mmio-bus@1 {
462 #address-cells = <1>;
463 #size-cells = <1>;
464 compatible = "denx,u-boot-test-bus";
Nicolas Saenz Julienne892e9b42021-01-12 13:55:25 +0100465
466 subnode@0 {
467 compatible = "denx,u-boot-fdt-test";
468 };
Nicolas Saenz Julienne22b7f7e2021-01-12 13:55:23 +0100469 };
470
Simon Glass3c601b12020-07-07 13:12:06 -0600471 acpi_test1: acpi-test {
Simon Glass2d67fdf2020-04-08 16:57:34 -0600472 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600473 acpi-ssdt-test-data = "ab";
Simon Glass990cd5b2020-07-07 13:12:08 -0600474 acpi-dsdt-test-data = "hi";
Simon Glassebb2e832020-07-07 13:11:39 -0600475 child {
476 compatible = "denx,u-boot-acpi-test";
477 };
Simon Glass2d67fdf2020-04-08 16:57:34 -0600478 };
479
Simon Glass3c601b12020-07-07 13:12:06 -0600480 acpi_test2: acpi-test2 {
Simon Glass17968c32020-04-26 09:19:46 -0600481 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600482 acpi-ssdt-test-data = "cd";
Simon Glass990cd5b2020-07-07 13:12:08 -0600483 acpi-dsdt-test-data = "jk";
Simon Glass17968c32020-04-26 09:19:46 -0600484 };
485
Patrice Chotard9cc2d142017-09-04 14:55:57 +0200486 clocks {
487 clk_fixed: clk-fixed {
488 compatible = "fixed-clock";
489 #clock-cells = <0>;
490 clock-frequency = <1234>;
491 };
Anup Patel8d28c3c2019-02-25 08:14:55 +0000492
493 clk_fixed_factor: clk-fixed-factor {
494 compatible = "fixed-factor-clock";
495 #clock-cells = <0>;
496 clock-div = <3>;
497 clock-mult = <2>;
498 clocks = <&clk_fixed>;
499 };
Lukasz Majewskiccafcdd2019-06-24 15:50:47 +0200500
501 osc {
502 compatible = "fixed-clock";
503 #clock-cells = <0>;
504 clock-frequency = <20000000>;
505 };
Stephen Warrena9622432016-06-17 09:44:00 -0600506 };
507
508 clk_sandbox: clk-sbox {
Simon Glass8cc4d822015-07-06 12:54:24 -0600509 compatible = "sandbox,clk";
Stephen Warrena9622432016-06-17 09:44:00 -0600510 #clock-cells = <1>;
Jean-Jacques Hiblotc1e9c942019-10-22 14:00:07 +0200511 assigned-clocks = <&clk_sandbox 3>;
512 assigned-clock-rates = <321>;
Stephen Warrena9622432016-06-17 09:44:00 -0600513 };
514
515 clk-test {
516 compatible = "sandbox,clk-test";
517 clocks = <&clk_fixed>,
518 <&clk_sandbox 1>,
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200519 <&clk_sandbox 0>,
520 <&clk_sandbox 3>,
521 <&clk_sandbox 2>;
522 clock-names = "fixed", "i2c", "spi", "uart2", "uart1";
Simon Glass8cc4d822015-07-06 12:54:24 -0600523 };
524
Lukasz Majewski8c0709b2019-06-24 15:50:50 +0200525 ccf: clk-ccf {
526 compatible = "sandbox,clk-ccf";
527 };
528
Simon Glass507ab962021-12-04 08:56:31 -0700529 efi-media {
530 compatible = "sandbox,efi-media";
531 };
532
Simon Glass5b968632015-05-22 15:42:15 -0600533 eth@10002000 {
534 compatible = "sandbox,eth";
535 reg = <0x10002000 0x1000>;
Simon Glass5b968632015-05-22 15:42:15 -0600536 };
537
538 eth_5: eth@10003000 {
539 compatible = "sandbox,eth";
540 reg = <0x10003000 0x1000>;
Sean Anderson13652b82022-05-05 13:11:44 -0400541 nvmem-cells = <&eth5_addr>;
542 nvmem-cell-names = "mac-address";
Simon Glass5b968632015-05-22 15:42:15 -0600543 };
544
Bin Meng04a11cb2015-08-27 22:25:53 -0700545 eth_3: sbe5 {
546 compatible = "sandbox,eth";
547 reg = <0x10005000 0x1000>;
Sean Andersone2dc0e62022-05-05 13:11:42 -0400548 nvmem-cells = <&eth3_addr>;
549 nvmem-cell-names = "mac-address";
Bin Meng04a11cb2015-08-27 22:25:53 -0700550 };
551
Simon Glass5b968632015-05-22 15:42:15 -0600552 eth@10004000 {
553 compatible = "sandbox,eth";
554 reg = <0x10004000 0x1000>;
Simon Glass5b968632015-05-22 15:42:15 -0600555 };
556
Marek BehĂșnf4f1ddc2022-04-07 00:32:57 +0200557 phy_eth0: phy-test-eth {
558 compatible = "sandbox,eth";
559 reg = <0x10007000 0x1000>;
Sean Anderson24b1b8d2022-05-05 13:11:35 -0400560 mac-address = [ 02 00 11 22 33 49 ];
Marek BehĂșnf4f1ddc2022-04-07 00:32:57 +0200561 phy-handle = <&ethphy1>;
Marek BehĂșnbc194772022-04-07 00:33:01 +0200562 phy-mode = "2500base-x";
Marek BehĂșnf4f1ddc2022-04-07 00:32:57 +0200563 };
564
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800565 dsa_eth0: dsa-test-eth {
566 compatible = "sandbox,eth";
567 reg = <0x10006000 0x1000>;
Sean Anderson5768e8b2022-05-05 13:11:43 -0400568 nvmem-cells = <&eth4_addr>;
569 nvmem-cell-names = "mac-address";
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800570 };
571
572 dsa-test {
573 compatible = "sandbox,dsa";
574
575 ports {
576 #address-cells = <1>;
577 #size-cells = <0>;
578 swp_0: port@0 {
579 reg = <0>;
580 label = "lan0";
581 phy-mode = "rgmii-rxid";
582
583 fixed-link {
584 speed = <100>;
585 full-duplex;
586 };
587 };
588
589 swp_1: port@1 {
590 reg = <1>;
591 label = "lan1";
592 phy-mode = "rgmii-txid";
Bin Meng381ed972021-03-14 20:14:58 +0800593 fixed-link = <0 1 100 0 0>;
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800594 };
595
596 port@2 {
597 reg = <2>;
598 ethernet = <&dsa_eth0>;
599
600 fixed-link {
601 speed = <1000>;
602 full-duplex;
603 };
604 };
605 };
606 };
607
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700608 firmware {
609 sandbox_firmware: sandbox-firmware {
610 compatible = "sandbox,firmware";
611 };
Etienne Carriere02fd1262020-09-09 18:44:00 +0200612
Etienne Carriere09665cb2022-02-21 09:22:39 +0100613 scmi {
Etienne Carriere02fd1262020-09-09 18:44:00 +0200614 compatible = "sandbox,scmi-agent";
615 #address-cells = <1>;
616 #size-cells = <0>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200617
Etienne Carriere09665cb2022-02-21 09:22:39 +0100618 protocol@10 {
619 reg = <0x10>;
620 };
621
622 clk_scmi: protocol@14 {
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200623 reg = <0x14>;
624 #clock-cells = <1>;
625 };
Etienne Carriere8b9b6892020-09-09 18:44:07 +0200626
Etienne Carriere09665cb2022-02-21 09:22:39 +0100627 reset_scmi: protocol@16 {
Etienne Carriere8b9b6892020-09-09 18:44:07 +0200628 reg = <0x16>;
629 #reset-cells = <1>;
630 };
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100631
632 protocol@17 {
633 reg = <0x17>;
634
635 regulators {
636 #address-cells = <1>;
637 #size-cells = <0>;
638
Etienne Carriere09665cb2022-02-21 09:22:39 +0100639 regul0_scmi: reg@0 {
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100640 reg = <0>;
641 regulator-name = "sandbox-voltd0";
642 regulator-min-microvolt = <1100000>;
643 regulator-max-microvolt = <3300000>;
644 };
Etienne Carriere09665cb2022-02-21 09:22:39 +0100645 regul1_scmi: reg@1 {
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100646 reg = <0x1>;
647 regulator-name = "sandbox-voltd1";
648 regulator-min-microvolt = <1800000>;
649 };
650 };
651 };
Etienne Carriere02fd1262020-09-09 18:44:00 +0200652 };
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700653 };
654
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100655 pinctrl-gpio {
656 compatible = "sandbox,pinctrl-gpio";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700657
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100658 gpio_a: base-gpios {
659 compatible = "sandbox,gpio";
660 gpio-controller;
661 #gpio-cells = <1>;
662 gpio-bank-name = "a";
663 sandbox,gpio-count = <20>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200664 hog_input_active_low {
665 gpio-hog;
666 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200667 gpios = <10 GPIO_ACTIVE_LOW>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200668 };
669 hog_input_active_high {
670 gpio-hog;
671 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200672 gpios = <11 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200673 };
674 hog_output_low {
675 gpio-hog;
676 output-low;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200677 gpios = <12 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200678 };
679 hog_output_high {
680 gpio-hog;
681 output-high;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200682 gpios = <13 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200683 };
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100684 };
685
686 gpio_b: extra-gpios {
687 compatible = "sandbox,gpio";
688 gpio-controller;
689 #gpio-cells = <5>;
690 gpio-bank-name = "b";
691 sandbox,gpio-count = <10>;
692 };
Simon Glass25348a42014-10-13 23:42:11 -0600693
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100694 gpio_c: pinmux-gpios {
695 compatible = "sandbox,gpio";
696 gpio-controller;
697 #gpio-cells = <2>;
698 gpio-bank-name = "c";
699 sandbox,gpio-count = <10>;
700 };
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100701 };
702
Simon Glass7df766e2014-12-10 08:55:55 -0700703 i2c@0 {
704 #address-cells = <1>;
705 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600706 reg = <0 1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700707 compatible = "sandbox,i2c";
708 clock-frequency = <100000>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +0200709 pinctrl-names = "default";
710 pinctrl-0 = <&pinmux_i2c0_pins>;
711
Simon Glass7df766e2014-12-10 08:55:55 -0700712 eeprom@2c {
Sean Andersone2dc0e62022-05-05 13:11:42 -0400713 #address-cells = <1>;
714 #size-cells = <1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700715 reg = <0x2c>;
716 compatible = "i2c-eeprom";
Simon Glass17b56f62018-11-18 08:14:34 -0700717 sandbox,emul = <&emul_eeprom>;
Michal Simek4f18f922020-05-28 11:48:55 +0200718 partitions {
719 compatible = "fixed-partitions";
720 #address-cells = <1>;
721 #size-cells = <1>;
722 bootcount_i2c: bootcount@10 {
723 reg = <10 2>;
724 };
725 };
Sean Andersone2dc0e62022-05-05 13:11:42 -0400726
727 eth3_addr: mac-address@24 {
728 reg = <24 6>;
729 };
Simon Glass7df766e2014-12-10 08:55:55 -0700730 };
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200731
Simon Glass336b2952015-05-22 15:42:17 -0600732 rtc_0: rtc@43 {
Sean Anderson5768e8b2022-05-05 13:11:43 -0400733 #address-cells = <1>;
734 #size-cells = <1>;
Simon Glass336b2952015-05-22 15:42:17 -0600735 reg = <0x43>;
736 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700737 sandbox,emul = <&emul0>;
Sean Anderson5768e8b2022-05-05 13:11:43 -0400738
739 eth4_addr: mac-address@40 {
740 reg = <0x40 6>;
741 };
Simon Glass336b2952015-05-22 15:42:17 -0600742 };
743
744 rtc_1: rtc@61 {
745 reg = <0x61>;
746 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700747 sandbox,emul = <&emul1>;
748 };
749
750 i2c_emul: emul {
751 reg = <0xff>;
752 compatible = "sandbox,i2c-emul-parent";
753 emul_eeprom: emul-eeprom {
754 compatible = "sandbox,i2c-eeprom";
755 sandbox,filename = "i2c.bin";
756 sandbox,size = <256>;
757 };
758 emul0: emul0 {
Simon Glass98af3742021-02-03 06:01:17 -0700759 compatible = "sandbox,i2c-rtc-emul";
Simon Glass17b56f62018-11-18 08:14:34 -0700760 };
761 emul1: emull {
Simon Glass98af3742021-02-03 06:01:17 -0700762 compatible = "sandbox,i2c-rtc-emul";
Simon Glass336b2952015-05-22 15:42:17 -0600763 };
764 };
765
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200766 sandbox_pmic: sandbox_pmic {
767 reg = <0x40>;
Simon Glass17b56f62018-11-18 08:14:34 -0700768 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200769 };
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200770
771 mc34708: pmic@41 {
772 reg = <0x41>;
Simon Glass17b56f62018-11-18 08:14:34 -0700773 sandbox,emul = <&emul_pmic1>;
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200774 };
Simon Glass7df766e2014-12-10 08:55:55 -0700775 };
776
Philipp Tomsich1fc53302018-12-14 21:14:29 +0100777 bootcount@0 {
778 compatible = "u-boot,bootcount-rtc";
779 rtc = <&rtc_1>;
780 offset = <0x13>;
781 };
782
Michal Simek4f18f922020-05-28 11:48:55 +0200783 bootcount {
784 compatible = "u-boot,bootcount-i2c-eeprom";
785 i2c-eeprom = <&bootcount_i2c>;
786 };
787
Nandor Han88895812021-06-10 15:40:38 +0300788 bootcount_4@0 {
789 compatible = "u-boot,bootcount-syscon";
790 syscon = <&syscon0>;
791 reg = <0x0 0x04>, <0x0 0x04>;
792 reg-names = "syscon_reg", "offset";
793 };
794
795 bootcount_2@0 {
796 compatible = "u-boot,bootcount-syscon";
797 syscon = <&syscon0>;
798 reg = <0x0 0x04>, <0x0 0x02> ;
799 reg-names = "syscon_reg", "offset";
800 };
801
Marek Szyprowskiad398592021-02-18 11:33:18 +0100802 adc: adc@0 {
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100803 compatible = "sandbox,adc";
Marek Szyprowskiad398592021-02-18 11:33:18 +0100804 #io-channel-cells = <1>;
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100805 vdd-supply = <&buck2>;
806 vss-microvolts = <0>;
807 };
808
Mark Kettenis67748ee2021-10-23 16:58:02 +0200809 iommu: iommu@0 {
810 compatible = "sandbox,iommu";
811 #iommu-cells = <0>;
812 };
813
Simon Glass515dcff2020-02-06 09:55:00 -0700814 irq: irq {
Simon Glass54028bc2019-12-06 21:41:59 -0700815 compatible = "sandbox,irq";
Simon Glass515dcff2020-02-06 09:55:00 -0700816 interrupt-controller;
817 #interrupt-cells = <2>;
Simon Glass54028bc2019-12-06 21:41:59 -0700818 };
819
Simon Glass90b6fef2016-01-18 19:52:26 -0700820 lcd {
821 u-boot,dm-pre-reloc;
822 compatible = "sandbox,lcd-sdl";
Dario Binacchi20dd9e12021-04-11 09:39:50 +0200823 pinctrl-names = "default";
824 pinctrl-0 = <&pinmux_lcd_pins>;
Simon Glass90b6fef2016-01-18 19:52:26 -0700825 xres = <1366>;
826 yres = <768>;
827 };
828
Simon Glassd783eb32015-07-06 12:54:34 -0600829 leds {
830 compatible = "gpio-leds";
831
832 iracibble {
833 gpios = <&gpio_a 1 0>;
834 label = "sandbox:red";
835 };
836
837 martinet {
838 gpios = <&gpio_a 2 0>;
839 label = "sandbox:green";
840 };
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200841
842 default_on {
843 gpios = <&gpio_a 5 0>;
844 label = "sandbox:default_on";
845 default-state = "on";
846 };
847
848 default_off {
849 gpios = <&gpio_a 6 0>;
Sean Andersonfbf8d652020-09-14 11:02:03 -0400850 /* label intentionally omitted */
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200851 default-state = "off";
852 };
Simon Glassd783eb32015-07-06 12:54:34 -0600853 };
854
Paul Doelle709f0372022-07-04 09:00:25 +0000855 wdt-gpio-toggle {
Rasmus Villemoes2b673872021-08-19 11:57:05 +0200856 gpios = <&gpio_a 7 0>;
857 compatible = "linux,wdt-gpio";
Rasmus Villemoesf91ff5a2021-08-19 11:57:06 +0200858 hw_margin_ms = <100>;
Paul Doelle709f0372022-07-04 09:00:25 +0000859 hw_algo = "toggle";
860 always-running;
861 };
862
863 wdt-gpio-level {
864 gpios = <&gpio_a 7 0>;
865 compatible = "linux,wdt-gpio";
866 hw_margin_ms = <100>;
867 hw_algo = "level";
Rasmus Villemoes2b673872021-08-19 11:57:05 +0200868 always-running;
869 };
870
Stephen Warren62f2c902016-05-16 17:41:37 -0600871 mbox: mbox {
872 compatible = "sandbox,mbox";
873 #mbox-cells = <1>;
874 };
875
876 mbox-test {
877 compatible = "sandbox,mbox-test";
878 mboxes = <&mbox 100>, <&mbox 1>;
879 mbox-names = "other", "test";
880 };
881
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900882 cpus {
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +0200883 #address-cells = <1>;
884 #size-cells = <0>;
Sean Anderson79d3bba2020-09-28 10:52:23 -0400885 timebase-frequency = <2000000>;
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +0200886 cpu1: cpu@1 {
887 device_type = "cpu";
888 reg = <0x1>;
Sean Anderson79d3bba2020-09-28 10:52:23 -0400889 timebase-frequency = <3000000>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900890 compatible = "sandbox,cpu_sandbox";
891 u-boot,dm-pre-reloc;
892 };
Mario Sixdea5df72018-08-06 10:23:44 +0200893
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +0200894 cpu2: cpu@2 {
895 device_type = "cpu";
896 reg = <0x2>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900897 compatible = "sandbox,cpu_sandbox";
898 u-boot,dm-pre-reloc;
899 };
Mario Sixdea5df72018-08-06 10:23:44 +0200900
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +0200901 cpu3: cpu@3 {
902 device_type = "cpu";
903 reg = <0x3>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900904 compatible = "sandbox,cpu_sandbox";
905 u-boot,dm-pre-reloc;
906 };
Mario Sixdea5df72018-08-06 10:23:44 +0200907 };
908
Dave Gerlach75dbdfc2020-07-15 23:39:58 -0500909 chipid: chipid {
910 compatible = "sandbox,soc";
911 };
912
Simon Glassc953aaf2018-12-10 10:37:34 -0700913 i2s: i2s {
914 compatible = "sandbox,i2s";
915 #sound-dai-cells = <1>;
Simon Glass4d5814c2019-02-16 20:24:56 -0700916 sandbox,silent; /* Don't emit sounds while testing */
Simon Glassc953aaf2018-12-10 10:37:34 -0700917 };
918
Jean-Jacques Hiblotdb97c7f2019-07-05 09:33:57 +0200919 nop-test_0 {
920 compatible = "sandbox,nop_sandbox1";
921 nop-test_1 {
922 compatible = "sandbox,nop_sandbox2";
923 bind = "True";
924 };
925 nop-test_2 {
926 compatible = "sandbox,nop_sandbox2";
927 bind = "False";
928 };
929 };
930
Mario Sixa8ce0ee2018-07-31 14:24:14 +0200931 misc-test {
Sean Anderson13652b82022-05-05 13:11:44 -0400932 #address-cells = <1>;
933 #size-cells = <1>;
Mario Sixa8ce0ee2018-07-31 14:24:14 +0200934 compatible = "sandbox,misc_sandbox";
Sean Anderson13652b82022-05-05 13:11:44 -0400935
936 eth5_addr: mac-address@10 {
937 reg = <0x10 6>;
938 };
Mario Sixa8ce0ee2018-07-31 14:24:14 +0200939 };
940
Simon Glasse4fef742017-04-23 20:02:07 -0600941 mmc2 {
942 compatible = "sandbox,mmc";
Simon Glass965cd402021-07-05 16:32:58 -0600943 non-removable;
Simon Glasse4fef742017-04-23 20:02:07 -0600944 };
945
Simon Glassb255efc2022-04-24 23:31:24 -0600946 /* This is used for the bootdev tests */
Simon Glasse4fef742017-04-23 20:02:07 -0600947 mmc1 {
948 compatible = "sandbox,mmc";
Simon Glassb255efc2022-04-24 23:31:24 -0600949 filename = "mmc1.img";
Simon Glasse4fef742017-04-23 20:02:07 -0600950 };
951
Simon Glassb255efc2022-04-24 23:31:24 -0600952 /* This is used for the fastboot tests */
Simon Glasse4fef742017-04-23 20:02:07 -0600953 mmc0 {
Simon Glassd3e58e42015-07-06 12:54:32 -0600954 compatible = "sandbox,mmc";
955 };
956
Simon Glass53a68b32019-02-16 20:24:50 -0700957 pch {
958 compatible = "sandbox,pch";
959 };
960
Tom Rini4a3ca482020-02-11 12:41:23 -0500961 pci0: pci@0 {
Simon Glass3a6eae62015-03-05 12:25:34 -0700962 compatible = "sandbox,pci";
963 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500964 bus-range = <0x00 0xff>;
Simon Glass3a6eae62015-03-05 12:25:34 -0700965 #address-cells = <3>;
966 #size-cells = <2>;
Simon Glass35464f72019-09-25 08:56:08 -0600967 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glass3a6eae62015-03-05 12:25:34 -0700968 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Bin Mengcbf071b2018-08-03 01:14:39 -0700969 pci@0,0 {
970 compatible = "pci-generic";
971 reg = <0x0000 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600972 sandbox,emul = <&swap_case_emul0_0>;
Bin Mengcbf071b2018-08-03 01:14:39 -0700973 };
Alex Margineanf1274432019-06-07 11:24:24 +0300974 pci@1,0 {
975 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -0600976 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
977 reg = <0x02000814 0 0 0 0
978 0x01000810 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600979 sandbox,emul = <&swap_case_emul0_1>;
Alex Margineanf1274432019-06-07 11:24:24 +0300980 };
Simon Glass937bb472019-12-06 21:41:57 -0700981 p2sb-pci@2,0 {
982 compatible = "sandbox,p2sb";
983 reg = <0x02001010 0 0 0 0>;
984 sandbox,emul = <&p2sb_emul>;
985
986 adder {
987 intel,p2sb-port-id = <3>;
988 compatible = "sandbox,adder";
989 };
990 };
Simon Glass8c501022019-12-06 21:41:54 -0700991 pci@1e,0 {
992 compatible = "sandbox,pmc";
993 reg = <0xf000 0 0 0 0>;
994 sandbox,emul = <&pmc_emul1e>;
995 acpi-base = <0x400>;
996 gpe0-dwx-mask = <0xf>;
997 gpe0-dwx-shift-base = <4>;
998 gpe0-dw = <6 7 9>;
999 gpe0-sts = <0x20>;
1000 gpe0-en = <0x30>;
1001 };
Simon Glass3a6eae62015-03-05 12:25:34 -07001002 pci@1f,0 {
1003 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -06001004 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
1005 reg = <0x0100f810 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001006 sandbox,emul = <&swap_case_emul0_1f>;
Simon Glass3a6eae62015-03-05 12:25:34 -07001007 };
1008 };
1009
Simon Glassb98ba4c2019-09-25 08:56:10 -06001010 pci-emul0 {
1011 compatible = "sandbox,pci-emul-parent";
1012 swap_case_emul0_0: emul0@0,0 {
1013 compatible = "sandbox,swap-case";
1014 };
1015 swap_case_emul0_1: emul0@1,0 {
1016 compatible = "sandbox,swap-case";
1017 use-ea;
1018 };
1019 swap_case_emul0_1f: emul0@1f,0 {
1020 compatible = "sandbox,swap-case";
1021 };
Simon Glass937bb472019-12-06 21:41:57 -07001022 p2sb_emul: emul@2,0 {
1023 compatible = "sandbox,p2sb-emul";
1024 };
Simon Glass8c501022019-12-06 21:41:54 -07001025 pmc_emul1e: emul@1e,0 {
1026 compatible = "sandbox,pmc-emul";
1027 };
Simon Glassb98ba4c2019-09-25 08:56:10 -06001028 };
1029
Tom Rini4a3ca482020-02-11 12:41:23 -05001030 pci1: pci@1 {
Bin Meng408e5902018-08-03 01:14:41 -07001031 compatible = "sandbox,pci";
1032 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -05001033 bus-range = <0x00 0xff>;
Bin Meng408e5902018-08-03 01:14:41 -07001034 #address-cells = <3>;
1035 #size-cells = <2>;
Suneel Garapati3ac3aec2019-10-19 17:10:20 -07001036 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000 // MEM0
Andrew Scullc7456a42022-04-21 16:11:09 +00001037 0x02000000 0 0x31000000 0x3e000000 0 0x2000 // MEM1
Suneel Garapati3ac3aec2019-10-19 17:10:20 -07001038 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng5fed5362018-08-03 01:14:47 -07001039 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasute5733222018-10-10 21:27:08 +02001040 0x0c 0x00 0x1234 0x5678
1041 0x10 0x00 0x1234 0x5678>;
1042 pci@10,0 {
1043 reg = <0x8000 0 0 0 0>;
1044 };
Bin Meng408e5902018-08-03 01:14:41 -07001045 };
1046
Tom Rini4a3ca482020-02-11 12:41:23 -05001047 pci2: pci@2 {
Bin Meng510dddb2018-08-03 01:14:50 -07001048 compatible = "sandbox,pci";
1049 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -05001050 bus-range = <0x00 0xff>;
Bin Meng510dddb2018-08-03 01:14:50 -07001051 #address-cells = <3>;
1052 #size-cells = <2>;
1053 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
1054 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
1055 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
1056 pci@1f,0 {
1057 compatible = "pci-generic";
1058 reg = <0xf800 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001059 sandbox,emul = <&swap_case_emul2_1f>;
1060 };
1061 };
1062
1063 pci-emul2 {
1064 compatible = "sandbox,pci-emul-parent";
1065 swap_case_emul2_1f: emul2@1f,0 {
1066 compatible = "sandbox,swap-case";
Bin Meng510dddb2018-08-03 01:14:50 -07001067 };
1068 };
1069
Ramon Friedc64f19b2019-04-27 11:15:23 +03001070 pci_ep: pci_ep {
1071 compatible = "sandbox,pci_ep";
1072 };
1073
Simon Glass9c433fe2017-04-23 20:10:44 -06001074 probing {
1075 compatible = "simple-bus";
1076 test1 {
1077 compatible = "denx,u-boot-probe-test";
1078 };
1079
1080 test2 {
1081 compatible = "denx,u-boot-probe-test";
1082 };
1083
1084 test3 {
1085 compatible = "denx,u-boot-probe-test";
1086 };
1087
1088 test4 {
1089 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001090 first-syscon = <&syscon0>;
1091 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunayee010432019-03-07 09:57:13 +01001092 third-syscon = <&syscon2>;
Simon Glass9c433fe2017-04-23 20:10:44 -06001093 };
1094 };
1095
Stephen Warren92c67fa2016-07-13 13:45:31 -06001096 pwrdom: power-domain {
1097 compatible = "sandbox,power-domain";
1098 #power-domain-cells = <1>;
1099 };
1100
1101 power-domain-test {
1102 compatible = "sandbox,power-domain-test";
1103 power-domains = <&pwrdom 2>;
1104 };
1105
Simon Glass5620cf82018-10-01 12:22:40 -06001106 pwm: pwm {
Simon Glasse62f4be2017-04-16 21:01:11 -06001107 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -06001108 #pwm-cells = <2>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001109 pinctrl-names = "default";
1110 pinctrl-0 = <&pinmux_pwm_pins>;
Simon Glasse62f4be2017-04-16 21:01:11 -06001111 };
1112
1113 pwm2 {
1114 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -06001115 #pwm-cells = <2>;
Simon Glasse62f4be2017-04-16 21:01:11 -06001116 };
1117
Simon Glass3d355e62015-07-06 12:54:31 -06001118 ram {
1119 compatible = "sandbox,ram";
1120 };
1121
Simon Glassd860f222015-07-06 12:54:29 -06001122 reset@0 {
1123 compatible = "sandbox,warm-reset";
1124 };
1125
1126 reset@1 {
1127 compatible = "sandbox,reset";
1128 };
1129
Stephen Warren6488e642016-06-17 09:43:59 -06001130 resetc: reset-ctl {
1131 compatible = "sandbox,reset-ctl";
1132 #reset-cells = <1>;
1133 };
1134
1135 reset-ctl-test {
1136 compatible = "sandbox,reset-ctl-test";
Neil Armstrong9b4cdef2021-04-20 10:42:25 +02001137 resets = <&resetc 100>, <&resetc 2>, <&resetc 20>, <&resetc 40>;
1138 reset-names = "other", "test", "test2", "test3";
Stephen Warren6488e642016-06-17 09:43:59 -06001139 };
1140
Sughosh Ganu23e37512019-12-28 23:58:31 +05301141 rng {
1142 compatible = "sandbox,sandbox-rng";
1143 };
1144
Nishanth Menonedf85812015-09-17 15:42:41 -05001145 rproc_1: rproc@1 {
1146 compatible = "sandbox,test-processor";
1147 remoteproc-name = "remoteproc-test-dev1";
1148 };
1149
1150 rproc_2: rproc@2 {
1151 compatible = "sandbox,test-processor";
1152 internal-memory-mapped;
1153 remoteproc-name = "remoteproc-test-dev2";
1154 };
1155
Simon Glass5620cf82018-10-01 12:22:40 -06001156 panel {
1157 compatible = "simple-panel";
1158 backlight = <&backlight 0 100>;
1159 };
1160
Simon Glass509f32e2022-09-21 16:21:47 +02001161 scsi {
1162 compatible = "sandbox,scsi";
1163 sandbox,filepath = "scsi.img";
1164 };
1165
Ramon Fried26ed32e2018-07-02 02:57:59 +03001166 smem@0 {
1167 compatible = "sandbox,smem";
1168 };
1169
Simon Glass76072ac2018-12-10 10:37:36 -07001170 sound {
1171 compatible = "sandbox,sound";
1172 cpu {
1173 sound-dai = <&i2s 0>;
1174 };
1175
1176 codec {
1177 sound-dai = <&audio 0>;
1178 };
1179 };
1180
Simon Glass25348a42014-10-13 23:42:11 -06001181 spi@0 {
1182 #address-cells = <1>;
1183 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -06001184 reg = <0 1>;
Simon Glass25348a42014-10-13 23:42:11 -06001185 compatible = "sandbox,spi";
Ovidiu Panaitae734732020-12-14 19:06:47 +02001186 cs-gpios = <0>, <0>, <&gpio_a 0>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001187 pinctrl-names = "default";
1188 pinctrl-0 = <&pinmux_spi0_pins>;
1189
Simon Glass25348a42014-10-13 23:42:11 -06001190 spi.bin@0 {
1191 reg = <0>;
Neil Armstronga009fa72019-02-10 10:16:20 +00001192 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass25348a42014-10-13 23:42:11 -06001193 spi-max-frequency = <40000000>;
1194 sandbox,filename = "spi.bin";
1195 };
Ovidiu Panaitae734732020-12-14 19:06:47 +02001196 spi.bin@1 {
1197 reg = <1>;
1198 compatible = "spansion,m25p16", "jedec,spi-nor";
1199 spi-max-frequency = <50000000>;
1200 sandbox,filename = "spi.bin";
1201 spi-cpol;
1202 spi-cpha;
1203 };
Simon Glass25348a42014-10-13 23:42:11 -06001204 };
1205
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001206 syscon0: syscon@0 {
Simon Glasscd556522015-07-06 12:54:35 -06001207 compatible = "sandbox,syscon0";
Mario Sixe3f59f42018-10-04 09:00:40 +02001208 reg = <0x10 16>;
Simon Glasscd556522015-07-06 12:54:35 -06001209 };
1210
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001211 another_system_controller: syscon@1 {
Simon Glasscd556522015-07-06 12:54:35 -06001212 compatible = "sandbox,syscon1";
Simon Glasscf61f742015-07-06 12:54:36 -06001213 reg = <0x20 5
1214 0x28 6
1215 0x30 7
1216 0x38 8>;
Simon Glasscd556522015-07-06 12:54:35 -06001217 };
1218
Patrick Delaunayee010432019-03-07 09:57:13 +01001219 syscon2: syscon@2 {
Masahiro Yamada42ab1072018-04-23 13:26:53 +09001220 compatible = "simple-mfd", "syscon";
1221 reg = <0x40 5
1222 0x48 6
1223 0x50 7
1224 0x58 8>;
1225 };
1226
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +05301227 syscon3: syscon@3 {
1228 compatible = "simple-mfd", "syscon";
1229 reg = <0x000100 0x10>;
1230
1231 muxcontroller0: a-mux-controller {
1232 compatible = "mmio-mux";
1233 #mux-control-cells = <1>;
1234
1235 mux-reg-masks = <0x0 0x30>, /* 0: reg 0x0, bits 5:4 */
1236 <0xc 0x1E>, /* 1: reg 0xc, bits 4:1 */
1237 <0x4 0xFF>; /* 2: reg 0x4, bits 7:0 */
1238 idle-states = <MUX_IDLE_AS_IS>, <0x02>, <0x73>;
1239 u-boot,mux-autoprobe;
1240 };
1241 };
1242
1243 muxcontroller1: emul-mux-controller {
1244 compatible = "mux-emul";
1245 #mux-control-cells = <0>;
1246 u-boot,mux-autoprobe;
1247 idle-state = <0xabcd>;
1248 };
1249
Simon Glass791a17f2020-12-16 21:20:27 -07001250 testfdtm0 {
1251 compatible = "denx,u-boot-fdtm-test";
1252 };
1253
1254 testfdtm1: testfdtm1 {
1255 compatible = "denx,u-boot-fdtm-test";
1256 };
1257
1258 testfdtm2 {
1259 compatible = "denx,u-boot-fdtm-test";
1260 };
1261
Sean Anderson79d3bba2020-09-28 10:52:23 -04001262 timer@0 {
Thomas Chou6f2cfbf2015-12-11 16:27:34 +08001263 compatible = "sandbox,timer";
1264 clock-frequency = <1000000>;
1265 };
1266
Sean Anderson79d3bba2020-09-28 10:52:23 -04001267 timer@1 {
1268 compatible = "sandbox,timer";
1269 sandbox,timebase-frequency-fallback;
1270 };
1271
Miquel Raynal80938c12018-05-15 11:57:27 +02001272 tpm2 {
1273 compatible = "sandbox,tpm2";
1274 };
1275
Simon Glass5b968632015-05-22 15:42:15 -06001276 uart0: serial {
1277 compatible = "sandbox,serial";
1278 u-boot,dm-pre-reloc;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001279 pinctrl-names = "default";
1280 pinctrl-0 = <&pinmux_uart0_pins>;
Joe Hershberger4c197242015-03-22 17:09:15 -05001281 };
1282
Simon Glass31680482015-03-25 12:23:05 -06001283 usb_0: usb@0 {
1284 compatible = "sandbox,usb";
1285 status = "disabled";
1286 hub {
1287 compatible = "sandbox,usb-hub";
1288 #address-cells = <1>;
1289 #size-cells = <0>;
1290 flash-stick {
1291 reg = <0>;
1292 compatible = "sandbox,usb-flash";
1293 };
1294 };
1295 };
1296
1297 usb_1: usb@1 {
1298 compatible = "sandbox,usb";
Mark Kettenis67748ee2021-10-23 16:58:02 +02001299 iommus = <&iommu>;
Simon Glass31680482015-03-25 12:23:05 -06001300 hub {
1301 compatible = "usb-hub";
1302 usb,device-class = <9>;
Michael Walle7c961322020-06-02 01:47:07 +02001303 #address-cells = <1>;
1304 #size-cells = <0>;
Simon Glass31680482015-03-25 12:23:05 -06001305 hub-emul {
1306 compatible = "sandbox,usb-hub";
1307 #address-cells = <1>;
1308 #size-cells = <0>;
Simon Glass4700fe52015-11-08 23:48:01 -07001309 flash-stick@0 {
Simon Glass31680482015-03-25 12:23:05 -06001310 reg = <0>;
1311 compatible = "sandbox,usb-flash";
1312 sandbox,filepath = "testflash.bin";
1313 };
1314
Simon Glass4700fe52015-11-08 23:48:01 -07001315 flash-stick@1 {
1316 reg = <1>;
1317 compatible = "sandbox,usb-flash";
1318 sandbox,filepath = "testflash1.bin";
1319 };
1320
1321 flash-stick@2 {
1322 reg = <2>;
1323 compatible = "sandbox,usb-flash";
1324 sandbox,filepath = "testflash2.bin";
1325 };
1326
Simon Glassc0ccc722015-11-08 23:48:08 -07001327 keyb@3 {
1328 reg = <3>;
1329 compatible = "sandbox,usb-keyb";
1330 };
1331
Simon Glass31680482015-03-25 12:23:05 -06001332 };
Michael Walle7c961322020-06-02 01:47:07 +02001333
1334 usbstor@1 {
1335 reg = <1>;
1336 };
1337 usbstor@3 {
1338 reg = <3>;
1339 };
Simon Glass31680482015-03-25 12:23:05 -06001340 };
1341 };
1342
1343 usb_2: usb@2 {
1344 compatible = "sandbox,usb";
1345 status = "disabled";
1346 };
1347
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001348 spmi: spmi@0 {
1349 compatible = "sandbox,spmi";
1350 #address-cells = <0x1>;
1351 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -06001352 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001353 pm8916@0 {
1354 compatible = "qcom,spmi-pmic";
1355 reg = <0x0 0x1>;
1356 #address-cells = <0x1>;
1357 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -06001358 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001359
1360 spmi_gpios: gpios@c000 {
1361 compatible = "qcom,pm8916-gpio";
1362 reg = <0xc000 0x400>;
1363 gpio-controller;
1364 gpio-count = <4>;
1365 #gpio-cells = <2>;
1366 gpio-bank-name="spmi";
1367 };
1368 };
1369 };
maxims@google.comdaea6d42017-04-17 12:00:21 -07001370
1371 wdt0: wdt@0 {
1372 compatible = "sandbox,wdt";
Rasmus Villemoesf91ff5a2021-08-19 11:57:06 +02001373 hw_margin_ms = <200>;
maxims@google.comdaea6d42017-04-17 12:00:21 -07001374 };
Rob Clarka471b672018-01-10 11:33:30 +01001375
Mario Six95922152018-08-09 14:51:19 +02001376 axi: axi@0 {
1377 compatible = "sandbox,axi";
1378 #address-cells = <0x1>;
1379 #size-cells = <0x1>;
1380 store@0 {
1381 compatible = "sandbox,sandbox_store";
1382 reg = <0x0 0x400>;
1383 };
1384 };
1385
Rob Clarka471b672018-01-10 11:33:30 +01001386 chosen {
Simon Glass305ac9a2018-02-03 10:36:58 -07001387 #address-cells = <1>;
1388 #size-cells = <1>;
Simon Glassf3455962020-01-27 08:49:43 -07001389 setting = "sunrise ohoka";
1390 other-node = "/some-bus/c-test@5";
Simon Glasse09223c2020-01-27 08:49:46 -07001391 int-values = <0x1937 72993>;
Simon Glass3c601b12020-07-07 13:12:06 -06001392 u-boot,acpi-ssdt-order = <&acpi_test2 &acpi_test1>;
Rob Clarka471b672018-01-10 11:33:30 +01001393 chosen-test {
1394 compatible = "denx,u-boot-fdt-test";
1395 reg = <9 1>;
1396 };
Simon Glassc8d37212022-07-30 15:52:34 -06001397
1398 fwupd {
1399 compatible = "simple-bus";
1400 firmware0 {
1401 compatible = "fwupd,vbe-simple";
1402 storage = "mmc1";
1403 area-start = <0x400>;
1404 area-size = <0x1000>;
1405 skip-offset = <0x200>;
1406 state-offset = <0x400>;
1407 state-size = <0x40>;
1408 version-offset = <0x800>;
1409 version-size = <0x100>;
1410 };
1411 };
Rob Clarka471b672018-01-10 11:33:30 +01001412 };
Mario Six35616ef2018-03-12 14:53:33 +01001413
1414 translation-test@8000 {
1415 compatible = "simple-bus";
1416 reg = <0x8000 0x4000>;
1417
1418 #address-cells = <0x2>;
1419 #size-cells = <0x1>;
1420
1421 ranges = <0 0x0 0x8000 0x1000
1422 1 0x100 0x9000 0x1000
1423 2 0x200 0xA000 0x1000
1424 3 0x300 0xB000 0x1000
1425 >;
1426
Fabien Dessenne22236e02019-05-31 15:11:30 +02001427 dma-ranges = <0 0x000 0x10000000 0x1000
1428 1 0x100 0x20000000 0x1000
1429 >;
1430
Mario Six35616ef2018-03-12 14:53:33 +01001431 dev@0,0 {
1432 compatible = "denx,u-boot-fdt-dummy";
1433 reg = <0 0x0 0x1000>;
Álvaro Fernåndez Rojasa3181152018-12-03 19:37:09 +01001434 reg-names = "sandbox-dummy-0";
Mario Six35616ef2018-03-12 14:53:33 +01001435 };
1436
1437 dev@1,100 {
1438 compatible = "denx,u-boot-fdt-dummy";
1439 reg = <1 0x100 0x1000>;
1440
1441 };
1442
1443 dev@2,200 {
1444 compatible = "denx,u-boot-fdt-dummy";
1445 reg = <2 0x200 0x1000>;
1446 };
1447
1448
1449 noxlatebus@3,300 {
1450 compatible = "simple-bus";
1451 reg = <3 0x300 0x1000>;
1452
1453 #address-cells = <0x1>;
1454 #size-cells = <0x0>;
1455
1456 dev@42 {
1457 compatible = "denx,u-boot-fdt-dummy";
1458 reg = <0x42>;
1459 };
1460 };
1461 };
Mario Six02ad6fb2018-09-27 09:19:31 +02001462
1463 osd {
1464 compatible = "sandbox,sandbox_osd";
1465 };
Tom Rinib93eea72018-09-30 18:16:51 -04001466
Jens Wiklander86afaa62018-09-25 16:40:16 +02001467 sandbox_tee {
1468 compatible = "sandbox,tee";
1469 };
Bin Meng1bb290d2018-10-15 02:21:26 -07001470
1471 sandbox_virtio1 {
1472 compatible = "sandbox,virtio1";
1473 };
1474
1475 sandbox_virtio2 {
1476 compatible = "sandbox,virtio2";
1477 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001478
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +02001479 sandbox_scmi {
1480 compatible = "sandbox,scmi-devices";
Etienne Carrierebf1f1322022-02-21 09:22:41 +01001481 clocks = <&clk_scmi 2>, <&clk_scmi 0>;
Etienne Carriere09665cb2022-02-21 09:22:39 +01001482 resets = <&reset_scmi 3>;
1483 regul0-supply = <&regul0_scmi>;
1484 regul1-supply = <&regul1_scmi>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +02001485 };
1486
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001487 pinctrl {
1488 compatible = "sandbox,pinctrl";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001489
Sean Anderson3438e3b2020-09-14 11:01:57 -04001490 pinctrl-names = "default", "alternate";
1491 pinctrl-0 = <&pinctrl_gpios>, <&pinctrl_i2s>;
1492 pinctrl-1 = <&pinctrl_spi>, <&pinctrl_i2c>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001493
Sean Anderson3438e3b2020-09-14 11:01:57 -04001494 pinctrl_gpios: gpios {
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001495 gpio0 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001496 pins = "P5";
1497 function = "GPIO";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001498 bias-pull-up;
1499 input-disable;
1500 };
1501 gpio1 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001502 pins = "P6";
1503 function = "GPIO";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001504 output-high;
1505 drive-open-drain;
1506 };
1507 gpio2 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001508 pinmux = <SANDBOX_PINMUX(7, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001509 bias-pull-down;
1510 input-enable;
1511 };
1512 gpio3 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001513 pinmux = <SANDBOX_PINMUX(8, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001514 bias-disable;
1515 };
1516 };
Sean Anderson3438e3b2020-09-14 11:01:57 -04001517
1518 pinctrl_i2c: i2c {
1519 groups {
1520 groups = "I2C_UART";
1521 function = "I2C";
1522 };
1523
1524 pins {
1525 pins = "P0", "P1";
1526 drive-open-drain;
1527 };
1528 };
1529
1530 pinctrl_i2s: i2s {
1531 groups = "SPI_I2S";
1532 function = "I2S";
1533 };
1534
1535 pinctrl_spi: spi {
1536 groups = "SPI_I2S";
1537 function = "SPI";
1538
1539 cs {
1540 pinmux = <SANDBOX_PINMUX(5, SANDBOX_PINMUX_CS)>,
1541 <SANDBOX_PINMUX(6, SANDBOX_PINMUX_CS)>;
1542 };
1543 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001544 };
Benjamin Gaignarda550b542018-11-27 13:49:50 +01001545
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001546 pinctrl-single-no-width {
1547 compatible = "pinctrl-single";
1548 reg = <0x0000 0x238>;
1549 #pinctrl-cells = <1>;
1550 pinctrl-single,function-mask = <0x7f>;
1551 };
1552
1553 pinctrl-single-pins {
1554 compatible = "pinctrl-single";
1555 reg = <0x0000 0x238>;
1556 #pinctrl-cells = <1>;
1557 pinctrl-single,register-width = <32>;
1558 pinctrl-single,function-mask = <0x7f>;
1559
1560 pinmux_pwm_pins: pinmux_pwm_pins {
1561 pinctrl-single,pins = < 0x48 0x06 >;
1562 };
1563
1564 pinmux_spi0_pins: pinmux_spi0_pins {
1565 pinctrl-single,pins = <
1566 0x190 0x0c
1567 0x194 0x0c
1568 0x198 0x23
1569 0x19c 0x0c
1570 >;
1571 };
1572
1573 pinmux_uart0_pins: pinmux_uart0_pins {
1574 pinctrl-single,pins = <
1575 0x70 0x30
1576 0x74 0x00
1577 >;
1578 };
1579 };
1580
1581 pinctrl-single-bits {
1582 compatible = "pinctrl-single";
1583 reg = <0x0000 0x50>;
1584 #pinctrl-cells = <2>;
1585 pinctrl-single,bit-per-mux;
1586 pinctrl-single,register-width = <32>;
1587 pinctrl-single,function-mask = <0xf>;
1588
1589 pinmux_i2c0_pins: pinmux_i2c0_pins {
1590 pinctrl-single,bits = <
1591 0x10 0x00002200 0x0000ff00
1592 >;
1593 };
1594
1595 pinmux_lcd_pins: pinmux_lcd_pins {
1596 pinctrl-single,bits = <
1597 0x40 0x22222200 0xffffff00
1598 0x44 0x22222222 0xffffffff
1599 0x48 0x00000022 0x000000ff
1600 0x48 0x02000000 0x0f000000
1601 0x4c 0x02000022 0x0f0000ff
1602 >;
1603 };
1604 };
1605
Benjamin Gaignarda550b542018-11-27 13:49:50 +01001606 hwspinlock@0 {
1607 compatible = "sandbox,hwspinlock";
1608 };
Grygorii Strashko19ebf0b2018-11-28 19:17:51 +01001609
1610 dma: dma {
1611 compatible = "sandbox,dma";
1612 #dma-cells = <1>;
1613
1614 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
1615 dma-names = "m2m", "tx0", "rx0";
1616 };
Alex Marginean0daa53a2019-06-03 19:12:28 +03001617
Alex Marginean0649be52019-07-12 10:13:53 +03001618 /*
1619 * keep mdio-mux ahead of mdio so that the mux is removed first at the
1620 * end of the test. If parent mdio is removed first, clean-up of the
1621 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
1622 * active at the end of the test. That it turn doesn't allow the mdio
1623 * class to be destroyed, triggering an error.
1624 */
1625 mdio-mux-test {
1626 compatible = "sandbox,mdio-mux";
1627 #address-cells = <1>;
1628 #size-cells = <0>;
1629 mdio-parent-bus = <&mdio>;
1630
1631 mdio-ch-test@0 {
1632 reg = <0>;
1633 };
1634 mdio-ch-test@1 {
1635 reg = <1>;
1636 };
1637 };
1638
1639 mdio: mdio-test {
Alex Marginean0daa53a2019-06-03 19:12:28 +03001640 compatible = "sandbox,mdio";
Marek BehĂșnf4f1ddc2022-04-07 00:32:57 +02001641 #address-cells = <1>;
1642 #size-cells = <0>;
1643
1644 ethphy1: ethernet-phy@1 {
1645 reg = <1>;
1646 };
Alex Marginean0daa53a2019-06-03 19:12:28 +03001647 };
Sean Andersonb7860542020-06-24 06:41:12 -04001648
1649 pm-bus-test {
1650 compatible = "simple-pm-bus";
1651 clocks = <&clk_sandbox 4>;
1652 power-domains = <&pwrdom 1>;
1653 };
Sean Anderson0c1f6bf2020-06-24 06:41:14 -04001654
1655 resetc2: syscon-reset {
1656 compatible = "syscon-reset";
1657 #reset-cells = <1>;
1658 regmap = <&syscon0>;
1659 offset = <1>;
1660 mask = <0x27FFFFFF>;
1661 assert-high = <0>;
1662 };
1663
1664 syscon-reset-test {
1665 compatible = "sandbox,misc_sandbox";
1666 resets = <&resetc2 15>, <&resetc2 30>, <&resetc2 60>;
1667 reset-names = "valid", "no_mask", "out_of_range";
1668 };
Jean-Jacques Hiblot0b89fc52020-09-24 10:04:18 +05301669
Simon Glass458b66a2020-11-05 06:32:05 -07001670 sysinfo {
1671 compatible = "sandbox,sysinfo-sandbox";
1672 };
1673
Sean Anderson1c830672021-04-20 10:50:58 -04001674 sysinfo-gpio {
1675 compatible = "gpio-sysinfo";
1676 gpios = <&gpio_a 15>, <&gpio_a 16>, <&gpio_a 17>;
1677 revisions = <19>, <5>;
1678 names = "rev_a", "foo";
1679 };
1680
Jean-Jacques Hiblot0b89fc52020-09-24 10:04:18 +05301681 some_regmapped-bus {
1682 #address-cells = <0x1>;
1683 #size-cells = <0x1>;
1684
1685 ranges = <0x0 0x0 0x10>;
1686 compatible = "simple-bus";
1687
1688 regmap-test_0 {
1689 reg = <0 0x10>;
1690 compatible = "sandbox,regmap_test";
1691 };
1692 };
Simon Glassb2c1cac2014-02-26 15:59:21 -07001693};
Przemyslaw Marczak77bee052015-05-13 13:38:35 +02001694
1695#include "sandbox_pmic.dtsi"
Heinrich Schuchardte24fdef2021-02-18 13:01:35 +01001696#include "cros-ec-keyboard.dtsi"