Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 1 | if ARCH_STM32MP |
| 2 | |
| 3 | config SPL |
Patrick Delaunay | 4c5821d | 2020-07-24 11:13:31 +0200 | [diff] [blame] | 4 | select SPL_BOARD_INIT |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 5 | select SPL_CLK |
| 6 | select SPL_DM |
| 7 | select SPL_DM_SEQ_ALIAS |
Simon Glass | 284cb9c | 2021-07-10 21:14:31 -0600 | [diff] [blame] | 8 | select SPL_DRIVERS_MISC |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 9 | select SPL_FRAMEWORK |
Simon Glass | 035939e | 2021-07-10 21:14:30 -0600 | [diff] [blame] | 10 | select SPL_GPIO |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 11 | select SPL_LIBCOMMON_SUPPORT |
| 12 | select SPL_LIBGENERIC_SUPPORT |
| 13 | select SPL_OF_CONTROL |
| 14 | select SPL_OF_TRANSLATE |
| 15 | select SPL_PINCTRL |
| 16 | select SPL_REGMAP |
Ley Foon Tan | 9caf712 | 2018-06-14 18:45:19 +0800 | [diff] [blame] | 17 | select SPL_DM_RESET |
Simon Glass | f4d6039 | 2021-08-08 12:20:12 -0600 | [diff] [blame] | 18 | select SPL_SERIAL |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 19 | select SPL_SYSCON |
Simon Glass | 1ba1d4e | 2021-07-10 21:14:28 -0600 | [diff] [blame] | 20 | select SPL_WATCHDOG if WATCHDOG |
Patrick Delaunay | f860020 | 2019-04-18 17:32:47 +0200 | [diff] [blame] | 21 | imply BOOTSTAGE_STASH if SPL_BOOTSTAGE |
| 22 | imply SPL_BOOTSTAGE if BOOTSTAGE |
Patrick Delaunay | aa4e685 | 2019-02-27 17:01:14 +0100 | [diff] [blame] | 23 | imply SPL_DISPLAY_PRINT |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 24 | imply SPL_LIBDISK_SUPPORT |
Simon Glass | a582047 | 2021-08-08 12:20:14 -0600 | [diff] [blame] | 25 | imply SPL_SPI_LOAD if SPL_SPI |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 26 | |
| 27 | config SYS_SOC |
| 28 | default "stm32mp" |
| 29 | |
Patrick Delaunay | 7e517c6 | 2019-04-18 17:32:36 +0200 | [diff] [blame] | 30 | config SYS_MALLOC_LEN |
| 31 | default 0x2000000 |
| 32 | |
Patrick Delaunay | 088b676 | 2019-04-18 17:32:37 +0200 | [diff] [blame] | 33 | config ENV_SIZE |
Patrice Chotard | d83bba4 | 2019-05-07 18:40:47 +0200 | [diff] [blame] | 34 | default 0x2000 |
Patrick Delaunay | 088b676 | 2019-04-18 17:32:37 +0200 | [diff] [blame] | 35 | |
Patrick Delaunay | 310aa8a | 2020-01-13 15:17:42 +0100 | [diff] [blame] | 36 | config STM32MP15x |
| 37 | bool "Support STMicroelectronics STM32MP15x Soc" |
Patrick Delaunay | 196b7db | 2021-10-11 09:52:49 +0200 | [diff] [blame] | 38 | select ARCH_SUPPORT_PSCI |
Patrick Delaunay | 1e2a9b7 | 2021-10-13 15:11:18 +0200 | [diff] [blame] | 39 | select BINMAN |
Lokesh Vutla | 81b1a67 | 2018-04-26 18:21:26 +0530 | [diff] [blame] | 40 | select CPU_V7A |
Patrick Delaunay | 196b7db | 2021-10-11 09:52:49 +0200 | [diff] [blame] | 41 | select CPU_V7_HAS_NONSEC |
Patrick Delaunay | e020737 | 2018-04-16 10:13:24 +0200 | [diff] [blame] | 42 | select CPU_V7_HAS_VIRT |
Patrice Chotard | df29081 | 2022-01-20 08:19:15 +0100 | [diff] [blame] | 43 | select OF_BOARD if TFABOOT |
Patrick Delaunay | de98cbf | 2019-07-02 13:26:07 +0200 | [diff] [blame] | 44 | select OF_BOARD_SETUP |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 45 | select PINCTRL_STM32 |
Patrick Delaunay | b139a5b | 2018-07-09 15:17:20 +0200 | [diff] [blame] | 46 | select STM32_RCC |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 47 | select STM32_RESET |
Patrick Delaunay | 4368e56 | 2019-07-30 19:16:25 +0200 | [diff] [blame] | 48 | select STM32_SERIAL |
Patrick Delaunay | efd00f3 | 2022-05-20 18:24:40 +0200 | [diff] [blame] | 49 | select SUPPORT_SPL |
Andre Przywara | 7b16925 | 2018-04-12 04:24:46 +0300 | [diff] [blame] | 50 | select SYS_ARCH_TIMER |
Patrick Delaunay | 59d0da1 | 2020-07-02 17:43:45 +0200 | [diff] [blame] | 51 | imply CMD_NVEDIT_INFO |
Patrick Delaunay | 310aa8a | 2020-01-13 15:17:42 +0100 | [diff] [blame] | 52 | help |
| 53 | support of STMicroelectronics SOC STM32MP15x family |
| 54 | STM32MP157, STM32MP153 or STM32MP151 |
| 55 | STMicroelectronics MPU with core ARMv7 |
| 56 | dual core A7 for STM32MP157/3, monocore for STM32MP151 |
| 57 | target all the STMicroelectronics board with SOC STM32MP1 family |
| 58 | |
Patrick Delaunay | ba4b8b0 | 2021-07-26 11:21:34 +0200 | [diff] [blame] | 59 | config STM32MP15x_STM32IMAGE |
| 60 | bool "Support STM32 image for generated U-Boot image" |
| 61 | depends on STM32MP15x && TFABOOT |
| 62 | help |
| 63 | Support of STM32 image generation for SOC STM32MP15x |
| 64 | for TF-A boot when FIP container is not used |
| 65 | |
Patrick Delaunay | 310aa8a | 2020-01-13 15:17:42 +0100 | [diff] [blame] | 66 | choice |
| 67 | prompt "STM32MP15x board select" |
| 68 | optional |
| 69 | |
| 70 | config TARGET_ST_STM32MP15x |
| 71 | bool "STMicroelectronics STM32MP15x boards" |
| 72 | select STM32MP15x |
Patrick Delaunay | 66111eb | 2020-03-10 10:15:03 +0100 | [diff] [blame] | 73 | imply BOOTSTAGE |
Patrick Delaunay | 66111eb | 2020-03-10 10:15:03 +0100 | [diff] [blame] | 74 | imply CMD_BOOTSTAGE |
Patrick Delaunay | f97beae | 2019-12-03 09:38:58 +0100 | [diff] [blame] | 75 | imply CMD_CLS if CMD_BMP |
Patrick Delaunay | 28a4609 | 2019-07-30 19:16:26 +0200 | [diff] [blame] | 76 | imply DISABLE_CONSOLE |
Patrick Delaunay | fcb4991 | 2019-07-30 19:16:23 +0200 | [diff] [blame] | 77 | imply PRE_CONSOLE_BUFFER |
Patrick Delaunay | 887d9e4 | 2019-07-30 19:16:22 +0200 | [diff] [blame] | 78 | imply SILENT_CONSOLE |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 79 | help |
Patrick Delaunay | 310aa8a | 2020-01-13 15:17:42 +0100 | [diff] [blame] | 80 | target the STMicroelectronics board with SOC STM32MP15x |
| 81 | managed by board/st/stm32mp1: |
| 82 | Evalulation board (EV1) or Discovery board (DK1 and DK2). |
| 83 | The difference between board are managed with devicetree |
| 84 | |
Jagan Teki | 6cd3dc9 | 2021-03-16 21:52:06 +0530 | [diff] [blame] | 85 | config TARGET_MICROGEA_STM32MP1 |
| 86 | bool "Engicam MicroGEA STM32MP1 SOM" |
| 87 | select STM32MP15x |
Jagan Teki | 6cd3dc9 | 2021-03-16 21:52:06 +0530 | [diff] [blame] | 88 | imply BOOTSTAGE |
Jagan Teki | 6cd3dc9 | 2021-03-16 21:52:06 +0530 | [diff] [blame] | 89 | imply CMD_BOOTSTAGE |
| 90 | imply CMD_CLS if CMD_BMP |
| 91 | imply DISABLE_CONSOLE |
| 92 | imply PRE_CONSOLE_BUFFER |
| 93 | imply SILENT_CONSOLE |
| 94 | help |
| 95 | MicroGEA STM32MP1 is a STM32MP157A based Micro SOM. |
| 96 | |
| 97 | MicroGEA STM32MP1 MicroDev 2.0: |
| 98 | * MicroDev 2.0 is a general purpose miniature carrier board with CAN, |
| 99 | LTE and LVDS panel interfaces. |
| 100 | * MicroGEA STM32MP1 needs to mount on top of this MicroDev 2.0 board |
| 101 | for creating complete MicroGEA STM32MP1 MicroDev 2.0 Carrier board. |
| 102 | |
Jagan Teki | 46f44b5 | 2021-03-16 21:52:07 +0530 | [diff] [blame] | 103 | MicroGEA STM32MP1 MicroDev 2.0 7" OF: |
| 104 | * 7" OF is a capacitive touch 7" Open Frame panel solutions with LVDS |
| 105 | panel and toucscreen. |
| 106 | * MicroGEA STM32MP1 needs to mount on top of MicroDev 2.0 board with |
| 107 | pluged 7" OF for creating complete MicroGEA STM32MP1 MicroDev 2.0 7" |
| 108 | Open Frame Solution board. |
| 109 | |
Jagan Teki | c0f218b | 2021-03-16 21:52:03 +0530 | [diff] [blame] | 110 | config TARGET_ICORE_STM32MP1 |
| 111 | bool "Engicam i.Core STM32MP1 SOM" |
| 112 | select STM32MP15x |
Jagan Teki | c0f218b | 2021-03-16 21:52:03 +0530 | [diff] [blame] | 113 | imply BOOTSTAGE |
Jagan Teki | c0f218b | 2021-03-16 21:52:03 +0530 | [diff] [blame] | 114 | imply CMD_BOOTSTAGE |
| 115 | imply CMD_CLS if CMD_BMP |
| 116 | imply DISABLE_CONSOLE |
| 117 | imply PRE_CONSOLE_BUFFER |
| 118 | imply SILENT_CONSOLE |
| 119 | help |
| 120 | i.Core STM32MP1 is an EDIMM SOM based on STM32MP157A. |
| 121 | |
| 122 | i.Core STM32MP1 EDIMM2.2: |
| 123 | * EDIMM2.2 is a Form Factor Capacitive Evaluation Board. |
| 124 | * i.Core STM32MP1 needs to mount on top of EDIMM2.2 for |
| 125 | creating complete i.Core STM32MP1 EDIMM2.2 Starter Kit. |
| 126 | |
Jagan Teki | 4259785 | 2021-03-16 21:52:04 +0530 | [diff] [blame] | 127 | i.Core STM32MP1 C.TOUCH 2.0 |
| 128 | * C.TOUCH 2.0 is a general purpose Carrier board. |
| 129 | * i.Core STM32MP1 needs to mount on top of this Carrier board |
| 130 | for creating complete i.Core STM32MP1 C.TOUCH 2.0 board. |
| 131 | |
Marek Vasut | 5ff0529 | 2020-01-24 18:39:16 +0100 | [diff] [blame] | 132 | config TARGET_DH_STM32MP1_PDK2 |
| 133 | bool "DH STM32MP1 PDK2" |
| 134 | select STM32MP15x |
Marek Vasut | 5ff0529 | 2020-01-24 18:39:16 +0100 | [diff] [blame] | 135 | help |
| 136 | Target the DH PDK2 development kit with STM32MP15x SoM. |
| 137 | |
Patrick Delaunay | 310aa8a | 2020-01-13 15:17:42 +0100 | [diff] [blame] | 138 | endchoice |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 139 | |
| 140 | config SYS_TEXT_BASE |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 141 | default 0xC0100000 |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 142 | |
Patrick Delaunay | 6d3cbf3 | 2019-02-27 17:01:15 +0100 | [diff] [blame] | 143 | config NR_DRAM_BANKS |
| 144 | default 1 |
| 145 | |
Patrick Delaunay | ab7d644 | 2020-09-04 12:55:19 +0200 | [diff] [blame] | 146 | config DDR_CACHEABLE_SIZE |
| 147 | hex "Size of the DDR marked cacheable in pre-reloc stage" |
Patrick Delaunay | ab7d644 | 2020-09-04 12:55:19 +0200 | [diff] [blame] | 148 | default 0x40000000 |
| 149 | help |
| 150 | Define the size of the DDR marked as cacheable in U-Boot |
| 151 | pre-reloc stage. |
| 152 | This option can be useful to avoid speculatif access |
| 153 | to secured area of DDR used by TF-A or OP-TEE before U-Boot |
| 154 | initialization. |
| 155 | The areas marked "no-map" in device tree should be located |
| 156 | before this limit: STM32_DDR_BASE + DDR_CACHEABLE_SIZE. |
| 157 | |
Patrick Delaunay | fc69c68 | 2018-03-20 10:54:54 +0100 | [diff] [blame] | 158 | config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_MMC2 |
| 159 | hex "Partition on MMC2 to use to load U-Boot from" |
| 160 | depends on SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION |
| 161 | default 1 |
| 162 | help |
| 163 | Partition on the second MMC to load U-Boot from when the MMC is being |
| 164 | used in raw mode |
| 165 | |
Patrick Delaunay | 43f214c | 2019-07-05 17:20:15 +0200 | [diff] [blame] | 166 | config STM32_ETZPC |
| 167 | bool "STM32 Extended TrustZone Protection" |
Patrick Delaunay | 3a6e387 | 2020-03-10 16:05:43 +0100 | [diff] [blame] | 168 | depends on STM32MP15x |
Patrick Delaunay | 43f214c | 2019-07-05 17:20:15 +0200 | [diff] [blame] | 169 | default y |
Simon Glass | 1c38374 | 2021-12-18 11:27:51 -0700 | [diff] [blame] | 170 | imply BOOTP_SERVERIP |
Patrick Delaunay | 43f214c | 2019-07-05 17:20:15 +0200 | [diff] [blame] | 171 | help |
| 172 | Say y to enable STM32 Extended TrustZone Protection |
| 173 | |
Alexandru Gagniuc | 31aa697 | 2021-07-29 11:47:17 -0500 | [diff] [blame] | 174 | config STM32_ECDSA_VERIFY |
| 175 | bool "STM32 ECDSA verification via the ROM API" |
| 176 | depends on SPL_ECDSA_VERIFY |
| 177 | default y |
| 178 | help |
| 179 | Say y to enable the uclass driver for ECDSA verification using the |
| 180 | ROM API provided on STM32MP. |
| 181 | The ROM API is only available during SPL for now. |
| 182 | |
Patrick Delaunay | 109d13f | 2019-07-05 17:20:17 +0200 | [diff] [blame] | 183 | config CMD_STM32KEY |
| 184 | bool "command stm32key to fuse public key hash" |
Patrick Delaunay | 109d13f | 2019-07-05 17:20:17 +0200 | [diff] [blame] | 185 | help |
| 186 | fuse public key hash in corresponding fuse used to authenticate |
| 187 | binary. |
Patrick Delaunay | d6c098a | 2021-06-28 14:55:57 +0200 | [diff] [blame] | 188 | This command is used to evaluate the secure boot on stm32mp SOC, |
| 189 | it is deactivated by default in real products. |
Patrick Delaunay | 109d13f | 2019-07-05 17:20:17 +0200 | [diff] [blame] | 190 | |
Patrick Delaunay | fcb4991 | 2019-07-30 19:16:23 +0200 | [diff] [blame] | 191 | config PRE_CON_BUF_ADDR |
| 192 | default 0xC02FF000 |
| 193 | |
| 194 | config PRE_CON_BUF_SZ |
| 195 | default 4096 |
| 196 | |
Patrick Delaunay | f860020 | 2019-04-18 17:32:47 +0200 | [diff] [blame] | 197 | config BOOTSTAGE_STASH_ADDR |
| 198 | default 0xC3000000 |
| 199 | |
Patrick Delaunay | 951edb4 | 2021-12-07 10:05:59 +0100 | [diff] [blame] | 200 | if BOOTCOUNT_GENERIC |
Patrick Delaunay | 9c07f4a | 2019-04-18 17:32:45 +0200 | [diff] [blame] | 201 | config SYS_BOOTCOUNT_SINGLEWORD |
| 202 | default y |
| 203 | |
| 204 | # TAMP_BOOTCOUNT = TAMP_BACKUP_REGISTER(21) |
| 205 | config SYS_BOOTCOUNT_ADDR |
| 206 | default 0x5C00A154 |
| 207 | endif |
| 208 | |
Patrick Delaunay | 82168e8 | 2018-05-17 14:50:46 +0200 | [diff] [blame] | 209 | if DEBUG_UART |
| 210 | |
| 211 | config DEBUG_UART_BOARD_INIT |
| 212 | default y |
| 213 | |
| 214 | # debug on UART4 by default |
| 215 | config DEBUG_UART_BASE |
| 216 | default 0x40010000 |
| 217 | |
| 218 | # clock source is HSI on reset |
| 219 | config DEBUG_UART_CLOCK |
| 220 | default 64000000 |
| 221 | endif |
| 222 | |
Patrick Delaunay | 0440d86 | 2021-02-25 13:37:00 +0100 | [diff] [blame] | 223 | source "arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig" |
Marek Vasut | 5ff0529 | 2020-01-24 18:39:16 +0100 | [diff] [blame] | 224 | source "board/dhelectronics/dh_stm32mp1/Kconfig" |
Jagan Teki | c0f218b | 2021-03-16 21:52:03 +0530 | [diff] [blame] | 225 | source "board/engicam/stm32mp1/Kconfig" |
| 226 | source "board/st/stm32mp1/Kconfig" |
Patrick Delaunay | 6d3cbf3 | 2019-02-27 17:01:15 +0100 | [diff] [blame] | 227 | |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 228 | endif |