Masahiro Yamada | d3ae678 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 1 | menu "MIPS architecture" |
| 2 | depends on MIPS |
| 3 | |
| 4 | config SYS_ARCH |
Masahiro Yamada | d3ae678 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 5 | default "mips" |
| 6 | |
Daniel Schwierzeck | 99e7af2 | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 7 | config SYS_CPU |
Paul Burton | 3246437 | 2016-05-16 10:52:11 +0100 | [diff] [blame] | 8 | default "mips32" if CPU_MIPS32 |
| 9 | default "mips64" if CPU_MIPS64 |
Daniel Schwierzeck | 99e7af2 | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 10 | |
Masahiro Yamada | d3ae678 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 11 | choice |
| 12 | prompt "Target select" |
Joe Hershberger | f069960 | 2015-05-12 14:46:23 -0500 | [diff] [blame] | 13 | optional |
Masahiro Yamada | d3ae678 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 14 | |
| 15 | config TARGET_QEMU_MIPS |
| 16 | bool "Support qemu-mips" |
Michal Simek | 84f3dec | 2018-07-23 15:55:13 +0200 | [diff] [blame] | 17 | select ROM_EXCEPTION_VECTORS |
Daniel Schwierzeck | a4c242b | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 18 | select SUPPORTS_BIG_ENDIAN |
Daniel Schwierzeck | 256034d | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 19 | select SUPPORTS_CPU_MIPS32_R1 |
| 20 | select SUPPORTS_CPU_MIPS32_R2 |
Daniel Schwierzeck | 94384d1 | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 21 | select SUPPORTS_CPU_MIPS64_R1 |
| 22 | select SUPPORTS_CPU_MIPS64_R2 |
Michal Simek | 84f3dec | 2018-07-23 15:55:13 +0200 | [diff] [blame] | 23 | select SUPPORTS_LITTLE_ENDIAN |
Masahiro Yamada | d3ae678 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 24 | |
| 25 | config TARGET_MALTA |
| 26 | bool "Support malta" |
Paul Burton | a31a3df | 2016-05-17 07:43:28 +0100 | [diff] [blame] | 27 | select DM |
| 28 | select DM_SERIAL |
Paul Burton | 8d6600b | 2016-01-29 13:54:52 +0000 | [diff] [blame] | 29 | select DYNAMIC_IO_PORT_BASE |
Paul Burton | 59a4c8b | 2016-09-21 11:18:56 +0100 | [diff] [blame] | 30 | select MIPS_CM |
Daniel Schwierzeck | 2cc9a77 | 2018-09-07 19:18:44 +0200 | [diff] [blame] | 31 | select MIPS_INSERT_BOOT_CONFIG |
Michal Simek | 84f3dec | 2018-07-23 15:55:13 +0200 | [diff] [blame] | 32 | select MIPS_L1_CACHE_SHIFT_6 |
Paul Burton | 59a4c8b | 2016-09-21 11:18:56 +0100 | [diff] [blame] | 33 | select MIPS_L2_CACHE |
Paul Burton | a31a3df | 2016-05-17 07:43:28 +0100 | [diff] [blame] | 34 | select OF_CONTROL |
| 35 | select OF_ISA_BUS |
Michal Simek | 84f3dec | 2018-07-23 15:55:13 +0200 | [diff] [blame] | 36 | select ROM_EXCEPTION_VECTORS |
Daniel Schwierzeck | a4c242b | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 37 | select SUPPORTS_BIG_ENDIAN |
Daniel Schwierzeck | 256034d | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 38 | select SUPPORTS_CPU_MIPS32_R1 |
| 39 | select SUPPORTS_CPU_MIPS32_R2 |
Paul Burton | 1c10e0d | 2016-05-16 10:52:14 +0100 | [diff] [blame] | 40 | select SUPPORTS_CPU_MIPS32_R6 |
Paul Burton | 825cfbd | 2016-05-26 14:49:36 +0100 | [diff] [blame] | 41 | select SUPPORTS_CPU_MIPS64_R1 |
| 42 | select SUPPORTS_CPU_MIPS64_R2 |
| 43 | select SUPPORTS_CPU_MIPS64_R6 |
Michal Simek | 84f3dec | 2018-07-23 15:55:13 +0200 | [diff] [blame] | 44 | select SUPPORTS_LITTLE_ENDIAN |
Daniel Schwierzeck | 7dca686 | 2015-01-18 22:00:18 +0100 | [diff] [blame] | 45 | select SWAP_IO_SPACE |
Michal Simek | 2e7c819 | 2018-07-23 15:55:14 +0200 | [diff] [blame] | 46 | imply CMD_DM |
Masahiro Yamada | d3ae678 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 47 | |
| 48 | config TARGET_VCT |
| 49 | bool "Support vct" |
Michal Simek | 84f3dec | 2018-07-23 15:55:13 +0200 | [diff] [blame] | 50 | select ROM_EXCEPTION_VECTORS |
Daniel Schwierzeck | a4c242b | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 51 | select SUPPORTS_BIG_ENDIAN |
Daniel Schwierzeck | 256034d | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 52 | select SUPPORTS_CPU_MIPS32_R1 |
| 53 | select SUPPORTS_CPU_MIPS32_R2 |
Paul Burton | 6832bdc | 2015-01-29 01:28:02 +0000 | [diff] [blame] | 54 | select SYS_MIPS_CACHE_INIT_RAM_LOAD |
Masahiro Yamada | d3ae678 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 55 | |
Wills Wang | 833a1a8 | 2016-03-16 16:59:52 +0800 | [diff] [blame] | 56 | config ARCH_ATH79 |
| 57 | bool "Support QCA/Atheros ath79" |
Wills Wang | 833a1a8 | 2016-03-16 16:59:52 +0800 | [diff] [blame] | 58 | select DM |
Michal Simek | 84f3dec | 2018-07-23 15:55:13 +0200 | [diff] [blame] | 59 | select OF_CONTROL |
Michal Simek | 2e7c819 | 2018-07-23 15:55:14 +0200 | [diff] [blame] | 60 | imply CMD_DM |
Wills Wang | 833a1a8 | 2016-03-16 16:59:52 +0800 | [diff] [blame] | 61 | |
Álvaro Fernández Rojas | 98a97a8 | 2017-04-25 00:39:20 +0200 | [diff] [blame] | 62 | config ARCH_BMIPS |
| 63 | bool "Support BMIPS SoCs" |
Álvaro Fernández Rojas | 98a97a8 | 2017-04-25 00:39:20 +0200 | [diff] [blame] | 64 | select CLK |
| 65 | select CPU |
Michal Simek | 84f3dec | 2018-07-23 15:55:13 +0200 | [diff] [blame] | 66 | select DM |
| 67 | select OF_CONTROL |
Álvaro Fernández Rojas | 98a97a8 | 2017-04-25 00:39:20 +0200 | [diff] [blame] | 68 | select RAM |
| 69 | select SYSRESET |
Michal Simek | 2e7c819 | 2018-07-23 15:55:14 +0200 | [diff] [blame] | 70 | imply CMD_DM |
Álvaro Fernández Rojas | 98a97a8 | 2017-04-25 00:39:20 +0200 | [diff] [blame] | 71 | |
Stefan Roese | 65da15e | 2018-09-05 15:12:35 +0200 | [diff] [blame] | 72 | config ARCH_MT7620 |
| 73 | bool "Support MT7620/7688 SoCs" |
| 74 | imply CMD_DM |
| 75 | select DISPLAY_CPUINFO |
| 76 | select DM |
Stefan Roese | 8bbb6bf | 2018-10-09 08:59:09 +0200 | [diff] [blame] | 77 | imply DM_ETH |
| 78 | imply DM_GPIO |
Stefan Roese | 65da15e | 2018-09-05 15:12:35 +0200 | [diff] [blame] | 79 | select DM_SERIAL |
| 80 | imply DM_SPI |
| 81 | imply DM_SPI_FLASH |
Stefan Roese | 81382b7 | 2018-10-09 08:59:10 +0200 | [diff] [blame] | 82 | select ARCH_MISC_INIT if WATCHDOG |
Stefan Roese | 65da15e | 2018-09-05 15:12:35 +0200 | [diff] [blame] | 83 | select MIPS_TUNE_24KC |
| 84 | select OF_CONTROL |
| 85 | select ROM_EXCEPTION_VECTORS |
| 86 | select SUPPORTS_CPU_MIPS32_R1 |
| 87 | select SUPPORTS_CPU_MIPS32_R2 |
| 88 | select SUPPORTS_LITTLE_ENDIAN |
Stefan Roese | 845e0fd | 2018-08-16 15:27:32 +0200 | [diff] [blame] | 89 | select SYSRESET |
Stefan Roese | 65da15e | 2018-09-05 15:12:35 +0200 | [diff] [blame] | 90 | |
Purna Chandra Mandal | 825b321 | 2016-01-28 15:30:10 +0530 | [diff] [blame] | 91 | config MACH_PIC32 |
| 92 | bool "Support Microchip PIC32" |
Purna Chandra Mandal | 825b321 | 2016-01-28 15:30:10 +0530 | [diff] [blame] | 93 | select DM |
Michal Simek | 84f3dec | 2018-07-23 15:55:13 +0200 | [diff] [blame] | 94 | select OF_CONTROL |
Michal Simek | 2e7c819 | 2018-07-23 15:55:14 +0200 | [diff] [blame] | 95 | imply CMD_DM |
Purna Chandra Mandal | 825b321 | 2016-01-28 15:30:10 +0530 | [diff] [blame] | 96 | |
Paul Burton | f5de32a | 2016-09-08 07:47:39 +0100 | [diff] [blame] | 97 | config TARGET_BOSTON |
| 98 | bool "Support Boston" |
| 99 | select DM |
| 100 | select DM_SERIAL |
Paul Burton | f5de32a | 2016-09-08 07:47:39 +0100 | [diff] [blame] | 101 | select MIPS_CM |
| 102 | select MIPS_L1_CACHE_SHIFT_6 |
| 103 | select MIPS_L2_CACHE |
Paul Burton | a315bcd | 2017-04-30 21:22:42 +0200 | [diff] [blame] | 104 | select OF_BOARD_SETUP |
Michal Simek | 84f3dec | 2018-07-23 15:55:13 +0200 | [diff] [blame] | 105 | select OF_CONTROL |
| 106 | select ROM_EXCEPTION_VECTORS |
Paul Burton | f5de32a | 2016-09-08 07:47:39 +0100 | [diff] [blame] | 107 | select SUPPORTS_BIG_ENDIAN |
Paul Burton | f5de32a | 2016-09-08 07:47:39 +0100 | [diff] [blame] | 108 | select SUPPORTS_CPU_MIPS32_R1 |
| 109 | select SUPPORTS_CPU_MIPS32_R2 |
| 110 | select SUPPORTS_CPU_MIPS32_R6 |
| 111 | select SUPPORTS_CPU_MIPS64_R1 |
| 112 | select SUPPORTS_CPU_MIPS64_R2 |
| 113 | select SUPPORTS_CPU_MIPS64_R6 |
Michal Simek | 84f3dec | 2018-07-23 15:55:13 +0200 | [diff] [blame] | 114 | select SUPPORTS_LITTLE_ENDIAN |
Michal Simek | 2e7c819 | 2018-07-23 15:55:14 +0200 | [diff] [blame] | 115 | imply CMD_DM |
Paul Burton | f5de32a | 2016-09-08 07:47:39 +0100 | [diff] [blame] | 116 | |
Zubair Lutfullah Kakakhel | 1d153b3 | 2016-07-29 15:11:20 +0100 | [diff] [blame] | 117 | config TARGET_XILFPGA |
| 118 | bool "Support Imagination Xilfpga" |
Zubair Lutfullah Kakakhel | 1d153b3 | 2016-07-29 15:11:20 +0100 | [diff] [blame] | 119 | select DM |
Zubair Lutfullah Kakakhel | 1d153b3 | 2016-07-29 15:11:20 +0100 | [diff] [blame] | 120 | select DM_ETH |
Michal Simek | 84f3dec | 2018-07-23 15:55:13 +0200 | [diff] [blame] | 121 | select DM_GPIO |
| 122 | select DM_SERIAL |
Zubair Lutfullah Kakakhel | 1d153b3 | 2016-07-29 15:11:20 +0100 | [diff] [blame] | 123 | select MIPS_L1_CACHE_SHIFT_4 |
Michal Simek | 84f3dec | 2018-07-23 15:55:13 +0200 | [diff] [blame] | 124 | select OF_CONTROL |
Daniel Schwierzeck | 754cd05 | 2016-02-14 18:52:57 +0100 | [diff] [blame] | 125 | select ROM_EXCEPTION_VECTORS |
Michal Simek | 84f3dec | 2018-07-23 15:55:13 +0200 | [diff] [blame] | 126 | select SUPPORTS_CPU_MIPS32_R1 |
| 127 | select SUPPORTS_CPU_MIPS32_R2 |
| 128 | select SUPPORTS_LITTLE_ENDIAN |
Michal Simek | 2e7c819 | 2018-07-23 15:55:14 +0200 | [diff] [blame] | 129 | imply CMD_DM |
Zubair Lutfullah Kakakhel | 1d153b3 | 2016-07-29 15:11:20 +0100 | [diff] [blame] | 130 | help |
| 131 | This supports IMGTEC MIPSfpga platform |
| 132 | |
Masahiro Yamada | d3ae678 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 133 | endchoice |
| 134 | |
Paul Burton | f5de32a | 2016-09-08 07:47:39 +0100 | [diff] [blame] | 135 | source "board/imgtec/boston/Kconfig" |
Masahiro Yamada | d3ae678 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 136 | source "board/imgtec/malta/Kconfig" |
Zubair Lutfullah Kakakhel | 1d153b3 | 2016-07-29 15:11:20 +0100 | [diff] [blame] | 137 | source "board/imgtec/xilfpga/Kconfig" |
Masahiro Yamada | d3ae678 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 138 | source "board/micronas/vct/Kconfig" |
Masahiro Yamada | d3ae678 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 139 | source "board/qemu-mips/Kconfig" |
Wills Wang | 833a1a8 | 2016-03-16 16:59:52 +0800 | [diff] [blame] | 140 | source "arch/mips/mach-ath79/Kconfig" |
Álvaro Fernández Rojas | 98a97a8 | 2017-04-25 00:39:20 +0200 | [diff] [blame] | 141 | source "arch/mips/mach-bmips/Kconfig" |
Purna Chandra Mandal | 825b321 | 2016-01-28 15:30:10 +0530 | [diff] [blame] | 142 | source "arch/mips/mach-pic32/Kconfig" |
Stefan Roese | 65da15e | 2018-09-05 15:12:35 +0200 | [diff] [blame] | 143 | source "arch/mips/mach-mt7620/Kconfig" |
Masahiro Yamada | d3ae678 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 144 | |
Daniel Schwierzeck | a4c242b | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 145 | if MIPS |
| 146 | |
| 147 | choice |
| 148 | prompt "Endianness selection" |
| 149 | help |
| 150 | Some MIPS boards can be configured for either little or big endian |
| 151 | byte order. These modes require different U-Boot images. In general there |
| 152 | is one preferred byteorder for a particular system but some systems are |
| 153 | just as commonly used in the one or the other endianness. |
| 154 | |
| 155 | config SYS_BIG_ENDIAN |
| 156 | bool "Big endian" |
| 157 | depends on SUPPORTS_BIG_ENDIAN |
| 158 | |
| 159 | config SYS_LITTLE_ENDIAN |
| 160 | bool "Little endian" |
| 161 | depends on SUPPORTS_LITTLE_ENDIAN |
| 162 | |
| 163 | endchoice |
| 164 | |
Daniel Schwierzeck | 256034d | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 165 | choice |
| 166 | prompt "CPU selection" |
| 167 | default CPU_MIPS32_R2 |
| 168 | |
| 169 | config CPU_MIPS32_R1 |
| 170 | bool "MIPS32 Release 1" |
| 171 | depends on SUPPORTS_CPU_MIPS32_R1 |
| 172 | select 32BIT |
| 173 | help |
Paul Burton | 55e29dd | 2016-05-16 10:52:12 +0100 | [diff] [blame] | 174 | Choose this option to build an U-Boot for release 1 through 5 of the |
Daniel Schwierzeck | 256034d | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 175 | MIPS32 architecture. |
| 176 | |
| 177 | config CPU_MIPS32_R2 |
| 178 | bool "MIPS32 Release 2" |
| 179 | depends on SUPPORTS_CPU_MIPS32_R2 |
| 180 | select 32BIT |
| 181 | help |
Paul Burton | 55e29dd | 2016-05-16 10:52:12 +0100 | [diff] [blame] | 182 | Choose this option to build an U-Boot for release 2 through 5 of the |
Daniel Schwierzeck | 256034d | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 183 | MIPS32 architecture. |
| 184 | |
Paul Burton | 55e29dd | 2016-05-16 10:52:12 +0100 | [diff] [blame] | 185 | config CPU_MIPS32_R6 |
| 186 | bool "MIPS32 Release 6" |
| 187 | depends on SUPPORTS_CPU_MIPS32_R6 |
| 188 | select 32BIT |
| 189 | help |
| 190 | Choose this option to build an U-Boot for release 6 or later of the |
| 191 | MIPS32 architecture. |
| 192 | |
Daniel Schwierzeck | 256034d | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 193 | config CPU_MIPS64_R1 |
| 194 | bool "MIPS64 Release 1" |
| 195 | depends on SUPPORTS_CPU_MIPS64_R1 |
| 196 | select 64BIT |
| 197 | help |
Paul Burton | 55e29dd | 2016-05-16 10:52:12 +0100 | [diff] [blame] | 198 | Choose this option to build a kernel for release 1 through 5 of the |
Daniel Schwierzeck | 256034d | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 199 | MIPS64 architecture. |
| 200 | |
| 201 | config CPU_MIPS64_R2 |
| 202 | bool "MIPS64 Release 2" |
| 203 | depends on SUPPORTS_CPU_MIPS64_R2 |
| 204 | select 64BIT |
| 205 | help |
Paul Burton | 55e29dd | 2016-05-16 10:52:12 +0100 | [diff] [blame] | 206 | Choose this option to build a kernel for release 2 through 5 of the |
| 207 | MIPS64 architecture. |
| 208 | |
| 209 | config CPU_MIPS64_R6 |
| 210 | bool "MIPS64 Release 6" |
| 211 | depends on SUPPORTS_CPU_MIPS64_R6 |
| 212 | select 64BIT |
| 213 | help |
| 214 | Choose this option to build a kernel for release 6 or later of the |
Daniel Schwierzeck | 256034d | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 215 | MIPS64 architecture. |
| 216 | |
| 217 | endchoice |
| 218 | |
Daniel Schwierzeck | 754cd05 | 2016-02-14 18:52:57 +0100 | [diff] [blame] | 219 | menu "General setup" |
| 220 | |
| 221 | config ROM_EXCEPTION_VECTORS |
| 222 | bool "Build U-Boot image with exception vectors" |
| 223 | help |
| 224 | Enable this to include exception vectors in the U-Boot image. This is |
| 225 | required if the U-Boot entry point is equal to the address of the |
| 226 | CPU reset exception vector (e.g. U-Boot as ROM loader in Qemu, |
| 227 | U-Boot booted from parallel NOR flash). |
| 228 | Disable this, if the U-Boot image is booted from DRAM (e.g. by SPL). |
| 229 | In that case the image size will be reduced by 0x500 bytes. |
| 230 | |
Paul Burton | 3d6864a | 2017-05-12 13:26:11 +0200 | [diff] [blame] | 231 | config MIPS_CM_BASE |
| 232 | hex "MIPS CM GCR Base Address" |
| 233 | depends on MIPS_CM |
Paul Burton | a6ac965 | 2017-04-30 21:22:41 +0200 | [diff] [blame] | 234 | default 0x16100000 if TARGET_BOSTON |
Paul Burton | 3d6864a | 2017-05-12 13:26:11 +0200 | [diff] [blame] | 235 | default 0x1fbf8000 |
| 236 | help |
| 237 | The physical base address at which to map the MIPS Coherence Manager |
| 238 | Global Configuration Registers (GCRs). This should be set such that |
| 239 | the GCRs occupy a region of the physical address space which is |
| 240 | otherwise unused, or at minimum that software doesn't need to access. |
| 241 | |
Daniel Schwierzeck | e3b432d | 2018-09-07 19:02:05 +0200 | [diff] [blame] | 242 | config MIPS_CACHE_INDEX_BASE |
| 243 | hex "Index base address for cache initialisation" |
| 244 | default 0x80000000 if CPU_MIPS32 |
| 245 | default 0xffffffff80000000 if CPU_MIPS64 |
| 246 | help |
| 247 | This is the base address for a memory block, which is used for |
| 248 | initialising the cache lines. This is also the base address of a memory |
| 249 | block which is used for loading and filling cache lines when |
| 250 | SYS_MIPS_CACHE_INIT_RAM_LOAD is selected. |
| 251 | Normally this is CKSEG0. If the MIPS system needs to move this block |
| 252 | to some SRAM or ScratchPad RAM, adapt this option accordingly. |
| 253 | |
Daniel Schwierzeck | 8013286 | 2018-11-01 02:02:21 +0100 | [diff] [blame] | 254 | config MIPS_RELOCATION_TABLE_SIZE |
| 255 | hex "Relocation table size" |
| 256 | range 0x100 0x10000 |
| 257 | default "0x8000" |
| 258 | ---help--- |
| 259 | A table of relocation data will be appended to the U-Boot binary |
| 260 | and parsed in relocate_code() to fix up all offsets in the relocated |
| 261 | U-Boot. |
| 262 | |
| 263 | This option allows the amount of space reserved for the table to be |
| 264 | adjusted in a range from 256 up to 64k. The default is 32k and should |
| 265 | be ok in most cases. Reduce this value to shrink the size of U-Boot |
| 266 | binary. |
| 267 | |
| 268 | The build will fail and a valid size suggested if this is too small. |
| 269 | |
| 270 | If unsure, leave at the default value. |
| 271 | |
Daniel Schwierzeck | 754cd05 | 2016-02-14 18:52:57 +0100 | [diff] [blame] | 272 | endmenu |
| 273 | |
Daniel Schwierzeck | f9749fa | 2015-01-14 21:44:13 +0100 | [diff] [blame] | 274 | menu "OS boot interface" |
| 275 | |
| 276 | config MIPS_BOOT_CMDLINE_LEGACY |
| 277 | bool "Hand over legacy command line to Linux kernel" |
| 278 | default y |
| 279 | help |
| 280 | Enable this option if you want U-Boot to hand over the Yamon-style |
| 281 | command line to the kernel. All bootargs will be prepared as argc/argv |
| 282 | compatible list. The argument count (argc) is stored in register $a0. |
| 283 | The address of the argument list (argv) is stored in register $a1. |
| 284 | |
Daniel Schwierzeck | c07dc60 | 2015-01-14 21:44:13 +0100 | [diff] [blame] | 285 | config MIPS_BOOT_ENV_LEGACY |
| 286 | bool "Hand over legacy environment to Linux kernel" |
| 287 | default y |
| 288 | help |
| 289 | Enable this option if you want U-Boot to hand over the Yamon-style |
| 290 | environment to the kernel. Information like memory size, initrd |
| 291 | address and size will be prepared as zero-terminated key/value list. |
Robert P. J. Day | 8c60f92 | 2016-05-04 04:47:31 -0400 | [diff] [blame] | 292 | The address of the environment is stored in register $a2. |
Daniel Schwierzeck | c07dc60 | 2015-01-14 21:44:13 +0100 | [diff] [blame] | 293 | |
Daniel Schwierzeck | 8d7ff4d | 2015-01-14 21:44:13 +0100 | [diff] [blame] | 294 | config MIPS_BOOT_FDT |
Daniel Schwierzeck | d1b29d2 | 2015-02-22 16:58:30 +0100 | [diff] [blame] | 295 | bool "Hand over a flattened device tree to Linux kernel" |
Daniel Schwierzeck | 8d7ff4d | 2015-01-14 21:44:13 +0100 | [diff] [blame] | 296 | default n |
| 297 | help |
| 298 | Enable this option if you want U-Boot to hand over a flattened |
Daniel Schwierzeck | d1b29d2 | 2015-02-22 16:58:30 +0100 | [diff] [blame] | 299 | device tree to the kernel. According to UHI register $a0 will be set |
| 300 | to -2 and the FDT address is stored in $a1. |
Daniel Schwierzeck | 8d7ff4d | 2015-01-14 21:44:13 +0100 | [diff] [blame] | 301 | |
Daniel Schwierzeck | f9749fa | 2015-01-14 21:44:13 +0100 | [diff] [blame] | 302 | endmenu |
| 303 | |
Daniel Schwierzeck | a4c242b | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 304 | config SUPPORTS_BIG_ENDIAN |
| 305 | bool |
| 306 | |
| 307 | config SUPPORTS_LITTLE_ENDIAN |
| 308 | bool |
| 309 | |
Daniel Schwierzeck | 256034d | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 310 | config SUPPORTS_CPU_MIPS32_R1 |
| 311 | bool |
| 312 | |
| 313 | config SUPPORTS_CPU_MIPS32_R2 |
| 314 | bool |
| 315 | |
Paul Burton | 55e29dd | 2016-05-16 10:52:12 +0100 | [diff] [blame] | 316 | config SUPPORTS_CPU_MIPS32_R6 |
| 317 | bool |
| 318 | |
Daniel Schwierzeck | 256034d | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 319 | config SUPPORTS_CPU_MIPS64_R1 |
| 320 | bool |
| 321 | |
| 322 | config SUPPORTS_CPU_MIPS64_R2 |
| 323 | bool |
| 324 | |
Paul Burton | 55e29dd | 2016-05-16 10:52:12 +0100 | [diff] [blame] | 325 | config SUPPORTS_CPU_MIPS64_R6 |
| 326 | bool |
| 327 | |
Daniel Schwierzeck | dfbad0f | 2015-01-18 21:59:35 +0100 | [diff] [blame] | 328 | config CPU_MIPS32 |
| 329 | bool |
Paul Burton | 55e29dd | 2016-05-16 10:52:12 +0100 | [diff] [blame] | 330 | default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6 |
Daniel Schwierzeck | dfbad0f | 2015-01-18 21:59:35 +0100 | [diff] [blame] | 331 | |
| 332 | config CPU_MIPS64 |
| 333 | bool |
Paul Burton | 55e29dd | 2016-05-16 10:52:12 +0100 | [diff] [blame] | 334 | default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6 |
Daniel Schwierzeck | dfbad0f | 2015-01-18 21:59:35 +0100 | [diff] [blame] | 335 | |
Daniel Schwierzeck | aadd332 | 2015-12-26 19:55:37 +0100 | [diff] [blame] | 336 | config MIPS_TUNE_4KC |
| 337 | bool |
| 338 | |
| 339 | config MIPS_TUNE_14KC |
| 340 | bool |
| 341 | |
| 342 | config MIPS_TUNE_24KC |
| 343 | bool |
| 344 | |
Daniel Schwierzeck | c7661d5 | 2016-05-27 15:39:39 +0200 | [diff] [blame] | 345 | config MIPS_TUNE_34KC |
| 346 | bool |
| 347 | |
Marek Vasut | a9c6e8b | 2016-05-06 20:10:33 +0200 | [diff] [blame] | 348 | config MIPS_TUNE_74KC |
| 349 | bool |
| 350 | |
Daniel Schwierzeck | 256034d | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 351 | config 32BIT |
| 352 | bool |
| 353 | |
| 354 | config 64BIT |
| 355 | bool |
| 356 | |
Daniel Schwierzeck | 7dca686 | 2015-01-18 22:00:18 +0100 | [diff] [blame] | 357 | config SWAP_IO_SPACE |
| 358 | bool |
| 359 | |
Paul Burton | 6832bdc | 2015-01-29 01:28:02 +0000 | [diff] [blame] | 360 | config SYS_MIPS_CACHE_INIT_RAM_LOAD |
| 361 | bool |
| 362 | |
Daniel Schwierzeck | 41dc35e | 2016-06-04 16:13:21 +0200 | [diff] [blame] | 363 | config MIPS_INIT_STACK_IN_SRAM |
| 364 | bool |
| 365 | default n |
| 366 | help |
| 367 | Select this if the initial stack frame could be setup in SRAM. |
| 368 | Normally the initial stack frame is set up in DRAM which is often |
| 369 | only available after lowlevel_init. With this option the initial |
| 370 | stack frame and the early C environment is set up before |
| 371 | lowlevel_init. Thus lowlevel_init does not need to be implemented |
| 372 | in assembler. |
| 373 | |
Paul Burton | 5e51142 | 2016-05-27 14:28:04 +0100 | [diff] [blame] | 374 | config SYS_DCACHE_SIZE |
| 375 | int |
| 376 | default 0 |
| 377 | help |
| 378 | The total size of the L1 Dcache, if known at compile time. |
| 379 | |
Paul Burton | 62f1352 | 2016-05-27 14:28:05 +0100 | [diff] [blame] | 380 | config SYS_DCACHE_LINE_SIZE |
Paul Burton | 79e49fd | 2016-06-09 13:09:52 +0100 | [diff] [blame] | 381 | int |
Paul Burton | 62f1352 | 2016-05-27 14:28:05 +0100 | [diff] [blame] | 382 | default 0 |
| 383 | help |
| 384 | The size of L1 Dcache lines, if known at compile time. |
| 385 | |
Paul Burton | 5e51142 | 2016-05-27 14:28:04 +0100 | [diff] [blame] | 386 | config SYS_ICACHE_SIZE |
| 387 | int |
| 388 | default 0 |
| 389 | help |
| 390 | The total size of the L1 ICache, if known at compile time. |
| 391 | |
Paul Burton | 62f1352 | 2016-05-27 14:28:05 +0100 | [diff] [blame] | 392 | config SYS_ICACHE_LINE_SIZE |
Paul Burton | 5e51142 | 2016-05-27 14:28:04 +0100 | [diff] [blame] | 393 | int |
| 394 | default 0 |
| 395 | help |
Paul Burton | 62f1352 | 2016-05-27 14:28:05 +0100 | [diff] [blame] | 396 | The size of L1 Icache lines, if known at compile time. |
Paul Burton | 5e51142 | 2016-05-27 14:28:04 +0100 | [diff] [blame] | 397 | |
| 398 | config SYS_CACHE_SIZE_AUTO |
| 399 | def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \ |
Paul Burton | 62f1352 | 2016-05-27 14:28:05 +0100 | [diff] [blame] | 400 | SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0 |
Paul Burton | 5e51142 | 2016-05-27 14:28:04 +0100 | [diff] [blame] | 401 | help |
| 402 | Select this (or let it be auto-selected by not defining any cache |
| 403 | sizes) in order to allow U-Boot to automatically detect the sizes |
| 404 | of caches at runtime. This has a small cost in code size & runtime |
| 405 | so if you know the cache configuration for your system at compile |
| 406 | time it would be beneficial to configure it. |
| 407 | |
Daniel Schwierzeck | 02ca55e | 2016-01-09 17:32:50 +0100 | [diff] [blame] | 408 | config MIPS_L1_CACHE_SHIFT_4 |
| 409 | bool |
| 410 | |
| 411 | config MIPS_L1_CACHE_SHIFT_5 |
| 412 | bool |
| 413 | |
| 414 | config MIPS_L1_CACHE_SHIFT_6 |
| 415 | bool |
| 416 | |
| 417 | config MIPS_L1_CACHE_SHIFT_7 |
| 418 | bool |
| 419 | |
| 420 | config MIPS_L1_CACHE_SHIFT |
| 421 | int |
| 422 | default "7" if MIPS_L1_CACHE_SHIFT_7 |
| 423 | default "6" if MIPS_L1_CACHE_SHIFT_6 |
| 424 | default "5" if MIPS_L1_CACHE_SHIFT_5 |
| 425 | default "4" if MIPS_L1_CACHE_SHIFT_4 |
| 426 | default "5" |
| 427 | |
Paul Burton | 8156078 | 2016-09-21 11:18:54 +0100 | [diff] [blame] | 428 | config MIPS_L2_CACHE |
| 429 | bool |
| 430 | help |
| 431 | Select this if your system includes an L2 cache and you want U-Boot |
| 432 | to initialise & maintain it. |
| 433 | |
Paul Burton | 8d6600b | 2016-01-29 13:54:52 +0000 | [diff] [blame] | 434 | config DYNAMIC_IO_PORT_BASE |
| 435 | bool |
| 436 | |
Paul Burton | 79ac174 | 2016-09-21 11:18:53 +0100 | [diff] [blame] | 437 | config MIPS_CM |
| 438 | bool |
| 439 | help |
| 440 | Select this if your system contains a MIPS Coherence Manager and you |
| 441 | wish U-Boot to configure it or make use of it to retrieve system |
| 442 | information such as cache configuration. |
| 443 | |
Daniel Schwierzeck | 2cc9a77 | 2018-09-07 19:18:44 +0200 | [diff] [blame] | 444 | config MIPS_INSERT_BOOT_CONFIG |
| 445 | bool |
| 446 | default n |
| 447 | help |
| 448 | Enable this to insert some board-specific boot configuration in |
| 449 | the U-Boot binary at offset 0x10. |
| 450 | |
| 451 | config MIPS_BOOT_CONFIG_WORD0 |
| 452 | hex |
| 453 | depends on MIPS_INSERT_BOOT_CONFIG |
| 454 | default 0x420 if TARGET_MALTA |
| 455 | default 0x0 |
| 456 | help |
| 457 | Value which is inserted as boot config word 0. |
| 458 | |
| 459 | config MIPS_BOOT_CONFIG_WORD1 |
| 460 | hex |
| 461 | depends on MIPS_INSERT_BOOT_CONFIG |
| 462 | default 0x0 |
| 463 | help |
| 464 | Value which is inserted as boot config word 1. |
| 465 | |
Daniel Schwierzeck | a4c242b | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 466 | endif |
| 467 | |
Masahiro Yamada | d3ae678 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 468 | endmenu |