Masahiro Yamada | cc85b7b | 2015-07-26 02:46:26 +0900 | [diff] [blame] | 1 | # |
| 2 | # I2C subsystem configuration |
| 3 | # |
| 4 | |
Simon Glass | 8e85e3c | 2021-07-10 21:14:35 -0600 | [diff] [blame] | 5 | menuconfig I2C |
| 6 | bool "I2C support" |
| 7 | default y |
| 8 | help |
| 9 | Note: |
| 10 | This is a stand-in for an option to enable I2C support. In fact this |
| 11 | simply enables building of the I2C directory for U-Boot. The actual |
| 12 | I2C feature is enabled by DM_I2C (for driver model) and |
| 13 | the #define CONFIG_SYS_I2C_LEGACY (for the legacy I2C stack). |
| 14 | |
| 15 | So at present there is no need to ever disable this option. |
| 16 | |
| 17 | Eventually it will: |
| 18 | |
| 19 | Enable support for the I2C (Inter-Integrated Circuit) bus in U-Boot. |
| 20 | I2C works with a clock and data line which can be driven by a |
| 21 | one or more masters or slaves. It is a fairly complex bus but is |
| 22 | widely used as it only needs two lines for communication. Speeds of |
| 23 | 400kbps are typical but up to 3.4Mbps is supported by some |
| 24 | hardware. Enable this option to build the drivers in drivers/i2c as |
| 25 | part of a U-Boot build. |
| 26 | |
| 27 | if I2C |
Masahiro Yamada | cc85b7b | 2015-07-26 02:46:26 +0900 | [diff] [blame] | 28 | |
Masahiro Yamada | cd5cf8e | 2015-01-13 12:44:35 +0900 | [diff] [blame] | 29 | config DM_I2C |
| 30 | bool "Enable Driver Model for I2C drivers" |
| 31 | depends on DM |
| 32 | help |
Przemyslaw Marczak | e5fa121 | 2015-03-31 18:57:17 +0200 | [diff] [blame] | 33 | Enable driver model for I2C. The I2C uclass interface: probe, read, |
| 34 | write and speed, is implemented with the bus drivers operations, |
| 35 | which provide methods for bus setting and data transfer. Each chip |
Simon Glass | 71fa5b4 | 2020-12-03 16:55:18 -0700 | [diff] [blame] | 36 | device (bus child) info is kept as parent plat. The interface |
Bartosz Golaszewski | 1e4450c | 2019-07-29 08:58:00 +0200 | [diff] [blame] | 37 | is defined in include/i2c.h. |
Simon Glass | e200ee2 | 2015-02-13 12:20:48 -0700 | [diff] [blame] | 38 | |
Igor Opaniuk | 964f232 | 2021-02-09 13:52:43 +0200 | [diff] [blame] | 39 | config SPL_DM_I2C |
| 40 | bool "Enable Driver Model for I2C drivers in SPL" |
| 41 | depends on SPL_DM && DM_I2C |
| 42 | default y |
| 43 | help |
| 44 | Enable driver model for I2C. The I2C uclass interface: probe, read, |
| 45 | write and speed, is implemented with the bus drivers operations, |
| 46 | which provide methods for bus setting and data transfer. Each chip |
| 47 | device (bus child) info is kept as parent platdata. The interface |
| 48 | is defined in include/i2c.h. |
| 49 | |
Simon Glass | e7ca7da | 2022-04-30 00:56:53 -0600 | [diff] [blame] | 50 | config VPL_DM_I2C |
| 51 | bool "Enable Driver Model for I2C drivers in VPL" |
| 52 | depends on VPL_DM && DM_I2C |
| 53 | default y |
| 54 | help |
| 55 | Enable driver model for I2C. The I2C uclass interface: probe, read, |
| 56 | write and speed, is implemented with the bus drivers operations, |
| 57 | which provide methods for bus setting and data transfer. Each chip |
| 58 | device (bus child) info is kept as parent platdata. The interface |
| 59 | is defined in include/i2c.h. |
| 60 | |
Tom Rini | 52b2e26 | 2021-08-18 23:12:24 -0400 | [diff] [blame] | 61 | config SYS_I2C_LEGACY |
| 62 | bool "Enable legacy I2C subsystem and drivers" |
| 63 | depends on !DM_I2C |
| 64 | help |
| 65 | Enable the legacy I2C subsystem and drivers. While this is |
| 66 | deprecated in U-Boot itself, this can be useful in some situations |
| 67 | in SPL or TPL. |
| 68 | |
| 69 | config SPL_SYS_I2C_LEGACY |
| 70 | bool "Enable legacy I2C subsystem and drivers in SPL" |
| 71 | depends on SUPPORT_SPL && !SPL_DM_I2C |
| 72 | help |
| 73 | Enable the legacy I2C subsystem and drivers in SPL. This is useful |
| 74 | in some size constrained situations. |
| 75 | |
| 76 | config TPL_SYS_I2C_LEGACY |
| 77 | bool "Enable legacy I2C subsystem and drivers in TPL" |
| 78 | depends on SUPPORT_TPL && !SPL_DM_I2C |
| 79 | help |
| 80 | Enable the legacy I2C subsystem and drivers in TPL. This is useful |
| 81 | in some size constrained situations. |
| 82 | |
Tom Rini | 714482a | 2021-08-18 23:12:25 -0400 | [diff] [blame] | 83 | config SYS_I2C_EARLY_INIT |
| 84 | bool "Enable legacy I2C subsystem early in boot" |
| 85 | depends on BOARD_EARLY_INIT_F && SPL_SYS_I2C_LEGACY && SYS_I2C_MXC |
| 86 | help |
| 87 | Add the function prototype for i2c_early_init_f which is called in |
| 88 | board_early_init_f. |
| 89 | |
Simon Glass | 9ad07af | 2015-08-03 08:19:23 -0600 | [diff] [blame] | 90 | config I2C_CROS_EC_TUNNEL |
| 91 | tristate "Chrome OS EC tunnel I2C bus" |
| 92 | depends on CROS_EC |
| 93 | help |
| 94 | This provides an I2C bus that will tunnel i2c commands through to |
| 95 | the other side of the Chrome OS EC to the I2C bus connected there. |
| 96 | This will work whatever the interface used to talk to the EC (SPI, |
| 97 | I2C or LPC). Some Chromebooks use this when the hardware design |
| 98 | does not allow direct access to the main PMIC from the AP. |
| 99 | |
Simon Glass | eb2cc51 | 2015-08-03 08:19:24 -0600 | [diff] [blame] | 100 | config I2C_CROS_EC_LDO |
| 101 | bool "Provide access to LDOs on the Chrome OS EC" |
| 102 | depends on CROS_EC |
| 103 | ---help--- |
| 104 | On many Chromebooks the main PMIC is inaccessible to the AP. This is |
| 105 | often dealt with by using an I2C pass-through interface provided by |
| 106 | the EC. On some unfortunate models (e.g. Spring) the pass-through |
| 107 | is not available, and an LDO message is available instead. This |
| 108 | option enables a driver which provides very basic access to those |
| 109 | regulators, via the EC. We implement this as an I2C bus which |
| 110 | emulates just the TPS65090 messages we know about. This is done to |
| 111 | avoid duplicating the logic in the TPS65090 regulator driver for |
| 112 | enabling/disabling an LDO. |
Simon Glass | 9ad07af | 2015-08-03 08:19:23 -0600 | [diff] [blame] | 113 | |
Lukasz Majewski | 0a55627 | 2017-03-21 12:08:25 +0100 | [diff] [blame] | 114 | config I2C_SET_DEFAULT_BUS_NUM |
| 115 | bool "Set default I2C bus number" |
| 116 | depends on DM_I2C |
| 117 | help |
| 118 | Set default number of I2C bus to be accessed. This option provides |
| 119 | behaviour similar to old (i.e. pre DM) I2C bus driver. |
| 120 | |
| 121 | config I2C_DEFAULT_BUS_NUMBER |
| 122 | hex "I2C default bus number" |
| 123 | depends on I2C_SET_DEFAULT_BUS_NUM |
| 124 | default 0x0 |
| 125 | help |
| 126 | Number of default I2C bus to use |
| 127 | |
Przemyslaw Marczak | d3aa7e1 | 2015-03-31 18:57:18 +0200 | [diff] [blame] | 128 | config DM_I2C_GPIO |
| 129 | bool "Enable Driver Model for software emulated I2C bus driver" |
| 130 | depends on DM_I2C && DM_GPIO |
| 131 | help |
| 132 | Enable the i2c bus driver emulation by using the GPIOs. The bus GPIO |
| 133 | configuration is given by the device tree. Kernel-style device tree |
| 134 | bindings are supported. |
| 135 | Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt |
| 136 | |
Igor Opaniuk | 964f232 | 2021-02-09 13:52:43 +0200 | [diff] [blame] | 137 | config SPL_DM_I2C_GPIO |
| 138 | bool "Enable Driver Model for software emulated I2C bus driver in SPL" |
Simon Glass | 035939e | 2021-07-10 21:14:30 -0600 | [diff] [blame] | 139 | depends on SPL_DM && DM_I2C_GPIO && SPL_DM_GPIO && SPL_GPIO |
Igor Opaniuk | 964f232 | 2021-02-09 13:52:43 +0200 | [diff] [blame] | 140 | default y |
| 141 | help |
| 142 | Enable the i2c bus driver emulation by using the GPIOs. The bus GPIO |
| 143 | configuration is given by the device tree. Kernel-style device tree |
| 144 | bindings are supported. |
| 145 | Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt |
| 146 | |
Songjun Wu | 26d8828 | 2016-06-20 13:22:38 +0800 | [diff] [blame] | 147 | config SYS_I2C_AT91 |
| 148 | bool "Atmel I2C driver" |
| 149 | depends on DM_I2C && ARCH_AT91 |
| 150 | help |
| 151 | Add support for the Atmel I2C driver. A serious problem is that there |
| 152 | is no documented way to issue repeated START conditions for more than |
| 153 | two messages, as needed to support combined I2C messages. Use the |
| 154 | i2c-gpio driver unless your system can cope with this limitation. |
| 155 | Binding info: doc/device-tree-bindings/i2c/i2c-at91.txt |
| 156 | |
Rayagonda Kokatanur | d5dc36f | 2020-04-08 11:12:27 +0530 | [diff] [blame] | 157 | config SYS_I2C_IPROC |
| 158 | bool "Broadcom I2C driver" |
| 159 | depends on DM_I2C |
| 160 | help |
| 161 | Broadcom I2C driver. |
| 162 | Add support for Broadcom I2C driver. |
| 163 | Say yes here to to enable the Broadco I2C driver. |
| 164 | |
mario.six@gdsys.cc | 349686c | 2016-04-25 08:31:09 +0200 | [diff] [blame] | 165 | config SYS_I2C_FSL |
| 166 | bool "Freescale I2C bus driver" |
mario.six@gdsys.cc | 349686c | 2016-04-25 08:31:09 +0200 | [diff] [blame] | 167 | help |
| 168 | Add support for Freescale I2C busses as used on MPC8240, MPC8245, and |
| 169 | MPC85xx processors. |
| 170 | |
Tom Rini | be94c76 | 2021-08-18 23:12:35 -0400 | [diff] [blame] | 171 | if SYS_I2C_FSL && (SYS_I2C_LEGACY || SPL_SYS_I2C_LEGACY) |
| 172 | config SYS_FSL_I2C_OFFSET |
| 173 | hex "Offset from the IMMR of the address of the first I2C controller" |
| 174 | |
| 175 | config SYS_FSL_HAS_I2C2_OFFSET |
| 176 | bool "Support a second I2C controller" |
| 177 | |
| 178 | config SYS_FSL_I2C2_OFFSET |
| 179 | hex "Offset from the IMMR of the address of the second I2C controller" |
| 180 | depends on SYS_FSL_HAS_I2C2_OFFSET |
| 181 | |
| 182 | config SYS_FSL_HAS_I2C3_OFFSET |
| 183 | bool "Support a third I2C controller" |
| 184 | |
| 185 | config SYS_FSL_I2C3_OFFSET |
| 186 | hex "Offset from the IMMR of the address of the third I2C controller" |
| 187 | depends on SYS_FSL_HAS_I2C3_OFFSET |
| 188 | |
| 189 | config SYS_FSL_HAS_I2C4_OFFSET |
| 190 | bool "Support a fourth I2C controller" |
| 191 | |
| 192 | config SYS_FSL_I2C4_OFFSET |
| 193 | hex "Offset from the IMMR of the address of the fourth I2C controller" |
| 194 | depends on SYS_FSL_HAS_I2C4_OFFSET |
| 195 | endif |
| 196 | |
Moritz Fischer | 0075dac | 2015-12-28 09:47:11 -0800 | [diff] [blame] | 197 | config SYS_I2C_CADENCE |
| 198 | tristate "Cadence I2C Controller" |
Michal Simek | c28665d | 2020-08-06 15:18:36 +0200 | [diff] [blame] | 199 | depends on DM_I2C |
Moritz Fischer | 0075dac | 2015-12-28 09:47:11 -0800 | [diff] [blame] | 200 | help |
| 201 | Say yes here to select Cadence I2C Host Controller. This controller is |
| 202 | e.g. used by Xilinx Zynq. |
| 203 | |
Arthur Li | fe661ba | 2020-06-01 12:56:31 -0700 | [diff] [blame] | 204 | config SYS_I2C_CA |
| 205 | tristate "Cortina-Access I2C Controller" |
| 206 | depends on DM_I2C && CORTINA_PLATFORM |
Arthur Li | fe661ba | 2020-06-01 12:56:31 -0700 | [diff] [blame] | 207 | help |
| 208 | Add support for the Cortina Access I2C host controller. |
| 209 | Say yes here to select Cortina-Access I2C Host Controller. |
| 210 | |
Adam Ford | decc895 | 2018-08-10 05:05:22 -0500 | [diff] [blame] | 211 | config SYS_I2C_DAVINCI |
| 212 | bool "Davinci I2C Controller" |
| 213 | depends on (ARCH_KEYSTONE || ARCH_DAVINCI) |
| 214 | help |
| 215 | Say yes here to add support for Davinci and Keystone I2C controller |
| 216 | |
Stefan Roese | b71955f | 2016-04-28 09:47:17 +0200 | [diff] [blame] | 217 | config SYS_I2C_DW |
| 218 | bool "Designware I2C Controller" |
Stefan Roese | b71955f | 2016-04-28 09:47:17 +0200 | [diff] [blame] | 219 | help |
| 220 | Say yes here to select the Designware I2C Host Controller. This |
| 221 | controller is used in various SoCs, e.g. the ST SPEAr, Altera |
| 222 | SoCFPGA, Synopsys ARC700 and some Intel x86 SoCs. |
| 223 | |
maxims@google.com | 7f61331 | 2017-04-17 12:00:30 -0700 | [diff] [blame] | 224 | config SYS_I2C_ASPEED |
| 225 | bool "Aspeed I2C Controller" |
| 226 | depends on DM_I2C && ARCH_ASPEED |
| 227 | help |
| 228 | Say yes here to select Aspeed I2C Host Controller. The driver |
| 229 | supports AST2500 and AST2400 controllers, but is very limited. |
| 230 | Only single master mode is supported and only byte-by-byte |
| 231 | synchronous reads and writes are supported, no Pool Buffers or DMA. |
| 232 | |
Simon Glass | 5e66fdc | 2016-01-17 16:11:44 -0700 | [diff] [blame] | 233 | config SYS_I2C_INTEL |
| 234 | bool "Intel I2C/SMBUS driver" |
| 235 | depends on DM_I2C |
| 236 | help |
| 237 | Add support for the Intel SMBUS driver. So far this driver is just |
| 238 | a stub which perhaps some basic init. There is no implementation of |
| 239 | the I2C API meaning that any I2C operations will immediately fail |
| 240 | for now. |
| 241 | |
Peng Fan | d684adb | 2017-02-24 09:54:18 +0800 | [diff] [blame] | 242 | config SYS_I2C_IMX_LPI2C |
| 243 | bool "NXP i.MX LPI2C driver" |
Peng Fan | d684adb | 2017-02-24 09:54:18 +0800 | [diff] [blame] | 244 | help |
| 245 | Add support for the NXP i.MX LPI2C driver. |
| 246 | |
Trevor Woerner | 5f37e50 | 2021-06-10 22:37:08 -0400 | [diff] [blame] | 247 | config SYS_I2C_LPC32XX |
| 248 | bool "LPC32XX I2C driver" |
| 249 | depends on ARCH_LPC32XX |
| 250 | help |
| 251 | Enable support for the LPC32xx I2C driver. |
| 252 | |
Beniamino Galvani | d5b199c | 2017-10-29 10:09:00 +0100 | [diff] [blame] | 253 | config SYS_I2C_MESON |
| 254 | bool "Amlogic Meson I2C driver" |
| 255 | depends on DM_I2C && ARCH_MESON |
| 256 | help |
Beniamino Galvani | 83b153d | 2017-11-26 17:40:54 +0100 | [diff] [blame] | 257 | Add support for the I2C controller available in Amlogic Meson |
| 258 | SoCs. The controller supports programmable bus speed including |
| 259 | standard (100kbits/s) and fast (400kbit/s) speed and allows the |
| 260 | software to define a flexible format of the bit streams. It has an |
| 261 | internal buffer holding up to 8 bytes for transfers and supports |
| 262 | both 7-bit and 10-bit addresses. |
Beniamino Galvani | d5b199c | 2017-10-29 10:09:00 +0100 | [diff] [blame] | 263 | |
developer | 301212f | 2022-09-09 19:59:48 +0800 | [diff] [blame] | 264 | config SYS_I2C_MTK |
| 265 | bool "MediaTek I2C driver" |
| 266 | help |
| 267 | This selects the MediaTek Integrated Inter Circuit bus driver. |
| 268 | The I2C bus adapter is the base for some other I2C client, |
| 269 | eg: touch, sensors. |
| 270 | If you want to use MediaTek I2C interface, say Y here. |
| 271 | If unsure, say N. |
| 272 | |
Padmarao Begari | 7ddb4ec | 2021-11-17 18:21:16 +0530 | [diff] [blame] | 273 | config SYS_I2C_MICROCHIP |
| 274 | bool "Microchip I2C driver" |
| 275 | help |
| 276 | Add support for the Microchip I2C driver. This is operating on |
| 277 | standard mode up to 100 kbits/s and fast mode up to 400 kbits/s. |
| 278 | |
Jagan Teki | 0aedd7f | 2016-12-06 00:00:57 +0100 | [diff] [blame] | 279 | config SYS_I2C_MXC |
Sriram Dash | 7122a0c | 2018-02-06 11:26:30 +0530 | [diff] [blame] | 280 | bool "NXP MXC I2C driver" |
Jagan Teki | 0aedd7f | 2016-12-06 00:00:57 +0100 | [diff] [blame] | 281 | help |
Chris Packham | 94d0d3d | 2019-01-13 22:13:25 +1300 | [diff] [blame] | 282 | Add support for the NXP I2C driver. This supports up to four bus |
| 283 | channels and operating on standard mode up to 100 kbits/s and fast |
| 284 | mode up to 400 kbits/s. |
Jagan Teki | 0aedd7f | 2016-12-06 00:00:57 +0100 | [diff] [blame] | 285 | |
Tom Rini | 1a19588 | 2021-08-18 23:12:33 -0400 | [diff] [blame] | 286 | if SYS_I2C_MXC && (SYS_I2C_LEGACY || SPL_SYS_I2C_LEGACY) |
Sriram Dash | 7122a0c | 2018-02-06 11:26:30 +0530 | [diff] [blame] | 287 | config SYS_I2C_MXC_I2C1 |
| 288 | bool "NXP MXC I2C1" |
| 289 | help |
| 290 | Add support for NXP MXC I2C Controller 1. |
| 291 | Required for SoCs which have I2C MXC controller 1 eg LS1088A, LS2080A |
| 292 | |
| 293 | config SYS_I2C_MXC_I2C2 |
| 294 | bool "NXP MXC I2C2" |
| 295 | help |
| 296 | Add support for NXP MXC I2C Controller 2. |
| 297 | Required for SoCs which have I2C MXC controller 2 eg LS1088A, LS2080A |
| 298 | |
| 299 | config SYS_I2C_MXC_I2C3 |
| 300 | bool "NXP MXC I2C3" |
| 301 | help |
| 302 | Add support for NXP MXC I2C Controller 3. |
| 303 | Required for SoCs which have I2C MXC controller 3 eg LS1088A, LS2080A |
| 304 | |
| 305 | config SYS_I2C_MXC_I2C4 |
| 306 | bool "NXP MXC I2C4" |
| 307 | help |
| 308 | Add support for NXP MXC I2C Controller 4. |
| 309 | Required for SoCs which have I2C MXC controller 4 eg LS1088A, LS2080A |
Sriram Dash | a64aa19 | 2018-02-06 11:26:31 +0530 | [diff] [blame] | 310 | |
| 311 | config SYS_I2C_MXC_I2C5 |
| 312 | bool "NXP MXC I2C5" |
| 313 | help |
| 314 | Add support for NXP MXC I2C Controller 5. |
| 315 | Required for SoCs which have I2C MXC controller 5 eg LX2160A |
| 316 | |
| 317 | config SYS_I2C_MXC_I2C6 |
| 318 | bool "NXP MXC I2C6" |
| 319 | help |
| 320 | Add support for NXP MXC I2C Controller 6. |
| 321 | Required for SoCs which have I2C MXC controller 6 eg LX2160A |
| 322 | |
| 323 | config SYS_I2C_MXC_I2C7 |
| 324 | bool "NXP MXC I2C7" |
| 325 | help |
| 326 | Add support for NXP MXC I2C Controller 7. |
| 327 | Required for SoCs which have I2C MXC controller 7 eg LX2160A |
| 328 | |
| 329 | config SYS_I2C_MXC_I2C8 |
| 330 | bool "NXP MXC I2C8" |
| 331 | help |
| 332 | Add support for NXP MXC I2C Controller 8. |
| 333 | Required for SoCs which have I2C MXC controller 8 eg LX2160A |
Sriram Dash | 7122a0c | 2018-02-06 11:26:30 +0530 | [diff] [blame] | 334 | endif |
| 335 | |
| 336 | if SYS_I2C_MXC_I2C1 |
| 337 | config SYS_MXC_I2C1_SPEED |
| 338 | int "I2C Channel 1 speed" |
Tom Rini | 48425b1 | 2021-02-09 08:03:10 -0500 | [diff] [blame] | 339 | default 40000000 if TARGET_LS2080A_EMU |
Sriram Dash | 7122a0c | 2018-02-06 11:26:30 +0530 | [diff] [blame] | 340 | default 100000 |
| 341 | help |
| 342 | MXC I2C Channel 1 speed |
| 343 | |
| 344 | config SYS_MXC_I2C1_SLAVE |
Tom Rini | 1a19588 | 2021-08-18 23:12:33 -0400 | [diff] [blame] | 345 | hex "I2C1 Slave" |
Sriram Dash | 7122a0c | 2018-02-06 11:26:30 +0530 | [diff] [blame] | 346 | default 0 |
| 347 | help |
| 348 | MXC I2C1 Slave |
| 349 | endif |
| 350 | |
| 351 | if SYS_I2C_MXC_I2C2 |
| 352 | config SYS_MXC_I2C2_SPEED |
| 353 | int "I2C Channel 2 speed" |
Tom Rini | 48425b1 | 2021-02-09 08:03:10 -0500 | [diff] [blame] | 354 | default 40000000 if TARGET_LS2080A_EMU |
Sriram Dash | 7122a0c | 2018-02-06 11:26:30 +0530 | [diff] [blame] | 355 | default 100000 |
| 356 | help |
| 357 | MXC I2C Channel 2 speed |
| 358 | |
| 359 | config SYS_MXC_I2C2_SLAVE |
Tom Rini | 1a19588 | 2021-08-18 23:12:33 -0400 | [diff] [blame] | 360 | hex "I2C2 Slave" |
Sriram Dash | 7122a0c | 2018-02-06 11:26:30 +0530 | [diff] [blame] | 361 | default 0 |
| 362 | help |
| 363 | MXC I2C2 Slave |
| 364 | endif |
| 365 | |
| 366 | if SYS_I2C_MXC_I2C3 |
| 367 | config SYS_MXC_I2C3_SPEED |
| 368 | int "I2C Channel 3 speed" |
| 369 | default 100000 |
| 370 | help |
| 371 | MXC I2C Channel 3 speed |
| 372 | |
| 373 | config SYS_MXC_I2C3_SLAVE |
Tom Rini | 1a19588 | 2021-08-18 23:12:33 -0400 | [diff] [blame] | 374 | hex "I2C3 Slave" |
Sriram Dash | 7122a0c | 2018-02-06 11:26:30 +0530 | [diff] [blame] | 375 | default 0 |
| 376 | help |
| 377 | MXC I2C3 Slave |
| 378 | endif |
| 379 | |
| 380 | if SYS_I2C_MXC_I2C4 |
| 381 | config SYS_MXC_I2C4_SPEED |
| 382 | int "I2C Channel 4 speed" |
| 383 | default 100000 |
| 384 | help |
| 385 | MXC I2C Channel 4 speed |
| 386 | |
| 387 | config SYS_MXC_I2C4_SLAVE |
Tom Rini | 1a19588 | 2021-08-18 23:12:33 -0400 | [diff] [blame] | 388 | hex "I2C4 Slave" |
Sriram Dash | 7122a0c | 2018-02-06 11:26:30 +0530 | [diff] [blame] | 389 | default 0 |
| 390 | help |
| 391 | MXC I2C4 Slave |
| 392 | endif |
| 393 | |
Sriram Dash | a64aa19 | 2018-02-06 11:26:31 +0530 | [diff] [blame] | 394 | if SYS_I2C_MXC_I2C5 |
| 395 | config SYS_MXC_I2C5_SPEED |
| 396 | int "I2C Channel 5 speed" |
| 397 | default 100000 |
| 398 | help |
| 399 | MXC I2C Channel 5 speed |
| 400 | |
| 401 | config SYS_MXC_I2C5_SLAVE |
Tom Rini | 1a19588 | 2021-08-18 23:12:33 -0400 | [diff] [blame] | 402 | hex "I2C5 Slave" |
Sriram Dash | a64aa19 | 2018-02-06 11:26:31 +0530 | [diff] [blame] | 403 | default 0 |
| 404 | help |
| 405 | MXC I2C5 Slave |
| 406 | endif |
| 407 | |
| 408 | if SYS_I2C_MXC_I2C6 |
| 409 | config SYS_MXC_I2C6_SPEED |
| 410 | int "I2C Channel 6 speed" |
| 411 | default 100000 |
| 412 | help |
| 413 | MXC I2C Channel 6 speed |
| 414 | |
| 415 | config SYS_MXC_I2C6_SLAVE |
Tom Rini | 1a19588 | 2021-08-18 23:12:33 -0400 | [diff] [blame] | 416 | hex "I2C6 Slave" |
Sriram Dash | a64aa19 | 2018-02-06 11:26:31 +0530 | [diff] [blame] | 417 | default 0 |
| 418 | help |
| 419 | MXC I2C6 Slave |
| 420 | endif |
| 421 | |
| 422 | if SYS_I2C_MXC_I2C7 |
| 423 | config SYS_MXC_I2C7_SPEED |
| 424 | int "I2C Channel 7 speed" |
| 425 | default 100000 |
| 426 | help |
| 427 | MXC I2C Channel 7 speed |
| 428 | |
| 429 | config SYS_MXC_I2C7_SLAVE |
Tom Rini | 1a19588 | 2021-08-18 23:12:33 -0400 | [diff] [blame] | 430 | hex "I2C7 Slave" |
Sriram Dash | a64aa19 | 2018-02-06 11:26:31 +0530 | [diff] [blame] | 431 | default 0 |
| 432 | help |
| 433 | MXC I2C7 Slave |
| 434 | endif |
| 435 | |
| 436 | if SYS_I2C_MXC_I2C8 |
| 437 | config SYS_MXC_I2C8_SPEED |
| 438 | int "I2C Channel 8 speed" |
| 439 | default 100000 |
| 440 | help |
| 441 | MXC I2C Channel 8 speed |
| 442 | |
| 443 | config SYS_MXC_I2C8_SLAVE |
Tom Rini | 1a19588 | 2021-08-18 23:12:33 -0400 | [diff] [blame] | 444 | hex "I2C8 Slave" |
Sriram Dash | a64aa19 | 2018-02-06 11:26:31 +0530 | [diff] [blame] | 445 | default 0 |
| 446 | help |
| 447 | MXC I2C8 Slave |
| 448 | endif |
| 449 | |
Stefan Bosch | 9d85dfb | 2020-07-10 19:07:28 +0200 | [diff] [blame] | 450 | config SYS_I2C_NEXELL |
| 451 | bool "Nexell I2C driver" |
| 452 | depends on DM_I2C |
| 453 | help |
| 454 | Add support for the Nexell I2C driver. This is used with various |
| 455 | Nexell parts such as S5Pxx18 series SoCs. All chips |
| 456 | have several I2C ports and all are provided, controlled by the |
| 457 | device tree. |
| 458 | |
Jim Liu | b84426c | 2022-06-23 13:31:42 +0800 | [diff] [blame] | 459 | config SYS_I2C_NPCM |
| 460 | bool "Nuvoton NPCM I2C driver" |
| 461 | help |
| 462 | Support for Nuvoton I2C controller driver. |
| 463 | |
Pragnesh Patel | 1cfbd7a | 2020-11-14 14:42:34 +0530 | [diff] [blame] | 464 | config SYS_I2C_OCORES |
| 465 | bool "ocores I2C driver" |
| 466 | depends on DM_I2C |
| 467 | help |
| 468 | Add support for ocores I2C controller. For details see |
| 469 | https://opencores.org/projects/i2c |
| 470 | |
Adam Ford | 8590116 | 2017-08-07 13:11:34 -0500 | [diff] [blame] | 471 | config SYS_I2C_OMAP24XX |
| 472 | bool "TI OMAP2+ I2C driver" |
Vignesh R | 64d4f55 | 2019-06-04 18:08:11 -0500 | [diff] [blame] | 473 | depends on ARCH_OMAP2PLUS || ARCH_K3 |
Adam Ford | 8590116 | 2017-08-07 13:11:34 -0500 | [diff] [blame] | 474 | help |
| 475 | Add support for the OMAP2+ I2C driver. |
| 476 | |
Marek Vasut | 2716596 | 2018-04-21 18:57:28 +0200 | [diff] [blame] | 477 | config SYS_I2C_RCAR_I2C |
| 478 | bool "Renesas RCar I2C driver" |
| 479 | depends on (RCAR_GEN3 || RCAR_GEN2) && DM_I2C |
| 480 | help |
| 481 | Support for Renesas RCar I2C controller. |
| 482 | |
Marek Vasut | 125d8df | 2017-11-28 08:02:27 +0100 | [diff] [blame] | 483 | config SYS_I2C_RCAR_IIC |
| 484 | bool "Renesas RCar Gen3 IIC driver" |
Marek Vasut | 4bc57a3 | 2018-02-17 02:17:40 +0100 | [diff] [blame] | 485 | depends on (RCAR_GEN3 || RCAR_GEN2) && DM_I2C |
Marek Vasut | 125d8df | 2017-11-28 08:02:27 +0100 | [diff] [blame] | 486 | help |
| 487 | Support for Renesas RCar Gen3 IIC controller. |
| 488 | |
Simon Glass | 3595f95 | 2015-08-30 16:55:39 -0600 | [diff] [blame] | 489 | config SYS_I2C_ROCKCHIP |
| 490 | bool "Rockchip I2C driver" |
| 491 | depends on DM_I2C |
| 492 | help |
| 493 | Add support for the Rockchip I2C driver. This is used with various |
| 494 | Rockchip parts such as RK3126, RK3128, RK3036 and RK3288. All chips |
Chris Packham | 94d0d3d | 2019-01-13 22:13:25 +1300 | [diff] [blame] | 495 | have several I2C ports and all are provided, controlled by the |
Simon Glass | 3595f95 | 2015-08-30 16:55:39 -0600 | [diff] [blame] | 496 | device tree. |
| 497 | |
Simon Glass | 39bc3be | 2015-03-06 13:19:04 -0700 | [diff] [blame] | 498 | config SYS_I2C_SANDBOX |
| 499 | bool "Sandbox I2C driver" |
| 500 | depends on SANDBOX && DM_I2C |
| 501 | help |
| 502 | Enable I2C support for sandbox. This is an emulation of a real I2C |
| 503 | bus. Devices can be attached to the bus using the device tree |
Masahiro Yamada | 8d8371d | 2017-02-11 12:39:55 +0900 | [diff] [blame] | 504 | which specifies the driver to use. See sandbox.dts as an example. |
Simon Glass | 39bc3be | 2015-03-06 13:19:04 -0700 | [diff] [blame] | 505 | |
Tom Rini | b9a254d | 2021-08-18 23:12:34 -0400 | [diff] [blame] | 506 | config SYS_I2C_SH |
| 507 | bool "Legacy SuperH I2C interface" |
| 508 | depends on ARCH_RMOBILE && SYS_I2C_LEGACY |
| 509 | help |
| 510 | Enable the legacy SuperH I2C interface. |
| 511 | |
| 512 | if SYS_I2C_SH |
| 513 | config SYS_I2C_SH_NUM_CONTROLLERS |
| 514 | int |
| 515 | default 5 |
| 516 | |
| 517 | config SYS_I2C_SH_BASE0 |
| 518 | hex |
| 519 | default 0xE6820000 |
| 520 | |
| 521 | config SYS_I2C_SH_BASE1 |
| 522 | hex |
| 523 | default 0xE6822000 |
| 524 | |
| 525 | config SYS_I2C_SH_BASE2 |
| 526 | hex |
| 527 | default 0xE6824000 |
| 528 | |
| 529 | config SYS_I2C_SH_BASE3 |
| 530 | hex |
| 531 | default 0xE6826000 |
| 532 | |
| 533 | config SYS_I2C_SH_BASE4 |
| 534 | hex |
| 535 | default 0xE6828000 |
| 536 | |
| 537 | config SH_I2C_8BIT |
| 538 | bool |
| 539 | default y |
| 540 | |
| 541 | config SH_I2C_DATA_HIGH |
| 542 | int |
| 543 | default 4 |
| 544 | |
| 545 | config SH_I2C_DATA_LOW |
| 546 | int |
| 547 | default 5 |
| 548 | |
| 549 | config SH_I2C_CLOCK |
| 550 | int |
| 551 | default 104000000 |
| 552 | endif |
| 553 | |
Tom Rini | 5817ff0 | 2021-08-17 17:59:46 -0400 | [diff] [blame] | 554 | config SYS_I2C_SOFT |
| 555 | bool "Legacy software I2C interface" |
| 556 | help |
| 557 | Enable the legacy software defined I2C interface |
| 558 | |
| 559 | config SYS_I2C_SOFT_SPEED |
| 560 | int "Software I2C bus speed" |
| 561 | depends on SYS_I2C_SOFT |
| 562 | default 100000 |
| 563 | help |
| 564 | Speed of the software I2C bus |
| 565 | |
| 566 | config SYS_I2C_SOFT_SLAVE |
| 567 | hex "Software I2C slave address" |
| 568 | depends on SYS_I2C_SOFT |
| 569 | default 0xfe |
| 570 | help |
| 571 | Slave address of the software I2C bus |
| 572 | |
Suneel Garapati | c6baea2 | 2020-05-26 14:13:07 +0200 | [diff] [blame] | 573 | config SYS_I2C_OCTEON |
| 574 | bool "Octeon II/III/TX/TX2 I2C driver" |
| 575 | depends on (ARCH_OCTEON || ARCH_OCTEONTX || ARCH_OCTEONTX2) && DM_I2C |
| 576 | default y |
| 577 | help |
| 578 | Add support for the Marvell Octeon I2C driver. This is used with |
| 579 | various Octeon parts such as Octeon II/III and OcteonTX/TX2. All |
| 580 | chips have several I2C ports and all are provided, controlled by |
| 581 | the device tree. |
| 582 | |
Sumit Garg | 77e4c4e | 2023-02-01 19:29:00 +0530 | [diff] [blame] | 583 | config SYS_I2C_QUP |
| 584 | bool "Qualcomm QUP I2C controller" |
| 585 | depends on ARCH_SNAPDRAGON |
| 586 | help |
| 587 | Support for Qualcomm QUP I2C controller based on Qualcomm Universal |
| 588 | Peripherals (QUP) engine. The QUP engine is an advanced high |
| 589 | performance slave port that provides a common data path (an output |
| 590 | FIFO and an input FIFO) for I2C and SPI interfaces. The I2C/SPI QUP |
| 591 | controller is publicly documented in the Snapdragon 410E (APQ8016E) |
| 592 | Technical Reference Manual, chapter "6.1 Qualcomm Universal |
| 593 | Peripherals Engine (QUP)". |
| 594 | |
Jaehoon Chung | f7e6a03 | 2017-01-09 14:47:52 +0900 | [diff] [blame] | 595 | config SYS_I2C_S3C24X0 |
| 596 | bool "Samsung I2C driver" |
Tom Rini | fc917de | 2021-08-17 17:59:42 -0400 | [diff] [blame] | 597 | depends on (ARCH_EXYNOS4 || ARCH_EXYNOS5) && DM_I2C |
Jaehoon Chung | f7e6a03 | 2017-01-09 14:47:52 +0900 | [diff] [blame] | 598 | help |
| 599 | Support for Samsung I2C controller as Samsung SoCs. |
Simon Glass | 39bc3be | 2015-03-06 13:19:04 -0700 | [diff] [blame] | 600 | |
Patrice Chotard | ebf442d | 2017-08-09 14:45:27 +0200 | [diff] [blame] | 601 | config SYS_I2C_STM32F7 |
| 602 | bool "STMicroelectronics STM32F7 I2C support" |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 603 | depends on (STM32F7 || STM32H7 || ARCH_STM32MP) && DM_I2C |
Patrice Chotard | ebf442d | 2017-08-09 14:45:27 +0200 | [diff] [blame] | 604 | help |
| 605 | Enable this option to add support for STM32 I2C controller |
| 606 | introduced with STM32F7/H7 SoCs. This I2C controller supports : |
| 607 | _ Slave and master modes |
| 608 | _ Multimaster capability |
| 609 | _ Standard-mode (up to 100 kHz) |
| 610 | _ Fast-mode (up to 400 kHz) |
| 611 | _ Fast-mode Plus (up to 1 MHz) |
| 612 | _ 7-bit and 10-bit addressing mode |
| 613 | _ Multiple 7-bit slave addresses (2 addresses, 1 with configurable mask) |
| 614 | _ All 7-bit addresses acknowledge mode |
| 615 | _ General call |
| 616 | _ Programmable setup and hold times |
| 617 | _ Easy to use event management |
| 618 | _ Optional clock stretching |
| 619 | _ Software reset |
| 620 | |
Samuel Holland | 60d4928 | 2021-10-08 00:17:20 -0500 | [diff] [blame] | 621 | config SYS_I2C_SUN6I_P2WI |
| 622 | bool "Allwinner sun6i P2WI controller" |
| 623 | depends on ARCH_SUNXI |
| 624 | help |
| 625 | Support for the P2WI (Push/Pull 2 Wire Interface) controller embedded |
| 626 | in the Allwinner A31 and A31s SOCs. This interface is used to connect |
| 627 | to specific devices like the X-Powers AXP221 PMIC. |
| 628 | |
Samuel Holland | b348efb | 2021-10-08 00:17:21 -0500 | [diff] [blame] | 629 | config SYS_I2C_SUN8I_RSB |
| 630 | bool "Allwinner sun8i Reduced Serial Bus controller" |
| 631 | depends on ARCH_SUNXI |
| 632 | help |
| 633 | Support for Allwinner's Reduced Serial Bus (RSB) controller. This |
| 634 | controller is responsible for communicating with various RSB based |
| 635 | devices, such as X-Powers AXPxxx PMICs and AC100/AC200 CODEC ICs. |
| 636 | |
Jassi Brar | 23325cf | 2021-06-04 18:44:48 +0900 | [diff] [blame] | 637 | config SYS_I2C_SYNQUACER |
| 638 | bool "Socionext SynQuacer I2C controller" |
| 639 | depends on ARCH_SYNQUACER && DM_I2C |
| 640 | help |
| 641 | Support for Socionext Synquacer I2C controller. This I2C controller |
| 642 | will be used for RTC and LS-connector on DeveloperBox. |
| 643 | |
Peter Robinson | 12d37d8 | 2019-02-20 12:17:26 +0000 | [diff] [blame] | 644 | config SYS_I2C_TEGRA |
| 645 | bool "NVIDIA Tegra internal I2C controller" |
Trevor Woerner | 513f640 | 2020-05-06 08:02:41 -0400 | [diff] [blame] | 646 | depends on ARCH_TEGRA |
Peter Robinson | 12d37d8 | 2019-02-20 12:17:26 +0000 | [diff] [blame] | 647 | help |
| 648 | Support for NVIDIA I2C controller available in Tegra SoCs. |
| 649 | |
Masahiro Yamada | 96a42ed | 2015-01-13 12:44:36 +0900 | [diff] [blame] | 650 | config SYS_I2C_UNIPHIER |
| 651 | bool "UniPhier I2C driver" |
| 652 | depends on ARCH_UNIPHIER && DM_I2C |
| 653 | default y |
| 654 | help |
Masahiro Yamada | 563ee4c | 2015-05-29 17:30:01 +0900 | [diff] [blame] | 655 | Support for UniPhier I2C controller driver. This I2C controller |
| 656 | is used on PH1-LD4, PH1-sLD8 or older UniPhier SoCs. |
Masahiro Yamada | 4e82e5e | 2015-01-13 12:44:37 +0900 | [diff] [blame] | 657 | |
| 658 | config SYS_I2C_UNIPHIER_F |
| 659 | bool "UniPhier FIFO-builtin I2C driver" |
| 660 | depends on ARCH_UNIPHIER && DM_I2C |
| 661 | default y |
| 662 | help |
Masahiro Yamada | 563ee4c | 2015-05-29 17:30:01 +0900 | [diff] [blame] | 663 | Support for UniPhier FIFO-builtin I2C controller driver. |
Masahiro Yamada | 4e82e5e | 2015-01-13 12:44:37 +0900 | [diff] [blame] | 664 | This I2C controller is used on PH1-Pro4 or newer UniPhier SoCs. |
Simon Glass | 2a80c40 | 2015-08-03 08:19:21 -0600 | [diff] [blame] | 665 | |
Heiko Schocher | a37c196 | 2018-10-11 07:26:33 +0200 | [diff] [blame] | 666 | config SYS_I2C_VERSATILE |
| 667 | bool "Arm Ltd Versatile I2C bus driver" |
Tom Rini | 5af921e | 2021-02-20 20:05:47 -0500 | [diff] [blame] | 668 | depends on DM_I2C && TARGET_VEXPRESS64_JUNO |
Heiko Schocher | a37c196 | 2018-10-11 07:26:33 +0200 | [diff] [blame] | 669 | help |
| 670 | Add support for the Arm Ltd Versatile Express I2C driver. The I2C host |
| 671 | controller is present in the development boards manufactured by Arm Ltd. |
| 672 | |
Marek BehĂșn | 53929db | 2021-10-09 19:33:37 +0200 | [diff] [blame] | 673 | config SYS_I2C_MV |
| 674 | bool "Marvell PXA (Armada 3720) I2C driver" |
| 675 | help |
| 676 | Support for PXA based I2C controller used on Armada 3720 SoC. |
| 677 | In Linux, this driver is called i2c-pxa. |
| 678 | |
mario.six@gdsys.cc | 355a127 | 2016-07-21 11:57:10 +0200 | [diff] [blame] | 679 | config SYS_I2C_MVTWSI |
| 680 | bool "Marvell I2C driver" |
mario.six@gdsys.cc | 355a127 | 2016-07-21 11:57:10 +0200 | [diff] [blame] | 681 | help |
| 682 | Support for Marvell I2C controllers as used on the orion5x and |
| 683 | kirkwood SoC families. |
| 684 | |
Stephen Warren | 67a8348 | 2016-08-08 11:28:27 -0600 | [diff] [blame] | 685 | config TEGRA186_BPMP_I2C |
| 686 | bool "Enable Tegra186 BPMP-based I2C driver" |
| 687 | depends on TEGRA186_BPMP |
| 688 | help |
| 689 | Support for Tegra I2C controllers managed by the BPMP (Boot and |
| 690 | Power Management Processor). On Tegra186, some I2C controllers are |
| 691 | directly controlled by the main CPU, whereas others are controlled |
| 692 | by the BPMP, and can only be accessed by the main CPU via IPC |
| 693 | requests to the BPMP. This driver covers the latter case. |
| 694 | |
Tom Rini | a6e2923 | 2021-08-18 23:12:32 -0400 | [diff] [blame] | 695 | config SYS_I2C_SLAVE |
| 696 | hex "I2C Slave address channel (all buses)" |
| 697 | depends on SYS_I2C_LEGACY || SPL_SYS_I2C_LEGACY || TPL_SYS_I2C_LEGACY |
| 698 | default 0xfe |
| 699 | help |
| 700 | I2C Slave address channel 0 for all buses in the legacy drivers. |
| 701 | Many boards/controllers/drivers don't support an I2C slave |
| 702 | interface so provide a default slave address for them for use in |
| 703 | common code. A real value for CONFIG_SYS_I2C_SLAVE should be |
| 704 | defined for any board which does support a slave interface and |
| 705 | this default used otherwise. |
| 706 | |
| 707 | config SYS_I2C_SPEED |
| 708 | int "I2C Slave channel 0 speed (all buses)" |
| 709 | depends on SYS_I2C_LEGACY || SPL_SYS_I2C_LEGACY || TPL_SYS_I2C_LEGACY |
| 710 | default 100000 |
| 711 | help |
| 712 | I2C Slave speed channel 0 for all buses in the legacy drivers. |
| 713 | |
Adam Ford | fa1dd3d | 2017-08-11 06:39:34 -0500 | [diff] [blame] | 714 | config SYS_I2C_BUS_MAX |
| 715 | int "Max I2C busses" |
Tom Rini | a2359f5 | 2022-06-27 13:35:50 -0400 | [diff] [blame] | 716 | depends on ARCH_OMAP2PLUS || ARCH_SOCFPGA |
Adam Ford | fa1dd3d | 2017-08-11 06:39:34 -0500 | [diff] [blame] | 717 | default 2 if TI816X |
Tom Rini | a2359f5 | 2022-06-27 13:35:50 -0400 | [diff] [blame] | 718 | default 3 if OMAP34XX || AM33XX || AM43XX |
Tom Rini | 428deb3 | 2022-12-02 16:42:41 -0500 | [diff] [blame] | 719 | default 4 if ARCH_SOCFPGA || OMAP44XX |
Adam Ford | fa1dd3d | 2017-08-11 06:39:34 -0500 | [diff] [blame] | 720 | default 5 if OMAP54XX |
| 721 | help |
| 722 | Define the maximum number of available I2C buses. |
| 723 | |
Marek Vasut | 9de0e2a | 2018-12-19 12:26:27 +0100 | [diff] [blame] | 724 | config SYS_I2C_XILINX_XIIC |
| 725 | bool "Xilinx AXI I2C driver" |
| 726 | depends on DM_I2C |
| 727 | help |
| 728 | Support for Xilinx AXI I2C controller. |
| 729 | |
Mario Six | 3bb409c | 2018-01-15 11:08:11 +0100 | [diff] [blame] | 730 | config SYS_I2C_IHS |
| 731 | bool "gdsys IHS I2C driver" |
| 732 | depends on DM_I2C |
| 733 | help |
| 734 | Support for gdsys IHS I2C driver on FPGA bus. |
| 735 | |
Simon Glass | 2a80c40 | 2015-08-03 08:19:21 -0600 | [diff] [blame] | 736 | source "drivers/i2c/muxes/Kconfig" |
Masahiro Yamada | cc85b7b | 2015-07-26 02:46:26 +0900 | [diff] [blame] | 737 | |
Simon Glass | 8e85e3c | 2021-07-10 21:14:35 -0600 | [diff] [blame] | 738 | endif |