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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Pavel Machek5e2d70a2014-09-08 14:08:45 +02002/*
3 * Copyright (C) 2012 Altera Corporation <www.altera.com>
Pavel Machek5e2d70a2014-09-08 14:08:45 +02004 */
Dinh Nguyenf593acd2015-12-03 16:05:59 -06005#ifndef __CONFIG_SOCFPGA_COMMON_H__
6#define __CONFIG_SOCFPGA_COMMON_H__
Pavel Machek5e2d70a2014-09-08 14:08:45 +02007
Pavel Machek5e2d70a2014-09-08 14:08:45 +02008/*
9 * High level configuration
10 */
Pavel Machek5e2d70a2014-09-08 14:08:45 +020011#define CONFIG_CLOCKS
12
Pavel Machek5e2d70a2014-09-08 14:08:45 +020013#define CONFIG_TIMESTAMP /* Print image info with timestamp */
14
15/*
16 * Memory configurations
17 */
Pavel Machek5e2d70a2014-09-08 14:08:45 +020018#define PHYS_SDRAM_1 0x0
Marek Vasut40f1d6b2014-11-04 04:25:09 +010019#define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024)
Ley Foon Tan10b69642017-04-26 02:44:46 +080020#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
Pavel Machek5e2d70a2014-09-08 14:08:45 +020021#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
Ley Foon Tane62883b2020-03-06 16:55:19 +080022#define CONFIG_SYS_INIT_RAM_SIZE SOCFPGA_PHYS_OCRAM_SIZE
Ley Foon Tan10b69642017-04-26 02:44:46 +080023#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
24#define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000
Simon Goldschmidtfb2965c2019-04-09 21:02:04 +020025/* SPL memory allocation configuration, this is for FAT implementation */
26#ifndef CONFIG_SYS_SPL_MALLOC_SIZE
27#define CONFIG_SYS_SPL_MALLOC_SIZE 0x10000
28#endif
Ley Foon Tane62883b2020-03-06 16:55:19 +080029#define CONFIG_SYS_INIT_RAM_SIZE (SOCFPGA_PHYS_OCRAM_SIZE - \
30 CONFIG_SYS_SPL_MALLOC_SIZE)
Simon Goldschmidtfb2965c2019-04-09 21:02:04 +020031#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_INIT_RAM_ADDR + \
32 CONFIG_SYS_INIT_RAM_SIZE)
Ley Foon Tan10b69642017-04-26 02:44:46 +080033#endif
Stefan Roesead4105f2018-10-30 10:00:22 +010034
35/*
36 * Some boards (e.g. socfpga_sr1500) use 8 bytes at the end of the internal
37 * SRAM as bootcounter storage. Make sure to not put the stack directly
38 * at this address to not overwrite the bootcounter by checking, if the
39 * bootcounter address is located in the internal SRAM.
40 */
41#if ((CONFIG_SYS_BOOTCOUNT_ADDR > CONFIG_SYS_INIT_RAM_ADDR) && \
42 (CONFIG_SYS_BOOTCOUNT_ADDR < (CONFIG_SYS_INIT_RAM_ADDR + \
43 CONFIG_SYS_INIT_RAM_SIZE)))
Simon Goldschmidtfb2965c2019-04-09 21:02:04 +020044#define CONFIG_SPL_STACK CONFIG_SYS_BOOTCOUNT_ADDR
Stefan Roesead4105f2018-10-30 10:00:22 +010045#else
Simon Goldschmidtfb2965c2019-04-09 21:02:04 +020046#define CONFIG_SPL_STACK \
Marek Vasutbb45f272018-04-26 22:23:05 +020047 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
Stefan Roesead4105f2018-10-30 10:00:22 +010048#endif
Pavel Machek5e2d70a2014-09-08 14:08:45 +020049
Simon Goldschmidtfb2965c2019-04-09 21:02:04 +020050/*
51 * U-Boot stack setup: if SPL post-reloc uses DDR stack, use it in pre-reloc
52 * phase of U-Boot, too. This prevents overwriting SPL data if stack/heap usage
53 * in U-Boot pre-reloc is higher than in SPL.
54 */
55#if defined(CONFIG_SPL_STACK_R_ADDR) && CONFIG_SPL_STACK_R_ADDR
56#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK_R_ADDR
57#else
58#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK
59#endif
60
Pavel Machek5e2d70a2014-09-08 14:08:45 +020061#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
Pavel Machek5e2d70a2014-09-08 14:08:45 +020062
63/*
64 * U-Boot general configurations
65 */
Pavel Machek5e2d70a2014-09-08 14:08:45 +020066#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
Pavel Machek5e2d70a2014-09-08 14:08:45 +020067 /* Print buffer size */
68#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
69#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
70 /* Boot argument buffer size */
Pavel Machek5e2d70a2014-09-08 14:08:45 +020071
72/*
73 * Cache
74 */
Pavel Machek5e2d70a2014-09-08 14:08:45 +020075#define CONFIG_SYS_L2_PL310
76#define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS
77
78/*
79 * Ethernet on SoC (EMAC)
80 */
Marek Vasut0d5abc92018-04-23 01:26:10 +020081#ifdef CONFIG_CMD_NET
Pavel Machek5e2d70a2014-09-08 14:08:45 +020082#define CONFIG_DW_ALTDESCRIPTOR
Pavel Machek5e2d70a2014-09-08 14:08:45 +020083#endif
84
85/*
86 * FPGA Driver
87 */
88#ifdef CONFIG_CMD_FPGA
Pavel Machek5e2d70a2014-09-08 14:08:45 +020089#define CONFIG_FPGA_COUNT 1
90#endif
Tien Fong Cheec5b16e12017-07-26 13:05:44 +080091
Pavel Machek5e2d70a2014-09-08 14:08:45 +020092/*
93 * L4 OSC1 Timer 0
94 */
Marek Vasutaaa40e72018-08-18 16:00:31 +020095#ifndef CONFIG_TIMER
Pavel Machek5e2d70a2014-09-08 14:08:45 +020096#define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
97#define CONFIG_SYS_TIMER_COUNTS_DOWN
98#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)
Marek Vasut979de712020-02-15 14:10:02 +010099#ifndef CONFIG_SYS_TIMER_RATE
Pavel Machek5e2d70a2014-09-08 14:08:45 +0200100#define CONFIG_SYS_TIMER_RATE 25000000
Marek Vasutaaa40e72018-08-18 16:00:31 +0200101#endif
Marek Vasut979de712020-02-15 14:10:02 +0100102#endif
Pavel Machek5e2d70a2014-09-08 14:08:45 +0200103
104/*
105 * L4 Watchdog
106 */
Pavel Machek5e2d70a2014-09-08 14:08:45 +0200107#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
108#define CONFIG_DW_WDT_CLOCK_KHZ 25000
Pavel Machek5e2d70a2014-09-08 14:08:45 +0200109
110/*
111 * MMC Driver
112 */
113#ifdef CONFIG_CMD_MMC
Pavel Machek5e2d70a2014-09-08 14:08:45 +0200114/* FIXME */
115/* using smaller max blk cnt to avoid flooding the limited stack we have */
116#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */
117#endif
118
Stefan Roese9a468c02014-11-07 12:37:52 +0100119/*
Marek Vasut7e442d92015-12-20 04:00:46 +0100120 * NAND Support
121 */
122#ifdef CONFIG_NAND_DENALI
Marek Vasutc48651e2020-02-15 14:10:09 +0100123#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
Marek Vasut7e442d92015-12-20 04:00:46 +0100124#define CONFIG_SYS_MAX_NAND_DEVICE 1
Marek Vasut7e442d92015-12-20 04:00:46 +0100125#define CONFIG_SYS_NAND_ONFI_DETECTION
Marek Vasut7e442d92015-12-20 04:00:46 +0100126#define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS
127#define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS
Marek Vasut7e442d92015-12-20 04:00:46 +0100128#endif
129
130/*
Stefan Roese9a468c02014-11-07 12:37:52 +0100131 * QSPI support
132 */
Stefan Roese9a468c02014-11-07 12:37:52 +0100133/* QSPI reference clock */
134#ifndef __ASSEMBLY__
135unsigned int cm_get_qspi_controller_clk_hz(void);
136#define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz()
137#endif
Stefan Roese9a468c02014-11-07 12:37:52 +0100138
Marek Vasutcabc3b42015-08-19 23:23:53 +0200139/*
Marek Vasut9f193122014-10-24 23:34:25 +0200140 * USB
141 */
Marek Vasut9f193122014-10-24 23:34:25 +0200142
143/*
Marek Vasut40f1d6b2014-11-04 04:25:09 +0100144 * USB Gadget (DFU, UMS)
145 */
146#if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
Marek Vasut4bd64e82016-10-29 21:15:56 +0200147#define CONFIG_SYS_DFU_DATA_BUF_SIZE (16 * 1024 * 1024)
Marek Vasut40f1d6b2014-11-04 04:25:09 +0100148#define DFU_DEFAULT_POLL_TIMEOUT 300
149
150/* USB IDs */
Sam Protsenkob706ffd2016-04-13 14:20:30 +0300151#define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525
152#define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5
Marek Vasut40f1d6b2014-11-04 04:25:09 +0100153#endif
154
155/*
Pavel Machek5e2d70a2014-09-08 14:08:45 +0200156 * U-Boot environment
157 */
Pavel Machek5e2d70a2014-09-08 14:08:45 +0200158
Chin Liang Seefb73f6d2015-12-21 21:02:45 +0800159/* Environment for SDMMC boot */
Tom Rini5cd7ece2019-11-18 20:02:10 -0500160#if defined(CONFIG_ENV_IS_IN_MMC)
Dalon Westergreenbfd74c62017-04-13 07:30:29 -0700161#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */
Chin Liang Seefb73f6d2015-12-21 21:02:45 +0800162#endif
163
Chin Liang See713e5b12016-02-24 16:50:22 +0800164/* Environment for QSPI boot */
Chin Liang See713e5b12016-02-24 16:50:22 +0800165
Pavel Machek5e2d70a2014-09-08 14:08:45 +0200166/*
167 * SPL
Marek Vasutea0123c2014-10-16 12:25:40 +0200168 *
Tien Fong Chee200ae352017-12-05 15:58:04 +0800169 * SRAM Memory layout for gen 5:
Marek Vasutea0123c2014-10-16 12:25:40 +0200170 *
171 * 0xFFFF_0000 ...... Start of SRAM
172 * 0xFFFF_xxxx ...... Top of stack (grows down)
Simon Goldschmidta3e50262019-04-09 21:02:03 +0200173 * 0xFFFF_yyyy ...... Global Data
174 * 0xFFFF_zzzz ...... Malloc area
175 * 0xFFFF_FFFF ...... End of SRAM
Tien Fong Chee200ae352017-12-05 15:58:04 +0800176 *
177 * SRAM Memory layout for Arria 10:
178 * 0xFFE0_0000 ...... Start of SRAM (bottom)
179 * 0xFFEx_xxxx ...... Top of stack (grows down to bottom)
180 * 0xFFEy_yyyy ...... Global Data
181 * 0xFFEz_zzzz ...... Malloc area (grows up to top)
182 * 0xFFE3_FFFF ...... End of SRAM (top)
Pavel Machek5e2d70a2014-09-08 14:08:45 +0200183 */
Simon Goldschmidt376a8f82019-03-15 20:44:32 +0100184#ifndef CONFIG_SPL_TEXT_BASE
Ley Foon Tan10b69642017-04-26 02:44:46 +0800185#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE
Simon Goldschmidt376a8f82019-03-15 20:44:32 +0100186#endif
Pavel Machek5e2d70a2014-09-08 14:08:45 +0200187
Marek Vasut1029caf2015-07-10 00:04:23 +0200188/* SPL SDMMC boot support */
189#ifdef CONFIG_SPL_MMC_SUPPORT
Tien Fong Chee6091dd12019-01-23 14:20:05 +0800190#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
Dalon Westergreen7c4c0c32019-08-07 10:37:36 -0700191#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
Dalon Westergreenbfd74c62017-04-13 07:30:29 -0700192#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
193#endif
194#else
195#ifndef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
196#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1
Marek Vasut1029caf2015-07-10 00:04:23 +0200197#endif
198#endif
Pavel Machek5e2d70a2014-09-08 14:08:45 +0200199
Marek Vasutcadf2f92015-07-21 07:50:03 +0200200/* SPL QSPI boot support */
Marek Vasutcadf2f92015-07-21 07:50:03 +0200201
Marek Vasut7e442d92015-12-20 04:00:46 +0100202/* SPL NAND boot support */
203#ifdef CONFIG_SPL_NAND_SUPPORT
Marek Vasutb5c087b2018-05-08 18:44:43 +0200204#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
Marek Vasut7e442d92015-12-20 04:00:46 +0100205#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
Marek Vasutb5c087b2018-05-08 18:44:43 +0200206#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
207#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x100000
208#endif
Marek Vasut7e442d92015-12-20 04:00:46 +0100209#endif
210
Dalon Westergreenbfd74c62017-04-13 07:30:29 -0700211/* Extra Environment */
212#ifndef CONFIG_SPL_BUILD
Dalon Westergreenbfd74c62017-04-13 07:30:29 -0700213
Simon Goldschmidt2e5d9a62018-01-25 07:18:27 +0100214#ifdef CONFIG_CMD_DHCP
215#define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na)
216#else
217#define BOOT_TARGET_DEVICES_DHCP(func)
218#endif
219
Joe Hershberger8e8594f2018-04-13 15:26:40 -0500220#if defined(CONFIG_CMD_PXE) && defined(CONFIG_CMD_DHCP)
Dalon Westergreenbfd74c62017-04-13 07:30:29 -0700221#define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na)
222#else
223#define BOOT_TARGET_DEVICES_PXE(func)
224#endif
225
226#ifdef CONFIG_CMD_MMC
227#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
228#else
229#define BOOT_TARGET_DEVICES_MMC(func)
230#endif
231
232#define BOOT_TARGET_DEVICES(func) \
233 BOOT_TARGET_DEVICES_MMC(func) \
234 BOOT_TARGET_DEVICES_PXE(func) \
Simon Goldschmidt2e5d9a62018-01-25 07:18:27 +0100235 BOOT_TARGET_DEVICES_DHCP(func)
Dalon Westergreenbfd74c62017-04-13 07:30:29 -0700236
237#include <config_distro_bootcmd.h>
238
239#ifndef CONFIG_EXTRA_ENV_SETTINGS
240#define CONFIG_EXTRA_ENV_SETTINGS \
241 "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
242 "bootm_size=0xa000000\0" \
243 "kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \
244 "fdt_addr_r=0x02000000\0" \
245 "scriptaddr=0x02100000\0" \
246 "pxefile_addr_r=0x02200000\0" \
247 "ramdisk_addr_r=0x02300000\0" \
Simon Goldschmidt0de397b2019-03-01 20:12:31 +0100248 "socfpga_legacy_reset_compat=1\0" \
Dalon Westergreenbfd74c62017-04-13 07:30:29 -0700249 BOOTENV
250
251#endif
252#endif
253
Dinh Nguyenf593acd2015-12-03 16:05:59 -0600254#endif /* __CONFIG_SOCFPGA_COMMON_H__ */