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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenk591dda52002-11-18 00:14:45 +00002/*
Graeme Russ45fc1d82011-04-13 19:43:26 +10003 * (C) Copyright 2008-2011
4 * Graeme Russ, <graeme.russ@gmail.com>
Graeme Russd11b0852009-11-24 20:04:18 +11005 *
wdenk591dda52002-11-18 00:14:45 +00006 * (C) Copyright 2002
Albert ARIBAUD60fbc8d2011-08-04 18:45:45 +02007 * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
wdenk591dda52002-11-18 00:14:45 +00008 *
Graeme Russc39acb42010-04-24 00:05:38 +10009 * Portions of this file are derived from the Linux kernel source
10 * Copyright (C) 1991, 1992 Linus Torvalds
wdenk591dda52002-11-18 00:14:45 +000011 */
12
Simon Glass754f55e2016-01-19 21:32:26 -070013#include <dm.h>
Heinrich Schuchardt954108d2019-08-25 19:55:12 +020014#include <efi_loader.h>
Simon Glassf11478f2019-12-28 10:45:07 -070015#include <hang.h>
Simon Glassda25eff2019-12-28 10:44:56 -070016#include <init.h>
Simon Glass21bb12a2020-02-06 09:54:58 -070017#include <irq.h>
Simon Glass9b61c7c2019-11-14 12:57:41 -070018#include <irq_func.h>
Stefan Reinauer2acf8482012-12-02 04:49:50 +000019#include <asm/control_regs.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060020#include <asm/global_data.h>
Bin Mengd538c362016-05-22 01:45:33 -070021#include <asm/i8259.h>
Graeme Russ0c8c62e2008-12-07 10:29:01 +110022#include <asm/interrupt.h>
Graeme Russ68699802011-02-12 15:11:28 +110023#include <asm/io.h>
Bin Mengd538c362016-05-22 01:45:33 -070024#include <asm/lapic.h>
Bin Mengd538c362016-05-22 01:45:33 -070025#include <asm/processor-flags.h>
Simon Glass6b9f0102020-05-10 11:40:06 -060026#include <asm/ptrace.h>
wdenk591dda52002-11-18 00:14:45 +000027
Simon Glassbb6306c2013-04-17 16:13:33 +000028DECLARE_GLOBAL_DATA_PTR;
29
Graeme Russd11b0852009-11-24 20:04:18 +110030#define DECLARE_INTERRUPT(x) \
31 ".globl irq_"#x"\n" \
Graeme Russ1aafcc92009-11-24 20:04:19 +110032 ".hidden irq_"#x"\n" \
33 ".type irq_"#x", @function\n" \
Graeme Russd11b0852009-11-24 20:04:18 +110034 "irq_"#x":\n" \
Graeme Russd11b0852009-11-24 20:04:18 +110035 "pushl $"#x"\n" \
J. Tang6c0712a2017-02-09 21:54:13 -050036 "jmp.d32 irq_common_entry\n"
wdenk591dda52002-11-18 00:14:45 +000037
Bin Mengfdebed82015-07-10 10:51:23 +080038static char *exceptions[] = {
39 "Divide Error",
40 "Debug",
41 "NMI Interrupt",
42 "Breakpoint",
43 "Overflow",
44 "BOUND Range Exceeded",
45 "Invalid Opcode (Undefined Opcode)",
Vagrant Cascadian973c0992019-05-03 14:28:37 -080046 "Device Not Available (No Math Coprocessor)",
Bin Mengfdebed82015-07-10 10:51:23 +080047 "Double Fault",
48 "Coprocessor Segment Overrun",
49 "Invalid TSS",
50 "Segment Not Present",
51 "Stack Segment Fault",
Simon Glassc4b9ef82015-07-31 09:31:32 -060052 "General Protection",
Bin Mengfdebed82015-07-10 10:51:23 +080053 "Page Fault",
54 "Reserved",
55 "x87 FPU Floating-Point Error",
56 "Alignment Check",
57 "Machine Check",
58 "SIMD Floating-Point Exception",
59 "Virtualization Exception",
60 "Reserved",
61 "Reserved",
62 "Reserved",
63 "Reserved",
64 "Reserved",
65 "Reserved",
66 "Reserved",
67 "Reserved",
68 "Reserved",
69 "Reserved",
70 "Reserved"
71};
72
Heinrich Schuchardt954108d2019-08-25 19:55:12 +020073/**
74 * show_efi_loaded_images() - show loaded UEFI images
75 *
76 * List all loaded UEFI images.
77 *
78 * @eip: instruction pointer
79 */
80static void show_efi_loaded_images(uintptr_t eip)
81{
82 efi_print_image_infos((void *)eip);
83}
84
Simon Glass83374332014-11-06 13:20:08 -070085static void dump_regs(struct irq_regs *regs)
Graeme Russc39acb42010-04-24 00:05:38 +100086{
Bin Meng9ff054b2015-07-10 10:38:32 +080087 unsigned long cs, eip, eflags;
Graeme Russc39acb42010-04-24 00:05:38 +100088 unsigned long cr0 = 0L, cr2 = 0L, cr3 = 0L, cr4 = 0L;
89 unsigned long d0, d1, d2, d3, d6, d7;
Graeme Russ68699802011-02-12 15:11:28 +110090 unsigned long sp;
Graeme Russc39acb42010-04-24 00:05:38 +100091
Bin Meng9ff054b2015-07-10 10:38:32 +080092 /*
93 * Some exceptions cause an error code to be saved on the current stack
94 * after the EIP value. We should extract CS/EIP/EFLAGS from different
95 * position on the stack based on the exception number.
96 */
97 switch (regs->irq_id) {
98 case EXC_DF:
99 case EXC_TS:
100 case EXC_NP:
101 case EXC_SS:
102 case EXC_GP:
103 case EXC_PF:
104 case EXC_AC:
105 cs = regs->context.ctx2.xcs;
106 eip = regs->context.ctx2.eip;
107 eflags = regs->context.ctx2.eflags;
108 /* We should fix up the ESP due to error code */
109 regs->esp += 4;
110 break;
111 default:
112 cs = regs->context.ctx1.xcs;
113 eip = regs->context.ctx1.eip;
114 eflags = regs->context.ctx1.eflags;
115 break;
116 }
117
Graeme Russc39acb42010-04-24 00:05:38 +1000118 printf("EIP: %04x:[<%08lx>] EFLAGS: %08lx\n",
Bin Meng9ff054b2015-07-10 10:38:32 +0800119 (u16)cs, eip, eflags);
Simon Glass79dd4342015-08-10 22:02:54 -0600120 if (gd->flags & GD_FLG_RELOC)
121 printf("Original EIP :[<%08lx>]\n", eip - gd->reloc_off);
Graeme Russc39acb42010-04-24 00:05:38 +1000122
123 printf("EAX: %08lx EBX: %08lx ECX: %08lx EDX: %08lx\n",
124 regs->eax, regs->ebx, regs->ecx, regs->edx);
125 printf("ESI: %08lx EDI: %08lx EBP: %08lx ESP: %08lx\n",
126 regs->esi, regs->edi, regs->ebp, regs->esp);
127 printf(" DS: %04x ES: %04x FS: %04x GS: %04x SS: %04x\n",
Graeme Russfdee8b12011-11-08 02:33:13 +0000128 (u16)regs->xds, (u16)regs->xes, (u16)regs->xfs,
129 (u16)regs->xgs, (u16)regs->xss);
Graeme Russc39acb42010-04-24 00:05:38 +1000130
131 cr0 = read_cr0();
132 cr2 = read_cr2();
133 cr3 = read_cr3();
134 cr4 = read_cr4();
135
136 printf("CR0: %08lx CR2: %08lx CR3: %08lx CR4: %08lx\n",
137 cr0, cr2, cr3, cr4);
138
139 d0 = get_debugreg(0);
140 d1 = get_debugreg(1);
141 d2 = get_debugreg(2);
142 d3 = get_debugreg(3);
143
144 printf("DR0: %08lx DR1: %08lx DR2: %08lx DR3: %08lx\n",
145 d0, d1, d2, d3);
146
147 d6 = get_debugreg(6);
148 d7 = get_debugreg(7);
149 printf("DR6: %08lx DR7: %08lx\n",
150 d6, d7);
Graeme Russ68699802011-02-12 15:11:28 +1100151
152 printf("Stack:\n");
153 sp = regs->esp;
154
155 sp += 64;
156
157 while (sp > (regs->esp - 16)) {
158 if (sp == regs->esp)
159 printf("--->");
160 else
161 printf(" ");
162 printf("0x%8.8lx : 0x%8.8lx\n", sp, (ulong)readl(sp));
163 sp -= 4;
164 }
Heinrich Schuchardt954108d2019-08-25 19:55:12 +0200165 show_efi_loaded_images(eip);
Graeme Russc39acb42010-04-24 00:05:38 +1000166}
167
Bin Mengfdebed82015-07-10 10:51:23 +0800168static void do_exception(struct irq_regs *regs)
169{
170 printf("%s\n", exceptions[regs->irq_id]);
171 dump_regs(regs);
172 hang();
173}
174
wdenk591dda52002-11-18 00:14:45 +0000175struct idt_entry {
176 u16 base_low;
177 u16 selector;
178 u8 res;
179 u8 access;
180 u16 base_high;
Graeme Russfdee8b12011-11-08 02:33:13 +0000181} __packed;
wdenk591dda52002-11-18 00:14:45 +0000182
Graeme Russaf3f2c82011-12-19 14:26:18 +1100183struct idt_entry idt[256] __aligned(16);
wdenk591dda52002-11-18 00:14:45 +0000184
Simon Glass495afca2020-11-04 09:57:28 -0700185struct idt_ptr idt_ptr;
wdenk591dda52002-11-18 00:14:45 +0000186
Simon Glass495afca2020-11-04 09:57:28 -0700187static inline void load_idt(const struct idt_ptr *dtr)
Graeme Russd11b0852009-11-24 20:04:18 +1100188{
Graeme Russfdee8b12011-11-08 02:33:13 +0000189 asm volatile("cs lidt %0" : : "m" (*dtr));
Graeme Russd11b0852009-11-24 20:04:18 +1100190}
wdenk591dda52002-11-18 00:14:45 +0000191
Graeme Russ77290ee2009-02-24 21:13:40 +1100192void set_vector(u8 intnum, void *routine)
wdenk591dda52002-11-18 00:14:45 +0000193{
Simon Glassb58770f2016-09-25 21:33:25 -0600194 idt[intnum].base_high = (u16)((ulong)(routine) >> 16);
195 idt[intnum].base_low = (u16)((ulong)(routine) & 0xffff);
wdenk591dda52002-11-18 00:14:45 +0000196}
197
Graeme Russfdee8b12011-11-08 02:33:13 +0000198/*
199 * Ideally these would be defined static to avoid a checkpatch warning, but
200 * the compiler cannot see them in the inline asm and complains that they
201 * aren't defined
202 */
Graeme Russd11b0852009-11-24 20:04:18 +1100203void irq_0(void);
204void irq_1(void);
wdenk591dda52002-11-18 00:14:45 +0000205
Graeme Russ77290ee2009-02-24 21:13:40 +1100206int cpu_init_interrupts(void)
wdenk591dda52002-11-18 00:14:45 +0000207{
208 int i;
wdenk57b2d802003-06-27 21:31:46 +0000209
Graeme Russd11b0852009-11-24 20:04:18 +1100210 int irq_entry_size = irq_1 - irq_0;
211 void *irq_entry = (void *)irq_0;
212
wdenk591dda52002-11-18 00:14:45 +0000213 /* Setup the IDT */
Graeme Russfdee8b12011-11-08 02:33:13 +0000214 for (i = 0; i < 256; i++) {
wdenk591dda52002-11-18 00:14:45 +0000215 idt[i].access = 0x8e;
wdenk57b2d802003-06-27 21:31:46 +0000216 idt[i].res = 0;
Simon Glassc4b9ef82015-07-31 09:31:32 -0600217 idt[i].selector = X86_GDT_ENTRY_32BIT_CS * X86_GDT_ENTRY_SIZE;
Graeme Russd11b0852009-11-24 20:04:18 +1100218 set_vector(i, irq_entry);
219 irq_entry += irq_entry_size;
wdenk57b2d802003-06-27 21:31:46 +0000220 }
221
Simon Glassc4b9ef82015-07-31 09:31:32 -0600222 idt_ptr.size = 256 * 8 - 1;
Graeme Russd11b0852009-11-24 20:04:18 +1100223 idt_ptr.address = (unsigned long) idt;
Graeme Russd11b0852009-11-24 20:04:18 +1100224
225 load_idt(&idt_ptr);
wdenk57b2d802003-06-27 21:31:46 +0000226
wdenk591dda52002-11-18 00:14:45 +0000227 return 0;
228}
229
Simon Glass495afca2020-11-04 09:57:28 -0700230void interrupt_read_idt(struct idt_ptr *ptr)
231{
232 asm volatile("sidt %0" : : "m" (*ptr));
233}
234
Simon Glass98d7e982015-04-28 20:25:16 -0600235void *x86_get_idt(void)
236{
237 return &idt_ptr;
238}
239
Graeme Russd11b0852009-11-24 20:04:18 +1100240void __do_irq(int irq)
241{
242 printf("Unhandled IRQ : %d\n", irq);
243}
244void do_irq(int irq) __attribute__((weak, alias("__do_irq")));
245
wdenk591dda52002-11-18 00:14:45 +0000246void enable_interrupts(void)
247{
248 asm("sti\n");
249}
250
251int disable_interrupts(void)
252{
253 long flags;
wdenk57b2d802003-06-27 21:31:46 +0000254
Simon Glass1560a632017-01-16 07:04:00 -0700255#if CONFIG_IS_ENABLED(X86_64)
Simon Glass87086d52016-09-25 21:33:23 -0600256 asm volatile ("pushfq ; popq %0 ; cli\n" : "=g" (flags) : );
257#else
wdenk591dda52002-11-18 00:14:45 +0000258 asm volatile ("pushfl ; popl %0 ; cli\n" : "=g" (flags) : );
Simon Glass87086d52016-09-25 21:33:23 -0600259#endif
Graeme Russfdee8b12011-11-08 02:33:13 +0000260 return flags & X86_EFLAGS_IF;
wdenk591dda52002-11-18 00:14:45 +0000261}
Graeme Russd11b0852009-11-24 20:04:18 +1100262
Bin Mengcb9d9cb2014-11-20 16:11:16 +0800263int interrupt_init(void)
264{
Simon Glass754f55e2016-01-19 21:32:26 -0700265 struct udevice *dev;
266 int ret;
267
Simon Glass41941572023-07-15 21:38:40 -0600268 /*
269 * When running as an EFI application we are not in control of
270 * interrupts and should leave them alone.
271 */
Simon Glass8b8e7542020-04-26 09:12:55 -0600272 if (!ll_boot_init())
273 return 0;
274
Simon Glass754f55e2016-01-19 21:32:26 -0700275 /* Try to set up the interrupt router, but don't require one */
Simon Glass21bb12a2020-02-06 09:54:58 -0700276 ret = irq_first_device_type(X86_IRQT_BASE, &dev);
Simon Glass754f55e2016-01-19 21:32:26 -0700277 if (ret && ret != -ENODEV)
278 return ret;
279
Bin Mengcb9d9cb2014-11-20 16:11:16 +0800280 /* Just in case... */
281 disable_interrupts();
282
Bin Mengb29a08c2015-10-22 19:13:30 -0700283#ifdef CONFIG_I8259_PIC
Bin Mengcb9d9cb2014-11-20 16:11:16 +0800284 /* Initialize the master/slave i8259 pic */
285 i8259_init();
286#endif
287
Hannes Schmelzerd18df3c2018-11-18 23:19:43 +0100288#ifdef CONFIG_APIC
Bin Mengd538c362016-05-22 01:45:33 -0700289 lapic_setup();
Hannes Schmelzerd18df3c2018-11-18 23:19:43 +0100290#endif
Bin Mengd538c362016-05-22 01:45:33 -0700291
Bin Mengcb9d9cb2014-11-20 16:11:16 +0800292 /* Initialize core interrupt and exception functionality of CPU */
293 cpu_init_interrupts();
294
Simon Glass41941572023-07-15 21:38:40 -0600295 /* It is now safe to enable interrupts */
Simon Glass8b8e7542020-04-26 09:12:55 -0600296 enable_interrupts();
Bin Mengcb9d9cb2014-11-20 16:11:16 +0800297
298 return 0;
299}
300
Graeme Russd11b0852009-11-24 20:04:18 +1100301/* IRQ Low-Level Service Routine */
Graeme Russ43261532010-10-07 20:03:23 +1100302void irq_llsr(struct irq_regs *regs)
Graeme Russd11b0852009-11-24 20:04:18 +1100303{
304 /*
305 * For detailed description of each exception, refer to:
Albert ARIBAUD60fbc8d2011-08-04 18:45:45 +0200306 * Intel® 64 and IA-32 Architectures Software Developer's Manual
Graeme Russd11b0852009-11-24 20:04:18 +1100307 * Volume 1: Basic Architecture
308 * Order Number: 253665-029US, November 2008
309 * Table 6-1. Exceptions and Interrupts
310 */
Bin Mengfdebed82015-07-10 10:51:23 +0800311 if (regs->irq_id < 32) {
312 /* Architecture defined exception */
313 do_exception(regs);
314 } else {
Graeme Russd11b0852009-11-24 20:04:18 +1100315 /* Hardware or User IRQ */
Graeme Russ43261532010-10-07 20:03:23 +1100316 do_irq(regs->irq_id);
Graeme Russd11b0852009-11-24 20:04:18 +1100317 }
318}
319
320/*
321 * OK - This looks really horrible, but it serves a purpose - It helps create
322 * fully relocatable code.
323 * - The call to irq_llsr will be a relative jump
324 * - The IRQ entries will be guaranteed to be in order
Graeme Russc39acb42010-04-24 00:05:38 +1000325 * Interrupt entries are now very small (a push and a jump) but they are
326 * now slower (all registers pushed on stack which provides complete
327 * crash dumps in the low level handlers
Graeme Russ43261532010-10-07 20:03:23 +1100328 *
329 * Interrupt Entry Point:
330 * - Interrupt has caused eflags, CS and EIP to be pushed
331 * - Interrupt Vector Handler has pushed orig_eax
332 * - pt_regs.esp needs to be adjusted by 40 bytes:
333 * 12 bytes pushed by CPU (EFLAGSF, CS, EIP)
334 * 4 bytes pushed by vector handler (irq_id)
335 * 24 bytes pushed before SP (SS, GS, FS, ES, DS, EAX)
336 * NOTE: Only longs are pushed on/popped off the stack!
Graeme Russd11b0852009-11-24 20:04:18 +1100337 */
338asm(".globl irq_common_entry\n" \
Graeme Russ1aafcc92009-11-24 20:04:19 +1100339 ".hidden irq_common_entry\n" \
340 ".type irq_common_entry, @function\n" \
Graeme Russd11b0852009-11-24 20:04:18 +1100341 "irq_common_entry:\n" \
Graeme Russc39acb42010-04-24 00:05:38 +1000342 "cld\n" \
Graeme Russ43261532010-10-07 20:03:23 +1100343 "pushl %ss\n" \
Graeme Russc39acb42010-04-24 00:05:38 +1000344 "pushl %gs\n" \
345 "pushl %fs\n" \
346 "pushl %es\n" \
347 "pushl %ds\n" \
348 "pushl %eax\n" \
Graeme Russ43261532010-10-07 20:03:23 +1100349 "movl %esp, %eax\n" \
350 "addl $40, %eax\n" \
351 "pushl %eax\n" \
Graeme Russc39acb42010-04-24 00:05:38 +1000352 "pushl %ebp\n" \
353 "pushl %edi\n" \
354 "pushl %esi\n" \
355 "pushl %edx\n" \
356 "pushl %ecx\n" \
357 "pushl %ebx\n" \
358 "mov %esp, %eax\n" \
Graeme Russd11b0852009-11-24 20:04:18 +1100359 "call irq_llsr\n" \
Graeme Russc39acb42010-04-24 00:05:38 +1000360 "popl %ebx\n" \
361 "popl %ecx\n" \
362 "popl %edx\n" \
363 "popl %esi\n" \
364 "popl %edi\n" \
365 "popl %ebp\n" \
366 "popl %eax\n" \
Graeme Russ43261532010-10-07 20:03:23 +1100367 "popl %eax\n" \
Graeme Russc39acb42010-04-24 00:05:38 +1000368 "popl %ds\n" \
369 "popl %es\n" \
370 "popl %fs\n" \
371 "popl %gs\n" \
Graeme Russ43261532010-10-07 20:03:23 +1100372 "popl %ss\n" \
Graeme Russc39acb42010-04-24 00:05:38 +1000373 "add $4, %esp\n" \
Graeme Russd11b0852009-11-24 20:04:18 +1100374 "iret\n" \
375 DECLARE_INTERRUPT(0) \
376 DECLARE_INTERRUPT(1) \
377 DECLARE_INTERRUPT(2) \
378 DECLARE_INTERRUPT(3) \
379 DECLARE_INTERRUPT(4) \
380 DECLARE_INTERRUPT(5) \
381 DECLARE_INTERRUPT(6) \
382 DECLARE_INTERRUPT(7) \
383 DECLARE_INTERRUPT(8) \
384 DECLARE_INTERRUPT(9) \
385 DECLARE_INTERRUPT(10) \
386 DECLARE_INTERRUPT(11) \
387 DECLARE_INTERRUPT(12) \
388 DECLARE_INTERRUPT(13) \
389 DECLARE_INTERRUPT(14) \
390 DECLARE_INTERRUPT(15) \
391 DECLARE_INTERRUPT(16) \
392 DECLARE_INTERRUPT(17) \
393 DECLARE_INTERRUPT(18) \
394 DECLARE_INTERRUPT(19) \
395 DECLARE_INTERRUPT(20) \
396 DECLARE_INTERRUPT(21) \
397 DECLARE_INTERRUPT(22) \
398 DECLARE_INTERRUPT(23) \
399 DECLARE_INTERRUPT(24) \
400 DECLARE_INTERRUPT(25) \
401 DECLARE_INTERRUPT(26) \
402 DECLARE_INTERRUPT(27) \
403 DECLARE_INTERRUPT(28) \
404 DECLARE_INTERRUPT(29) \
405 DECLARE_INTERRUPT(30) \
406 DECLARE_INTERRUPT(31) \
407 DECLARE_INTERRUPT(32) \
408 DECLARE_INTERRUPT(33) \
409 DECLARE_INTERRUPT(34) \
410 DECLARE_INTERRUPT(35) \
411 DECLARE_INTERRUPT(36) \
412 DECLARE_INTERRUPT(37) \
413 DECLARE_INTERRUPT(38) \
414 DECLARE_INTERRUPT(39) \
415 DECLARE_INTERRUPT(40) \
416 DECLARE_INTERRUPT(41) \
417 DECLARE_INTERRUPT(42) \
418 DECLARE_INTERRUPT(43) \
419 DECLARE_INTERRUPT(44) \
420 DECLARE_INTERRUPT(45) \
421 DECLARE_INTERRUPT(46) \
422 DECLARE_INTERRUPT(47) \
423 DECLARE_INTERRUPT(48) \
424 DECLARE_INTERRUPT(49) \
425 DECLARE_INTERRUPT(50) \
426 DECLARE_INTERRUPT(51) \
427 DECLARE_INTERRUPT(52) \
428 DECLARE_INTERRUPT(53) \
429 DECLARE_INTERRUPT(54) \
430 DECLARE_INTERRUPT(55) \
431 DECLARE_INTERRUPT(56) \
432 DECLARE_INTERRUPT(57) \
433 DECLARE_INTERRUPT(58) \
434 DECLARE_INTERRUPT(59) \
435 DECLARE_INTERRUPT(60) \
436 DECLARE_INTERRUPT(61) \
437 DECLARE_INTERRUPT(62) \
438 DECLARE_INTERRUPT(63) \
439 DECLARE_INTERRUPT(64) \
440 DECLARE_INTERRUPT(65) \
441 DECLARE_INTERRUPT(66) \
442 DECLARE_INTERRUPT(67) \
443 DECLARE_INTERRUPT(68) \
444 DECLARE_INTERRUPT(69) \
445 DECLARE_INTERRUPT(70) \
446 DECLARE_INTERRUPT(71) \
447 DECLARE_INTERRUPT(72) \
448 DECLARE_INTERRUPT(73) \
449 DECLARE_INTERRUPT(74) \
450 DECLARE_INTERRUPT(75) \
451 DECLARE_INTERRUPT(76) \
452 DECLARE_INTERRUPT(77) \
453 DECLARE_INTERRUPT(78) \
454 DECLARE_INTERRUPT(79) \
455 DECLARE_INTERRUPT(80) \
456 DECLARE_INTERRUPT(81) \
457 DECLARE_INTERRUPT(82) \
458 DECLARE_INTERRUPT(83) \
459 DECLARE_INTERRUPT(84) \
460 DECLARE_INTERRUPT(85) \
461 DECLARE_INTERRUPT(86) \
462 DECLARE_INTERRUPT(87) \
463 DECLARE_INTERRUPT(88) \
464 DECLARE_INTERRUPT(89) \
465 DECLARE_INTERRUPT(90) \
466 DECLARE_INTERRUPT(91) \
467 DECLARE_INTERRUPT(92) \
468 DECLARE_INTERRUPT(93) \
469 DECLARE_INTERRUPT(94) \
470 DECLARE_INTERRUPT(95) \
471 DECLARE_INTERRUPT(97) \
472 DECLARE_INTERRUPT(96) \
473 DECLARE_INTERRUPT(98) \
474 DECLARE_INTERRUPT(99) \
475 DECLARE_INTERRUPT(100) \
476 DECLARE_INTERRUPT(101) \
477 DECLARE_INTERRUPT(102) \
478 DECLARE_INTERRUPT(103) \
479 DECLARE_INTERRUPT(104) \
480 DECLARE_INTERRUPT(105) \
481 DECLARE_INTERRUPT(106) \
482 DECLARE_INTERRUPT(107) \
483 DECLARE_INTERRUPT(108) \
484 DECLARE_INTERRUPT(109) \
485 DECLARE_INTERRUPT(110) \
486 DECLARE_INTERRUPT(111) \
487 DECLARE_INTERRUPT(112) \
488 DECLARE_INTERRUPT(113) \
489 DECLARE_INTERRUPT(114) \
490 DECLARE_INTERRUPT(115) \
491 DECLARE_INTERRUPT(116) \
492 DECLARE_INTERRUPT(117) \
493 DECLARE_INTERRUPT(118) \
494 DECLARE_INTERRUPT(119) \
495 DECLARE_INTERRUPT(120) \
496 DECLARE_INTERRUPT(121) \
497 DECLARE_INTERRUPT(122) \
498 DECLARE_INTERRUPT(123) \
499 DECLARE_INTERRUPT(124) \
500 DECLARE_INTERRUPT(125) \
501 DECLARE_INTERRUPT(126) \
502 DECLARE_INTERRUPT(127) \
503 DECLARE_INTERRUPT(128) \
504 DECLARE_INTERRUPT(129) \
505 DECLARE_INTERRUPT(130) \
506 DECLARE_INTERRUPT(131) \
507 DECLARE_INTERRUPT(132) \
508 DECLARE_INTERRUPT(133) \
509 DECLARE_INTERRUPT(134) \
510 DECLARE_INTERRUPT(135) \
511 DECLARE_INTERRUPT(136) \
512 DECLARE_INTERRUPT(137) \
513 DECLARE_INTERRUPT(138) \
514 DECLARE_INTERRUPT(139) \
515 DECLARE_INTERRUPT(140) \
516 DECLARE_INTERRUPT(141) \
517 DECLARE_INTERRUPT(142) \
518 DECLARE_INTERRUPT(143) \
519 DECLARE_INTERRUPT(144) \
520 DECLARE_INTERRUPT(145) \
521 DECLARE_INTERRUPT(146) \
522 DECLARE_INTERRUPT(147) \
523 DECLARE_INTERRUPT(148) \
524 DECLARE_INTERRUPT(149) \
525 DECLARE_INTERRUPT(150) \
526 DECLARE_INTERRUPT(151) \
527 DECLARE_INTERRUPT(152) \
528 DECLARE_INTERRUPT(153) \
529 DECLARE_INTERRUPT(154) \
530 DECLARE_INTERRUPT(155) \
531 DECLARE_INTERRUPT(156) \
532 DECLARE_INTERRUPT(157) \
533 DECLARE_INTERRUPT(158) \
534 DECLARE_INTERRUPT(159) \
535 DECLARE_INTERRUPT(160) \
536 DECLARE_INTERRUPT(161) \
537 DECLARE_INTERRUPT(162) \
538 DECLARE_INTERRUPT(163) \
539 DECLARE_INTERRUPT(164) \
540 DECLARE_INTERRUPT(165) \
541 DECLARE_INTERRUPT(166) \
542 DECLARE_INTERRUPT(167) \
543 DECLARE_INTERRUPT(168) \
544 DECLARE_INTERRUPT(169) \
545 DECLARE_INTERRUPT(170) \
546 DECLARE_INTERRUPT(171) \
547 DECLARE_INTERRUPT(172) \
548 DECLARE_INTERRUPT(173) \
549 DECLARE_INTERRUPT(174) \
550 DECLARE_INTERRUPT(175) \
551 DECLARE_INTERRUPT(176) \
552 DECLARE_INTERRUPT(177) \
553 DECLARE_INTERRUPT(178) \
554 DECLARE_INTERRUPT(179) \
555 DECLARE_INTERRUPT(180) \
556 DECLARE_INTERRUPT(181) \
557 DECLARE_INTERRUPT(182) \
558 DECLARE_INTERRUPT(183) \
559 DECLARE_INTERRUPT(184) \
560 DECLARE_INTERRUPT(185) \
561 DECLARE_INTERRUPT(186) \
562 DECLARE_INTERRUPT(187) \
563 DECLARE_INTERRUPT(188) \
564 DECLARE_INTERRUPT(189) \
565 DECLARE_INTERRUPT(190) \
566 DECLARE_INTERRUPT(191) \
567 DECLARE_INTERRUPT(192) \
568 DECLARE_INTERRUPT(193) \
569 DECLARE_INTERRUPT(194) \
570 DECLARE_INTERRUPT(195) \
571 DECLARE_INTERRUPT(196) \
572 DECLARE_INTERRUPT(197) \
573 DECLARE_INTERRUPT(198) \
574 DECLARE_INTERRUPT(199) \
575 DECLARE_INTERRUPT(200) \
576 DECLARE_INTERRUPT(201) \
577 DECLARE_INTERRUPT(202) \
578 DECLARE_INTERRUPT(203) \
579 DECLARE_INTERRUPT(204) \
580 DECLARE_INTERRUPT(205) \
581 DECLARE_INTERRUPT(206) \
582 DECLARE_INTERRUPT(207) \
583 DECLARE_INTERRUPT(208) \
584 DECLARE_INTERRUPT(209) \
585 DECLARE_INTERRUPT(210) \
586 DECLARE_INTERRUPT(211) \
587 DECLARE_INTERRUPT(212) \
588 DECLARE_INTERRUPT(213) \
589 DECLARE_INTERRUPT(214) \
590 DECLARE_INTERRUPT(215) \
591 DECLARE_INTERRUPT(216) \
592 DECLARE_INTERRUPT(217) \
593 DECLARE_INTERRUPT(218) \
594 DECLARE_INTERRUPT(219) \
595 DECLARE_INTERRUPT(220) \
596 DECLARE_INTERRUPT(221) \
597 DECLARE_INTERRUPT(222) \
598 DECLARE_INTERRUPT(223) \
599 DECLARE_INTERRUPT(224) \
600 DECLARE_INTERRUPT(225) \
601 DECLARE_INTERRUPT(226) \
602 DECLARE_INTERRUPT(227) \
603 DECLARE_INTERRUPT(228) \
604 DECLARE_INTERRUPT(229) \
605 DECLARE_INTERRUPT(230) \
606 DECLARE_INTERRUPT(231) \
607 DECLARE_INTERRUPT(232) \
608 DECLARE_INTERRUPT(233) \
609 DECLARE_INTERRUPT(234) \
610 DECLARE_INTERRUPT(235) \
611 DECLARE_INTERRUPT(236) \
612 DECLARE_INTERRUPT(237) \
613 DECLARE_INTERRUPT(238) \
614 DECLARE_INTERRUPT(239) \
615 DECLARE_INTERRUPT(240) \
616 DECLARE_INTERRUPT(241) \
617 DECLARE_INTERRUPT(242) \
618 DECLARE_INTERRUPT(243) \
619 DECLARE_INTERRUPT(244) \
620 DECLARE_INTERRUPT(245) \
621 DECLARE_INTERRUPT(246) \
622 DECLARE_INTERRUPT(247) \
623 DECLARE_INTERRUPT(248) \
624 DECLARE_INTERRUPT(249) \
625 DECLARE_INTERRUPT(250) \
626 DECLARE_INTERRUPT(251) \
627 DECLARE_INTERRUPT(252) \
628 DECLARE_INTERRUPT(253) \
629 DECLARE_INTERRUPT(254) \
630 DECLARE_INTERRUPT(255));