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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenk591dda52002-11-18 00:14:45 +00002/*
Graeme Russ45fc1d82011-04-13 19:43:26 +10003 * (C) Copyright 2008-2011
4 * Graeme Russ, <graeme.russ@gmail.com>
Graeme Russd11b0852009-11-24 20:04:18 +11005 *
wdenk591dda52002-11-18 00:14:45 +00006 * (C) Copyright 2002
Albert ARIBAUD60fbc8d2011-08-04 18:45:45 +02007 * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
wdenk591dda52002-11-18 00:14:45 +00008 *
Graeme Russc39acb42010-04-24 00:05:38 +10009 * Portions of this file are derived from the Linux kernel source
10 * Copyright (C) 1991, 1992 Linus Torvalds
wdenk591dda52002-11-18 00:14:45 +000011 */
12
13#include <common.h>
Simon Glass754f55e2016-01-19 21:32:26 -070014#include <dm.h>
Heinrich Schuchardt954108d2019-08-25 19:55:12 +020015#include <efi_loader.h>
Simon Glassda25eff2019-12-28 10:44:56 -070016#include <init.h>
Simon Glass9b61c7c2019-11-14 12:57:41 -070017#include <irq_func.h>
Stefan Reinauer2acf8482012-12-02 04:49:50 +000018#include <asm/control_regs.h>
Bin Mengd538c362016-05-22 01:45:33 -070019#include <asm/i8259.h>
Graeme Russ0c8c62e2008-12-07 10:29:01 +110020#include <asm/interrupt.h>
Graeme Russ68699802011-02-12 15:11:28 +110021#include <asm/io.h>
Bin Mengd538c362016-05-22 01:45:33 -070022#include <asm/lapic.h>
Bin Mengd538c362016-05-22 01:45:33 -070023#include <asm/processor-flags.h>
wdenk591dda52002-11-18 00:14:45 +000024
Simon Glassbb6306c2013-04-17 16:13:33 +000025DECLARE_GLOBAL_DATA_PTR;
26
Graeme Russd11b0852009-11-24 20:04:18 +110027#define DECLARE_INTERRUPT(x) \
28 ".globl irq_"#x"\n" \
Graeme Russ1aafcc92009-11-24 20:04:19 +110029 ".hidden irq_"#x"\n" \
30 ".type irq_"#x", @function\n" \
Graeme Russd11b0852009-11-24 20:04:18 +110031 "irq_"#x":\n" \
Graeme Russd11b0852009-11-24 20:04:18 +110032 "pushl $"#x"\n" \
J. Tang6c0712a2017-02-09 21:54:13 -050033 "jmp.d32 irq_common_entry\n"
wdenk591dda52002-11-18 00:14:45 +000034
Bin Mengfdebed82015-07-10 10:51:23 +080035static char *exceptions[] = {
36 "Divide Error",
37 "Debug",
38 "NMI Interrupt",
39 "Breakpoint",
40 "Overflow",
41 "BOUND Range Exceeded",
42 "Invalid Opcode (Undefined Opcode)",
Vagrant Cascadian973c0992019-05-03 14:28:37 -080043 "Device Not Available (No Math Coprocessor)",
Bin Mengfdebed82015-07-10 10:51:23 +080044 "Double Fault",
45 "Coprocessor Segment Overrun",
46 "Invalid TSS",
47 "Segment Not Present",
48 "Stack Segment Fault",
Simon Glassc4b9ef82015-07-31 09:31:32 -060049 "General Protection",
Bin Mengfdebed82015-07-10 10:51:23 +080050 "Page Fault",
51 "Reserved",
52 "x87 FPU Floating-Point Error",
53 "Alignment Check",
54 "Machine Check",
55 "SIMD Floating-Point Exception",
56 "Virtualization Exception",
57 "Reserved",
58 "Reserved",
59 "Reserved",
60 "Reserved",
61 "Reserved",
62 "Reserved",
63 "Reserved",
64 "Reserved",
65 "Reserved",
66 "Reserved",
67 "Reserved"
68};
69
Heinrich Schuchardt954108d2019-08-25 19:55:12 +020070/**
71 * show_efi_loaded_images() - show loaded UEFI images
72 *
73 * List all loaded UEFI images.
74 *
75 * @eip: instruction pointer
76 */
77static void show_efi_loaded_images(uintptr_t eip)
78{
79 efi_print_image_infos((void *)eip);
80}
81
Simon Glass83374332014-11-06 13:20:08 -070082static void dump_regs(struct irq_regs *regs)
Graeme Russc39acb42010-04-24 00:05:38 +100083{
Bin Meng9ff054b2015-07-10 10:38:32 +080084 unsigned long cs, eip, eflags;
Graeme Russc39acb42010-04-24 00:05:38 +100085 unsigned long cr0 = 0L, cr2 = 0L, cr3 = 0L, cr4 = 0L;
86 unsigned long d0, d1, d2, d3, d6, d7;
Graeme Russ68699802011-02-12 15:11:28 +110087 unsigned long sp;
Graeme Russc39acb42010-04-24 00:05:38 +100088
Bin Meng9ff054b2015-07-10 10:38:32 +080089 /*
90 * Some exceptions cause an error code to be saved on the current stack
91 * after the EIP value. We should extract CS/EIP/EFLAGS from different
92 * position on the stack based on the exception number.
93 */
94 switch (regs->irq_id) {
95 case EXC_DF:
96 case EXC_TS:
97 case EXC_NP:
98 case EXC_SS:
99 case EXC_GP:
100 case EXC_PF:
101 case EXC_AC:
102 cs = regs->context.ctx2.xcs;
103 eip = regs->context.ctx2.eip;
104 eflags = regs->context.ctx2.eflags;
105 /* We should fix up the ESP due to error code */
106 regs->esp += 4;
107 break;
108 default:
109 cs = regs->context.ctx1.xcs;
110 eip = regs->context.ctx1.eip;
111 eflags = regs->context.ctx1.eflags;
112 break;
113 }
114
Graeme Russc39acb42010-04-24 00:05:38 +1000115 printf("EIP: %04x:[<%08lx>] EFLAGS: %08lx\n",
Bin Meng9ff054b2015-07-10 10:38:32 +0800116 (u16)cs, eip, eflags);
Simon Glass79dd4342015-08-10 22:02:54 -0600117 if (gd->flags & GD_FLG_RELOC)
118 printf("Original EIP :[<%08lx>]\n", eip - gd->reloc_off);
Graeme Russc39acb42010-04-24 00:05:38 +1000119
120 printf("EAX: %08lx EBX: %08lx ECX: %08lx EDX: %08lx\n",
121 regs->eax, regs->ebx, regs->ecx, regs->edx);
122 printf("ESI: %08lx EDI: %08lx EBP: %08lx ESP: %08lx\n",
123 regs->esi, regs->edi, regs->ebp, regs->esp);
124 printf(" DS: %04x ES: %04x FS: %04x GS: %04x SS: %04x\n",
Graeme Russfdee8b12011-11-08 02:33:13 +0000125 (u16)regs->xds, (u16)regs->xes, (u16)regs->xfs,
126 (u16)regs->xgs, (u16)regs->xss);
Graeme Russc39acb42010-04-24 00:05:38 +1000127
128 cr0 = read_cr0();
129 cr2 = read_cr2();
130 cr3 = read_cr3();
131 cr4 = read_cr4();
132
133 printf("CR0: %08lx CR2: %08lx CR3: %08lx CR4: %08lx\n",
134 cr0, cr2, cr3, cr4);
135
136 d0 = get_debugreg(0);
137 d1 = get_debugreg(1);
138 d2 = get_debugreg(2);
139 d3 = get_debugreg(3);
140
141 printf("DR0: %08lx DR1: %08lx DR2: %08lx DR3: %08lx\n",
142 d0, d1, d2, d3);
143
144 d6 = get_debugreg(6);
145 d7 = get_debugreg(7);
146 printf("DR6: %08lx DR7: %08lx\n",
147 d6, d7);
Graeme Russ68699802011-02-12 15:11:28 +1100148
149 printf("Stack:\n");
150 sp = regs->esp;
151
152 sp += 64;
153
154 while (sp > (regs->esp - 16)) {
155 if (sp == regs->esp)
156 printf("--->");
157 else
158 printf(" ");
159 printf("0x%8.8lx : 0x%8.8lx\n", sp, (ulong)readl(sp));
160 sp -= 4;
161 }
Heinrich Schuchardt954108d2019-08-25 19:55:12 +0200162 show_efi_loaded_images(eip);
Graeme Russc39acb42010-04-24 00:05:38 +1000163}
164
Bin Mengfdebed82015-07-10 10:51:23 +0800165static void do_exception(struct irq_regs *regs)
166{
167 printf("%s\n", exceptions[regs->irq_id]);
168 dump_regs(regs);
169 hang();
170}
171
wdenk591dda52002-11-18 00:14:45 +0000172struct idt_entry {
173 u16 base_low;
174 u16 selector;
175 u8 res;
176 u8 access;
177 u16 base_high;
Graeme Russfdee8b12011-11-08 02:33:13 +0000178} __packed;
wdenk591dda52002-11-18 00:14:45 +0000179
Graeme Russd11b0852009-11-24 20:04:18 +1100180struct desc_ptr {
181 unsigned short size;
182 unsigned long address;
Graeme Russfdee8b12011-11-08 02:33:13 +0000183} __packed;
wdenk591dda52002-11-18 00:14:45 +0000184
Graeme Russaf3f2c82011-12-19 14:26:18 +1100185struct idt_entry idt[256] __aligned(16);
wdenk591dda52002-11-18 00:14:45 +0000186
Graeme Russd11b0852009-11-24 20:04:18 +1100187struct desc_ptr idt_ptr;
wdenk591dda52002-11-18 00:14:45 +0000188
Graeme Russd11b0852009-11-24 20:04:18 +1100189static inline void load_idt(const struct desc_ptr *dtr)
190{
Graeme Russfdee8b12011-11-08 02:33:13 +0000191 asm volatile("cs lidt %0" : : "m" (*dtr));
Graeme Russd11b0852009-11-24 20:04:18 +1100192}
wdenk591dda52002-11-18 00:14:45 +0000193
Graeme Russ77290ee2009-02-24 21:13:40 +1100194void set_vector(u8 intnum, void *routine)
wdenk591dda52002-11-18 00:14:45 +0000195{
Simon Glassb58770f2016-09-25 21:33:25 -0600196 idt[intnum].base_high = (u16)((ulong)(routine) >> 16);
197 idt[intnum].base_low = (u16)((ulong)(routine) & 0xffff);
wdenk591dda52002-11-18 00:14:45 +0000198}
199
Graeme Russfdee8b12011-11-08 02:33:13 +0000200/*
201 * Ideally these would be defined static to avoid a checkpatch warning, but
202 * the compiler cannot see them in the inline asm and complains that they
203 * aren't defined
204 */
Graeme Russd11b0852009-11-24 20:04:18 +1100205void irq_0(void);
206void irq_1(void);
wdenk591dda52002-11-18 00:14:45 +0000207
Graeme Russ77290ee2009-02-24 21:13:40 +1100208int cpu_init_interrupts(void)
wdenk591dda52002-11-18 00:14:45 +0000209{
210 int i;
wdenk57b2d802003-06-27 21:31:46 +0000211
Graeme Russd11b0852009-11-24 20:04:18 +1100212 int irq_entry_size = irq_1 - irq_0;
213 void *irq_entry = (void *)irq_0;
214
wdenk591dda52002-11-18 00:14:45 +0000215 /* Setup the IDT */
Graeme Russfdee8b12011-11-08 02:33:13 +0000216 for (i = 0; i < 256; i++) {
wdenk591dda52002-11-18 00:14:45 +0000217 idt[i].access = 0x8e;
wdenk57b2d802003-06-27 21:31:46 +0000218 idt[i].res = 0;
Simon Glassc4b9ef82015-07-31 09:31:32 -0600219 idt[i].selector = X86_GDT_ENTRY_32BIT_CS * X86_GDT_ENTRY_SIZE;
Graeme Russd11b0852009-11-24 20:04:18 +1100220 set_vector(i, irq_entry);
221 irq_entry += irq_entry_size;
wdenk57b2d802003-06-27 21:31:46 +0000222 }
223
Simon Glassc4b9ef82015-07-31 09:31:32 -0600224 idt_ptr.size = 256 * 8 - 1;
Graeme Russd11b0852009-11-24 20:04:18 +1100225 idt_ptr.address = (unsigned long) idt;
Graeme Russd11b0852009-11-24 20:04:18 +1100226
227 load_idt(&idt_ptr);
wdenk57b2d802003-06-27 21:31:46 +0000228
wdenk591dda52002-11-18 00:14:45 +0000229 return 0;
230}
231
Simon Glass98d7e982015-04-28 20:25:16 -0600232void *x86_get_idt(void)
233{
234 return &idt_ptr;
235}
236
Graeme Russd11b0852009-11-24 20:04:18 +1100237void __do_irq(int irq)
238{
239 printf("Unhandled IRQ : %d\n", irq);
240}
241void do_irq(int irq) __attribute__((weak, alias("__do_irq")));
242
wdenk591dda52002-11-18 00:14:45 +0000243void enable_interrupts(void)
244{
245 asm("sti\n");
246}
247
248int disable_interrupts(void)
249{
250 long flags;
wdenk57b2d802003-06-27 21:31:46 +0000251
Simon Glass1560a632017-01-16 07:04:00 -0700252#if CONFIG_IS_ENABLED(X86_64)
Simon Glass87086d52016-09-25 21:33:23 -0600253 asm volatile ("pushfq ; popq %0 ; cli\n" : "=g" (flags) : );
254#else
wdenk591dda52002-11-18 00:14:45 +0000255 asm volatile ("pushfl ; popl %0 ; cli\n" : "=g" (flags) : );
Simon Glass87086d52016-09-25 21:33:23 -0600256#endif
Graeme Russfdee8b12011-11-08 02:33:13 +0000257 return flags & X86_EFLAGS_IF;
wdenk591dda52002-11-18 00:14:45 +0000258}
Graeme Russd11b0852009-11-24 20:04:18 +1100259
Bin Mengcb9d9cb2014-11-20 16:11:16 +0800260int interrupt_init(void)
261{
Simon Glass754f55e2016-01-19 21:32:26 -0700262 struct udevice *dev;
263 int ret;
264
265 /* Try to set up the interrupt router, but don't require one */
Simon Glassc7298e72016-02-11 13:23:26 -0700266 ret = uclass_first_device_err(UCLASS_IRQ, &dev);
Simon Glass754f55e2016-01-19 21:32:26 -0700267 if (ret && ret != -ENODEV)
268 return ret;
269
Ben Stoltzab76a472015-08-04 12:33:46 -0600270 /*
271 * When running as an EFI application we are not in control of
272 * interrupts and should leave them alone.
273 */
274#ifndef CONFIG_EFI_APP
Bin Mengcb9d9cb2014-11-20 16:11:16 +0800275 /* Just in case... */
276 disable_interrupts();
277
Bin Mengb29a08c2015-10-22 19:13:30 -0700278#ifdef CONFIG_I8259_PIC
Bin Mengcb9d9cb2014-11-20 16:11:16 +0800279 /* Initialize the master/slave i8259 pic */
280 i8259_init();
281#endif
282
Hannes Schmelzerd18df3c2018-11-18 23:19:43 +0100283#ifdef CONFIG_APIC
Bin Mengd538c362016-05-22 01:45:33 -0700284 lapic_setup();
Hannes Schmelzerd18df3c2018-11-18 23:19:43 +0100285#endif
Bin Mengd538c362016-05-22 01:45:33 -0700286
Bin Mengcb9d9cb2014-11-20 16:11:16 +0800287 /* Initialize core interrupt and exception functionality of CPU */
288 cpu_init_interrupts();
289
Simon Glass2b6d80b2015-08-04 12:34:00 -0600290 /*
291 * It is now safe to enable interrupts.
292 *
293 * TODO(sjg@chromium.org): But we don't handle these correctly when
294 * booted from EFI.
295 */
296 if (ll_boot_init())
297 enable_interrupts();
Ben Stoltzab76a472015-08-04 12:33:46 -0600298#endif
Bin Mengcb9d9cb2014-11-20 16:11:16 +0800299
300 return 0;
301}
302
Graeme Russd11b0852009-11-24 20:04:18 +1100303/* IRQ Low-Level Service Routine */
Graeme Russ43261532010-10-07 20:03:23 +1100304void irq_llsr(struct irq_regs *regs)
Graeme Russd11b0852009-11-24 20:04:18 +1100305{
306 /*
307 * For detailed description of each exception, refer to:
Albert ARIBAUD60fbc8d2011-08-04 18:45:45 +0200308 * Intel® 64 and IA-32 Architectures Software Developer's Manual
Graeme Russd11b0852009-11-24 20:04:18 +1100309 * Volume 1: Basic Architecture
310 * Order Number: 253665-029US, November 2008
311 * Table 6-1. Exceptions and Interrupts
312 */
Bin Mengfdebed82015-07-10 10:51:23 +0800313 if (regs->irq_id < 32) {
314 /* Architecture defined exception */
315 do_exception(regs);
316 } else {
Graeme Russd11b0852009-11-24 20:04:18 +1100317 /* Hardware or User IRQ */
Graeme Russ43261532010-10-07 20:03:23 +1100318 do_irq(regs->irq_id);
Graeme Russd11b0852009-11-24 20:04:18 +1100319 }
320}
321
322/*
323 * OK - This looks really horrible, but it serves a purpose - It helps create
324 * fully relocatable code.
325 * - The call to irq_llsr will be a relative jump
326 * - The IRQ entries will be guaranteed to be in order
Graeme Russc39acb42010-04-24 00:05:38 +1000327 * Interrupt entries are now very small (a push and a jump) but they are
328 * now slower (all registers pushed on stack which provides complete
329 * crash dumps in the low level handlers
Graeme Russ43261532010-10-07 20:03:23 +1100330 *
331 * Interrupt Entry Point:
332 * - Interrupt has caused eflags, CS and EIP to be pushed
333 * - Interrupt Vector Handler has pushed orig_eax
334 * - pt_regs.esp needs to be adjusted by 40 bytes:
335 * 12 bytes pushed by CPU (EFLAGSF, CS, EIP)
336 * 4 bytes pushed by vector handler (irq_id)
337 * 24 bytes pushed before SP (SS, GS, FS, ES, DS, EAX)
338 * NOTE: Only longs are pushed on/popped off the stack!
Graeme Russd11b0852009-11-24 20:04:18 +1100339 */
340asm(".globl irq_common_entry\n" \
Graeme Russ1aafcc92009-11-24 20:04:19 +1100341 ".hidden irq_common_entry\n" \
342 ".type irq_common_entry, @function\n" \
Graeme Russd11b0852009-11-24 20:04:18 +1100343 "irq_common_entry:\n" \
Graeme Russc39acb42010-04-24 00:05:38 +1000344 "cld\n" \
Graeme Russ43261532010-10-07 20:03:23 +1100345 "pushl %ss\n" \
Graeme Russc39acb42010-04-24 00:05:38 +1000346 "pushl %gs\n" \
347 "pushl %fs\n" \
348 "pushl %es\n" \
349 "pushl %ds\n" \
350 "pushl %eax\n" \
Graeme Russ43261532010-10-07 20:03:23 +1100351 "movl %esp, %eax\n" \
352 "addl $40, %eax\n" \
353 "pushl %eax\n" \
Graeme Russc39acb42010-04-24 00:05:38 +1000354 "pushl %ebp\n" \
355 "pushl %edi\n" \
356 "pushl %esi\n" \
357 "pushl %edx\n" \
358 "pushl %ecx\n" \
359 "pushl %ebx\n" \
360 "mov %esp, %eax\n" \
Graeme Russd11b0852009-11-24 20:04:18 +1100361 "call irq_llsr\n" \
Graeme Russc39acb42010-04-24 00:05:38 +1000362 "popl %ebx\n" \
363 "popl %ecx\n" \
364 "popl %edx\n" \
365 "popl %esi\n" \
366 "popl %edi\n" \
367 "popl %ebp\n" \
368 "popl %eax\n" \
Graeme Russ43261532010-10-07 20:03:23 +1100369 "popl %eax\n" \
Graeme Russc39acb42010-04-24 00:05:38 +1000370 "popl %ds\n" \
371 "popl %es\n" \
372 "popl %fs\n" \
373 "popl %gs\n" \
Graeme Russ43261532010-10-07 20:03:23 +1100374 "popl %ss\n" \
Graeme Russc39acb42010-04-24 00:05:38 +1000375 "add $4, %esp\n" \
Graeme Russd11b0852009-11-24 20:04:18 +1100376 "iret\n" \
377 DECLARE_INTERRUPT(0) \
378 DECLARE_INTERRUPT(1) \
379 DECLARE_INTERRUPT(2) \
380 DECLARE_INTERRUPT(3) \
381 DECLARE_INTERRUPT(4) \
382 DECLARE_INTERRUPT(5) \
383 DECLARE_INTERRUPT(6) \
384 DECLARE_INTERRUPT(7) \
385 DECLARE_INTERRUPT(8) \
386 DECLARE_INTERRUPT(9) \
387 DECLARE_INTERRUPT(10) \
388 DECLARE_INTERRUPT(11) \
389 DECLARE_INTERRUPT(12) \
390 DECLARE_INTERRUPT(13) \
391 DECLARE_INTERRUPT(14) \
392 DECLARE_INTERRUPT(15) \
393 DECLARE_INTERRUPT(16) \
394 DECLARE_INTERRUPT(17) \
395 DECLARE_INTERRUPT(18) \
396 DECLARE_INTERRUPT(19) \
397 DECLARE_INTERRUPT(20) \
398 DECLARE_INTERRUPT(21) \
399 DECLARE_INTERRUPT(22) \
400 DECLARE_INTERRUPT(23) \
401 DECLARE_INTERRUPT(24) \
402 DECLARE_INTERRUPT(25) \
403 DECLARE_INTERRUPT(26) \
404 DECLARE_INTERRUPT(27) \
405 DECLARE_INTERRUPT(28) \
406 DECLARE_INTERRUPT(29) \
407 DECLARE_INTERRUPT(30) \
408 DECLARE_INTERRUPT(31) \
409 DECLARE_INTERRUPT(32) \
410 DECLARE_INTERRUPT(33) \
411 DECLARE_INTERRUPT(34) \
412 DECLARE_INTERRUPT(35) \
413 DECLARE_INTERRUPT(36) \
414 DECLARE_INTERRUPT(37) \
415 DECLARE_INTERRUPT(38) \
416 DECLARE_INTERRUPT(39) \
417 DECLARE_INTERRUPT(40) \
418 DECLARE_INTERRUPT(41) \
419 DECLARE_INTERRUPT(42) \
420 DECLARE_INTERRUPT(43) \
421 DECLARE_INTERRUPT(44) \
422 DECLARE_INTERRUPT(45) \
423 DECLARE_INTERRUPT(46) \
424 DECLARE_INTERRUPT(47) \
425 DECLARE_INTERRUPT(48) \
426 DECLARE_INTERRUPT(49) \
427 DECLARE_INTERRUPT(50) \
428 DECLARE_INTERRUPT(51) \
429 DECLARE_INTERRUPT(52) \
430 DECLARE_INTERRUPT(53) \
431 DECLARE_INTERRUPT(54) \
432 DECLARE_INTERRUPT(55) \
433 DECLARE_INTERRUPT(56) \
434 DECLARE_INTERRUPT(57) \
435 DECLARE_INTERRUPT(58) \
436 DECLARE_INTERRUPT(59) \
437 DECLARE_INTERRUPT(60) \
438 DECLARE_INTERRUPT(61) \
439 DECLARE_INTERRUPT(62) \
440 DECLARE_INTERRUPT(63) \
441 DECLARE_INTERRUPT(64) \
442 DECLARE_INTERRUPT(65) \
443 DECLARE_INTERRUPT(66) \
444 DECLARE_INTERRUPT(67) \
445 DECLARE_INTERRUPT(68) \
446 DECLARE_INTERRUPT(69) \
447 DECLARE_INTERRUPT(70) \
448 DECLARE_INTERRUPT(71) \
449 DECLARE_INTERRUPT(72) \
450 DECLARE_INTERRUPT(73) \
451 DECLARE_INTERRUPT(74) \
452 DECLARE_INTERRUPT(75) \
453 DECLARE_INTERRUPT(76) \
454 DECLARE_INTERRUPT(77) \
455 DECLARE_INTERRUPT(78) \
456 DECLARE_INTERRUPT(79) \
457 DECLARE_INTERRUPT(80) \
458 DECLARE_INTERRUPT(81) \
459 DECLARE_INTERRUPT(82) \
460 DECLARE_INTERRUPT(83) \
461 DECLARE_INTERRUPT(84) \
462 DECLARE_INTERRUPT(85) \
463 DECLARE_INTERRUPT(86) \
464 DECLARE_INTERRUPT(87) \
465 DECLARE_INTERRUPT(88) \
466 DECLARE_INTERRUPT(89) \
467 DECLARE_INTERRUPT(90) \
468 DECLARE_INTERRUPT(91) \
469 DECLARE_INTERRUPT(92) \
470 DECLARE_INTERRUPT(93) \
471 DECLARE_INTERRUPT(94) \
472 DECLARE_INTERRUPT(95) \
473 DECLARE_INTERRUPT(97) \
474 DECLARE_INTERRUPT(96) \
475 DECLARE_INTERRUPT(98) \
476 DECLARE_INTERRUPT(99) \
477 DECLARE_INTERRUPT(100) \
478 DECLARE_INTERRUPT(101) \
479 DECLARE_INTERRUPT(102) \
480 DECLARE_INTERRUPT(103) \
481 DECLARE_INTERRUPT(104) \
482 DECLARE_INTERRUPT(105) \
483 DECLARE_INTERRUPT(106) \
484 DECLARE_INTERRUPT(107) \
485 DECLARE_INTERRUPT(108) \
486 DECLARE_INTERRUPT(109) \
487 DECLARE_INTERRUPT(110) \
488 DECLARE_INTERRUPT(111) \
489 DECLARE_INTERRUPT(112) \
490 DECLARE_INTERRUPT(113) \
491 DECLARE_INTERRUPT(114) \
492 DECLARE_INTERRUPT(115) \
493 DECLARE_INTERRUPT(116) \
494 DECLARE_INTERRUPT(117) \
495 DECLARE_INTERRUPT(118) \
496 DECLARE_INTERRUPT(119) \
497 DECLARE_INTERRUPT(120) \
498 DECLARE_INTERRUPT(121) \
499 DECLARE_INTERRUPT(122) \
500 DECLARE_INTERRUPT(123) \
501 DECLARE_INTERRUPT(124) \
502 DECLARE_INTERRUPT(125) \
503 DECLARE_INTERRUPT(126) \
504 DECLARE_INTERRUPT(127) \
505 DECLARE_INTERRUPT(128) \
506 DECLARE_INTERRUPT(129) \
507 DECLARE_INTERRUPT(130) \
508 DECLARE_INTERRUPT(131) \
509 DECLARE_INTERRUPT(132) \
510 DECLARE_INTERRUPT(133) \
511 DECLARE_INTERRUPT(134) \
512 DECLARE_INTERRUPT(135) \
513 DECLARE_INTERRUPT(136) \
514 DECLARE_INTERRUPT(137) \
515 DECLARE_INTERRUPT(138) \
516 DECLARE_INTERRUPT(139) \
517 DECLARE_INTERRUPT(140) \
518 DECLARE_INTERRUPT(141) \
519 DECLARE_INTERRUPT(142) \
520 DECLARE_INTERRUPT(143) \
521 DECLARE_INTERRUPT(144) \
522 DECLARE_INTERRUPT(145) \
523 DECLARE_INTERRUPT(146) \
524 DECLARE_INTERRUPT(147) \
525 DECLARE_INTERRUPT(148) \
526 DECLARE_INTERRUPT(149) \
527 DECLARE_INTERRUPT(150) \
528 DECLARE_INTERRUPT(151) \
529 DECLARE_INTERRUPT(152) \
530 DECLARE_INTERRUPT(153) \
531 DECLARE_INTERRUPT(154) \
532 DECLARE_INTERRUPT(155) \
533 DECLARE_INTERRUPT(156) \
534 DECLARE_INTERRUPT(157) \
535 DECLARE_INTERRUPT(158) \
536 DECLARE_INTERRUPT(159) \
537 DECLARE_INTERRUPT(160) \
538 DECLARE_INTERRUPT(161) \
539 DECLARE_INTERRUPT(162) \
540 DECLARE_INTERRUPT(163) \
541 DECLARE_INTERRUPT(164) \
542 DECLARE_INTERRUPT(165) \
543 DECLARE_INTERRUPT(166) \
544 DECLARE_INTERRUPT(167) \
545 DECLARE_INTERRUPT(168) \
546 DECLARE_INTERRUPT(169) \
547 DECLARE_INTERRUPT(170) \
548 DECLARE_INTERRUPT(171) \
549 DECLARE_INTERRUPT(172) \
550 DECLARE_INTERRUPT(173) \
551 DECLARE_INTERRUPT(174) \
552 DECLARE_INTERRUPT(175) \
553 DECLARE_INTERRUPT(176) \
554 DECLARE_INTERRUPT(177) \
555 DECLARE_INTERRUPT(178) \
556 DECLARE_INTERRUPT(179) \
557 DECLARE_INTERRUPT(180) \
558 DECLARE_INTERRUPT(181) \
559 DECLARE_INTERRUPT(182) \
560 DECLARE_INTERRUPT(183) \
561 DECLARE_INTERRUPT(184) \
562 DECLARE_INTERRUPT(185) \
563 DECLARE_INTERRUPT(186) \
564 DECLARE_INTERRUPT(187) \
565 DECLARE_INTERRUPT(188) \
566 DECLARE_INTERRUPT(189) \
567 DECLARE_INTERRUPT(190) \
568 DECLARE_INTERRUPT(191) \
569 DECLARE_INTERRUPT(192) \
570 DECLARE_INTERRUPT(193) \
571 DECLARE_INTERRUPT(194) \
572 DECLARE_INTERRUPT(195) \
573 DECLARE_INTERRUPT(196) \
574 DECLARE_INTERRUPT(197) \
575 DECLARE_INTERRUPT(198) \
576 DECLARE_INTERRUPT(199) \
577 DECLARE_INTERRUPT(200) \
578 DECLARE_INTERRUPT(201) \
579 DECLARE_INTERRUPT(202) \
580 DECLARE_INTERRUPT(203) \
581 DECLARE_INTERRUPT(204) \
582 DECLARE_INTERRUPT(205) \
583 DECLARE_INTERRUPT(206) \
584 DECLARE_INTERRUPT(207) \
585 DECLARE_INTERRUPT(208) \
586 DECLARE_INTERRUPT(209) \
587 DECLARE_INTERRUPT(210) \
588 DECLARE_INTERRUPT(211) \
589 DECLARE_INTERRUPT(212) \
590 DECLARE_INTERRUPT(213) \
591 DECLARE_INTERRUPT(214) \
592 DECLARE_INTERRUPT(215) \
593 DECLARE_INTERRUPT(216) \
594 DECLARE_INTERRUPT(217) \
595 DECLARE_INTERRUPT(218) \
596 DECLARE_INTERRUPT(219) \
597 DECLARE_INTERRUPT(220) \
598 DECLARE_INTERRUPT(221) \
599 DECLARE_INTERRUPT(222) \
600 DECLARE_INTERRUPT(223) \
601 DECLARE_INTERRUPT(224) \
602 DECLARE_INTERRUPT(225) \
603 DECLARE_INTERRUPT(226) \
604 DECLARE_INTERRUPT(227) \
605 DECLARE_INTERRUPT(228) \
606 DECLARE_INTERRUPT(229) \
607 DECLARE_INTERRUPT(230) \
608 DECLARE_INTERRUPT(231) \
609 DECLARE_INTERRUPT(232) \
610 DECLARE_INTERRUPT(233) \
611 DECLARE_INTERRUPT(234) \
612 DECLARE_INTERRUPT(235) \
613 DECLARE_INTERRUPT(236) \
614 DECLARE_INTERRUPT(237) \
615 DECLARE_INTERRUPT(238) \
616 DECLARE_INTERRUPT(239) \
617 DECLARE_INTERRUPT(240) \
618 DECLARE_INTERRUPT(241) \
619 DECLARE_INTERRUPT(242) \
620 DECLARE_INTERRUPT(243) \
621 DECLARE_INTERRUPT(244) \
622 DECLARE_INTERRUPT(245) \
623 DECLARE_INTERRUPT(246) \
624 DECLARE_INTERRUPT(247) \
625 DECLARE_INTERRUPT(248) \
626 DECLARE_INTERRUPT(249) \
627 DECLARE_INTERRUPT(250) \
628 DECLARE_INTERRUPT(251) \
629 DECLARE_INTERRUPT(252) \
630 DECLARE_INTERRUPT(253) \
631 DECLARE_INTERRUPT(254) \
632 DECLARE_INTERRUPT(255));