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git01.mediatek.com / filogic / uboot / fdebed82ade393eff958993e9b4293cb3243caec / . / arch / x86 / cpu / interrupts.c
blob: 853c82f5a7709105b822309abc2edcd44f6e7635 [file] [log] [blame]
wdenk591dda52002-11-18 00:14:45 +0000[diff] [blame]1/*
Graeme Russ45fc1d82011-04-13 19:43:26 +1000[diff] [blame]2 * (C) Copyright 2008-2011
3 * Graeme Russ, <graeme.russ@gmail.com>
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]4 *
wdenk591dda52002-11-18 00:14:45 +0000[diff] [blame]5 * (C) Copyright 2002
Albert ARIBAUD60fbc8d2011-08-04 18:45:45 +0200[diff] [blame]6 * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
wdenk591dda52002-11-18 00:14:45 +0000[diff] [blame]7 *
Graeme Russc39acb42010-04-24 00:05:38 +1000[diff] [blame]8 * Portions of this file are derived from the Linux kernel source
9 * Copyright (C) 1991, 1992 Linus Torvalds
10 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]11 * SPDX-License-Identifier: GPL-2.0+
wdenk591dda52002-11-18 00:14:45 +0000[diff] [blame]12 */
13
14#include <common.h>
Stefan Reinauer2acf8482012-12-02 04:49:50 +0000[diff] [blame]15#include <asm/cache.h>
16#include <asm/control_regs.h>
Graeme Russ0c8c62e2008-12-07 10:29:01 +1100[diff] [blame]17#include <asm/interrupt.h>
Graeme Russ68699802011-02-12 15:11:28 +1100[diff] [blame]18#include <asm/io.h>
Graeme Russ93efcb22011-02-12 15:11:32 +1100[diff] [blame]19#include <asm/processor-flags.h>
Graeme Russfdee8b12011-11-08 02:33:13 +0000[diff] [blame]20#include <linux/compiler.h>
Vadim Bendebury6ab02582012-12-03 13:59:20 +0000[diff] [blame]21#include <asm/msr.h>
22#include <asm/u-boot-x86.h>
Bin Mengcb9d9cb2014-11-20 16:11:16 +0800[diff] [blame]23#include <asm/i8259.h>
wdenk591dda52002-11-18 00:14:45 +0000[diff] [blame]24
Simon Glassbb6306c2013-04-17 16:13:33 +0000[diff] [blame]25DECLARE_GLOBAL_DATA_PTR;
26
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]27#define DECLARE_INTERRUPT(x) \
28 ".globl irq_"#x"\n" \
Graeme Russ1aafcc92009-11-24 20:04:19 +1100[diff] [blame]29 ".hidden irq_"#x"\n" \
30 ".type irq_"#x", @function\n" \
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]31 "irq_"#x":\n" \
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]32 "pushl $"#x"\n" \
33 "jmp irq_common_entry\n"
wdenk591dda52002-11-18 00:14:45 +0000[diff] [blame]34
Bin Mengfdebed82015-07-10 10:51:23 +0800[diff] [blame^]35static char *exceptions[] = {
36 "Divide Error",
37 "Debug",
38 "NMI Interrupt",
39 "Breakpoint",
40 "Overflow",
41 "BOUND Range Exceeded",
42 "Invalid Opcode (Undefined Opcode)",
43 "Device Not Avaiable (No Math Coprocessor)",
44 "Double Fault",
45 "Coprocessor Segment Overrun",
46 "Invalid TSS",
47 "Segment Not Present",
48 "Stack Segment Fault",
49 "Gerneral Protection",
50 "Page Fault",
51 "Reserved",
52 "x87 FPU Floating-Point Error",
53 "Alignment Check",
54 "Machine Check",
55 "SIMD Floating-Point Exception",
56 "Virtualization Exception",
57 "Reserved",
58 "Reserved",
59 "Reserved",
60 "Reserved",
61 "Reserved",
62 "Reserved",
63 "Reserved",
64 "Reserved",
65 "Reserved",
66 "Reserved",
67 "Reserved"
68};
69
Simon Glass83374332014-11-06 13:20:08 -0700[diff] [blame]70static void dump_regs(struct irq_regs *regs)
Graeme Russc39acb42010-04-24 00:05:38 +1000[diff] [blame]71{
Bin Meng9ff054b2015-07-10 10:38:32 +0800[diff] [blame]72 unsigned long cs, eip, eflags;
Graeme Russc39acb42010-04-24 00:05:38 +1000[diff] [blame]73 unsigned long cr0 = 0L, cr2 = 0L, cr3 = 0L, cr4 = 0L;
74 unsigned long d0, d1, d2, d3, d6, d7;
Graeme Russ68699802011-02-12 15:11:28 +1100[diff] [blame]75 unsigned long sp;
Graeme Russc39acb42010-04-24 00:05:38 +1000[diff] [blame]76
Bin Meng9ff054b2015-07-10 10:38:32 +0800[diff] [blame]77 /*
78 * Some exceptions cause an error code to be saved on the current stack
79 * after the EIP value. We should extract CS/EIP/EFLAGS from different
80 * position on the stack based on the exception number.
81 */
82 switch (regs->irq_id) {
83 case EXC_DF:
84 case EXC_TS:
85 case EXC_NP:
86 case EXC_SS:
87 case EXC_GP:
88 case EXC_PF:
89 case EXC_AC:
90 cs = regs->context.ctx2.xcs;
91 eip = regs->context.ctx2.eip;
92 eflags = regs->context.ctx2.eflags;
93 /* We should fix up the ESP due to error code */
94 regs->esp += 4;
95 break;
96 default:
97 cs = regs->context.ctx1.xcs;
98 eip = regs->context.ctx1.eip;
99 eflags = regs->context.ctx1.eflags;
100 break;
101 }
102
Graeme Russc39acb42010-04-24 00:05:38 +1000[diff] [blame]103 printf("EIP: %04x:[<%08lx>] EFLAGS: %08lx\n",
Bin Meng9ff054b2015-07-10 10:38:32 +0800[diff] [blame]104 (u16)cs, eip, eflags);
Graeme Russc39acb42010-04-24 00:05:38 +1000[diff] [blame]105
106 printf("EAX: %08lx EBX: %08lx ECX: %08lx EDX: %08lx\n",
107 regs->eax, regs->ebx, regs->ecx, regs->edx);
108 printf("ESI: %08lx EDI: %08lx EBP: %08lx ESP: %08lx\n",
109 regs->esi, regs->edi, regs->ebp, regs->esp);
110 printf(" DS: %04x ES: %04x FS: %04x GS: %04x SS: %04x\n",
Graeme Russfdee8b12011-11-08 02:33:13 +0000[diff] [blame]111 (u16)regs->xds, (u16)regs->xes, (u16)regs->xfs,
112 (u16)regs->xgs, (u16)regs->xss);
Graeme Russc39acb42010-04-24 00:05:38 +1000[diff] [blame]113
114 cr0 = read_cr0();
115 cr2 = read_cr2();
116 cr3 = read_cr3();
117 cr4 = read_cr4();
118
119 printf("CR0: %08lx CR2: %08lx CR3: %08lx CR4: %08lx\n",
120 cr0, cr2, cr3, cr4);
121
122 d0 = get_debugreg(0);
123 d1 = get_debugreg(1);
124 d2 = get_debugreg(2);
125 d3 = get_debugreg(3);
126
127 printf("DR0: %08lx DR1: %08lx DR2: %08lx DR3: %08lx\n",
128 d0, d1, d2, d3);
129
130 d6 = get_debugreg(6);
131 d7 = get_debugreg(7);
132 printf("DR6: %08lx DR7: %08lx\n",
133 d6, d7);
Graeme Russ68699802011-02-12 15:11:28 +1100[diff] [blame]134
135 printf("Stack:\n");
136 sp = regs->esp;
137
138 sp += 64;
139
140 while (sp > (regs->esp - 16)) {
141 if (sp == regs->esp)
142 printf("--->");
143 else
144 printf(" ");
145 printf("0x%8.8lx : 0x%8.8lx\n", sp, (ulong)readl(sp));
146 sp -= 4;
147 }
Graeme Russc39acb42010-04-24 00:05:38 +1000[diff] [blame]148}
149
Bin Mengfdebed82015-07-10 10:51:23 +0800[diff] [blame^]150static void do_exception(struct irq_regs *regs)
151{
152 printf("%s\n", exceptions[regs->irq_id]);
153 dump_regs(regs);
154 hang();
155}
156
wdenk591dda52002-11-18 00:14:45 +0000[diff] [blame]157struct idt_entry {
158 u16 base_low;
159 u16 selector;
160 u8 res;
161 u8 access;
162 u16 base_high;
Graeme Russfdee8b12011-11-08 02:33:13 +0000[diff] [blame]163} __packed;
wdenk591dda52002-11-18 00:14:45 +0000[diff] [blame]164
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]165struct desc_ptr {
166 unsigned short size;
167 unsigned long address;
168 unsigned short segment;
Graeme Russfdee8b12011-11-08 02:33:13 +0000[diff] [blame]169} __packed;
wdenk591dda52002-11-18 00:14:45 +0000[diff] [blame]170
Graeme Russaf3f2c82011-12-19 14:26:18 +1100[diff] [blame]171struct idt_entry idt[256] __aligned(16);
wdenk591dda52002-11-18 00:14:45 +0000[diff] [blame]172
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]173struct desc_ptr idt_ptr;
wdenk591dda52002-11-18 00:14:45 +0000[diff] [blame]174
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]175static inline void load_idt(const struct desc_ptr *dtr)
176{
Graeme Russfdee8b12011-11-08 02:33:13 +0000[diff] [blame]177 asm volatile("cs lidt %0" : : "m" (*dtr));
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]178}
wdenk591dda52002-11-18 00:14:45 +0000[diff] [blame]179
Graeme Russ77290ee2009-02-24 21:13:40 +1100[diff] [blame]180void set_vector(u8 intnum, void *routine)
wdenk591dda52002-11-18 00:14:45 +0000[diff] [blame]181{
Graeme Russ078395c2009-11-24 20:04:21 +1100[diff] [blame]182 idt[intnum].base_high = (u16)((u32)(routine) >> 16);
183 idt[intnum].base_low = (u16)((u32)(routine) & 0xffff);
wdenk591dda52002-11-18 00:14:45 +0000[diff] [blame]184}
185
Graeme Russfdee8b12011-11-08 02:33:13 +0000[diff] [blame]186/*
187 * Ideally these would be defined static to avoid a checkpatch warning, but
188 * the compiler cannot see them in the inline asm and complains that they
189 * aren't defined
190 */
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]191void irq_0(void);
192void irq_1(void);
wdenk591dda52002-11-18 00:14:45 +0000[diff] [blame]193
Graeme Russ77290ee2009-02-24 21:13:40 +1100[diff] [blame]194int cpu_init_interrupts(void)
wdenk591dda52002-11-18 00:14:45 +0000[diff] [blame]195{
196 int i;
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]197
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]198 int irq_entry_size = irq_1 - irq_0;
199 void *irq_entry = (void *)irq_0;
200
wdenk591dda52002-11-18 00:14:45 +0000[diff] [blame]201 /* Setup the IDT */
Graeme Russfdee8b12011-11-08 02:33:13 +0000[diff] [blame]202 for (i = 0; i < 256; i++) {
wdenk591dda52002-11-18 00:14:45 +0000[diff] [blame]203 idt[i].access = 0x8e;
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]204 idt[i].res = 0;
205 idt[i].selector = 0x10;
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]206 set_vector(i, irq_entry);
207 irq_entry += irq_entry_size;
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]208 }
209
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]210 idt_ptr.size = 256 * 8;
211 idt_ptr.address = (unsigned long) idt;
212 idt_ptr.segment = 0x18;
213
214 load_idt(&idt_ptr);
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]215
wdenk591dda52002-11-18 00:14:45 +0000[diff] [blame]216 return 0;
217}
218
Simon Glass98d7e982015-04-28 20:25:16 -0600[diff] [blame]219void *x86_get_idt(void)
220{
221 return &idt_ptr;
222}
223
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]224void __do_irq(int irq)
225{
226 printf("Unhandled IRQ : %d\n", irq);
227}
228void do_irq(int irq) __attribute__((weak, alias("__do_irq")));
229
wdenk591dda52002-11-18 00:14:45 +0000[diff] [blame]230void enable_interrupts(void)
231{
232 asm("sti\n");
233}
234
235int disable_interrupts(void)
236{
237 long flags;
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]238
wdenk591dda52002-11-18 00:14:45 +0000[diff] [blame]239 asm volatile ("pushfl ; popl %0 ; cli\n" : "=g" (flags) : );
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]240
Graeme Russfdee8b12011-11-08 02:33:13 +0000[diff] [blame]241 return flags & X86_EFLAGS_IF;
wdenk591dda52002-11-18 00:14:45 +0000[diff] [blame]242}
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]243
Bin Mengcb9d9cb2014-11-20 16:11:16 +0800[diff] [blame]244int interrupt_init(void)
245{
246 /* Just in case... */
247 disable_interrupts();
248
249#ifdef CONFIG_SYS_PCAT_INTERRUPTS
250 /* Initialize the master/slave i8259 pic */
251 i8259_init();
252#endif
253
254 /* Initialize core interrupt and exception functionality of CPU */
255 cpu_init_interrupts();
256
257 /* It is now safe to enable interrupts */
258 enable_interrupts();
259
260 return 0;
261}
262
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]263/* IRQ Low-Level Service Routine */
Graeme Russ43261532010-10-07 20:03:23 +1100[diff] [blame]264void irq_llsr(struct irq_regs *regs)
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]265{
266 /*
267 * For detailed description of each exception, refer to:
Albert ARIBAUD60fbc8d2011-08-04 18:45:45 +0200[diff] [blame]268 * Intel® 64 and IA-32 Architectures Software Developer's Manual
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]269 * Volume 1: Basic Architecture
270 * Order Number: 253665-029US, November 2008
271 * Table 6-1. Exceptions and Interrupts
272 */
Bin Mengfdebed82015-07-10 10:51:23 +0800[diff] [blame^]273 if (regs->irq_id < 32) {
274 /* Architecture defined exception */
275 do_exception(regs);
276 } else {
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]277 /* Hardware or User IRQ */
Graeme Russ43261532010-10-07 20:03:23 +1100[diff] [blame]278 do_irq(regs->irq_id);
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]279 }
280}
281
282/*
283 * OK - This looks really horrible, but it serves a purpose - It helps create
284 * fully relocatable code.
285 * - The call to irq_llsr will be a relative jump
286 * - The IRQ entries will be guaranteed to be in order
Graeme Russc39acb42010-04-24 00:05:38 +1000[diff] [blame]287 * Interrupt entries are now very small (a push and a jump) but they are
288 * now slower (all registers pushed on stack which provides complete
289 * crash dumps in the low level handlers
Graeme Russ43261532010-10-07 20:03:23 +1100[diff] [blame]290 *
291 * Interrupt Entry Point:
292 * - Interrupt has caused eflags, CS and EIP to be pushed
293 * - Interrupt Vector Handler has pushed orig_eax
294 * - pt_regs.esp needs to be adjusted by 40 bytes:
295 * 12 bytes pushed by CPU (EFLAGSF, CS, EIP)
296 * 4 bytes pushed by vector handler (irq_id)
297 * 24 bytes pushed before SP (SS, GS, FS, ES, DS, EAX)
298 * NOTE: Only longs are pushed on/popped off the stack!
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]299 */
300asm(".globl irq_common_entry\n" \
Graeme Russ1aafcc92009-11-24 20:04:19 +1100[diff] [blame]301 ".hidden irq_common_entry\n" \
302 ".type irq_common_entry, @function\n" \
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]303 "irq_common_entry:\n" \
Graeme Russc39acb42010-04-24 00:05:38 +1000[diff] [blame]304 "cld\n" \
Graeme Russ43261532010-10-07 20:03:23 +1100[diff] [blame]305 "pushl %ss\n" \
Graeme Russc39acb42010-04-24 00:05:38 +1000[diff] [blame]306 "pushl %gs\n" \
307 "pushl %fs\n" \
308 "pushl %es\n" \
309 "pushl %ds\n" \
310 "pushl %eax\n" \
Graeme Russ43261532010-10-07 20:03:23 +1100[diff] [blame]311 "movl %esp, %eax\n" \
312 "addl $40, %eax\n" \
313 "pushl %eax\n" \
Graeme Russc39acb42010-04-24 00:05:38 +1000[diff] [blame]314 "pushl %ebp\n" \
315 "pushl %edi\n" \
316 "pushl %esi\n" \
317 "pushl %edx\n" \
318 "pushl %ecx\n" \
319 "pushl %ebx\n" \
320 "mov %esp, %eax\n" \
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]321 "call irq_llsr\n" \
Graeme Russc39acb42010-04-24 00:05:38 +1000[diff] [blame]322 "popl %ebx\n" \
323 "popl %ecx\n" \
324 "popl %edx\n" \
325 "popl %esi\n" \
326 "popl %edi\n" \
327 "popl %ebp\n" \
328 "popl %eax\n" \
Graeme Russ43261532010-10-07 20:03:23 +1100[diff] [blame]329 "popl %eax\n" \
Graeme Russc39acb42010-04-24 00:05:38 +1000[diff] [blame]330 "popl %ds\n" \
331 "popl %es\n" \
332 "popl %fs\n" \
333 "popl %gs\n" \
Graeme Russ43261532010-10-07 20:03:23 +1100[diff] [blame]334 "popl %ss\n" \
Graeme Russc39acb42010-04-24 00:05:38 +1000[diff] [blame]335 "add $4, %esp\n" \
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]336 "iret\n" \
337 DECLARE_INTERRUPT(0) \
338 DECLARE_INTERRUPT(1) \
339 DECLARE_INTERRUPT(2) \
340 DECLARE_INTERRUPT(3) \
341 DECLARE_INTERRUPT(4) \
342 DECLARE_INTERRUPT(5) \
343 DECLARE_INTERRUPT(6) \
344 DECLARE_INTERRUPT(7) \
345 DECLARE_INTERRUPT(8) \
346 DECLARE_INTERRUPT(9) \
347 DECLARE_INTERRUPT(10) \
348 DECLARE_INTERRUPT(11) \
349 DECLARE_INTERRUPT(12) \
350 DECLARE_INTERRUPT(13) \
351 DECLARE_INTERRUPT(14) \
352 DECLARE_INTERRUPT(15) \
353 DECLARE_INTERRUPT(16) \
354 DECLARE_INTERRUPT(17) \
355 DECLARE_INTERRUPT(18) \
356 DECLARE_INTERRUPT(19) \
357 DECLARE_INTERRUPT(20) \
358 DECLARE_INTERRUPT(21) \
359 DECLARE_INTERRUPT(22) \
360 DECLARE_INTERRUPT(23) \
361 DECLARE_INTERRUPT(24) \
362 DECLARE_INTERRUPT(25) \
363 DECLARE_INTERRUPT(26) \
364 DECLARE_INTERRUPT(27) \
365 DECLARE_INTERRUPT(28) \
366 DECLARE_INTERRUPT(29) \
367 DECLARE_INTERRUPT(30) \
368 DECLARE_INTERRUPT(31) \
369 DECLARE_INTERRUPT(32) \
370 DECLARE_INTERRUPT(33) \
371 DECLARE_INTERRUPT(34) \
372 DECLARE_INTERRUPT(35) \
373 DECLARE_INTERRUPT(36) \
374 DECLARE_INTERRUPT(37) \
375 DECLARE_INTERRUPT(38) \
376 DECLARE_INTERRUPT(39) \
377 DECLARE_INTERRUPT(40) \
378 DECLARE_INTERRUPT(41) \
379 DECLARE_INTERRUPT(42) \
380 DECLARE_INTERRUPT(43) \
381 DECLARE_INTERRUPT(44) \
382 DECLARE_INTERRUPT(45) \
383 DECLARE_INTERRUPT(46) \
384 DECLARE_INTERRUPT(47) \
385 DECLARE_INTERRUPT(48) \
386 DECLARE_INTERRUPT(49) \
387 DECLARE_INTERRUPT(50) \
388 DECLARE_INTERRUPT(51) \
389 DECLARE_INTERRUPT(52) \
390 DECLARE_INTERRUPT(53) \
391 DECLARE_INTERRUPT(54) \
392 DECLARE_INTERRUPT(55) \
393 DECLARE_INTERRUPT(56) \
394 DECLARE_INTERRUPT(57) \
395 DECLARE_INTERRUPT(58) \
396 DECLARE_INTERRUPT(59) \
397 DECLARE_INTERRUPT(60) \
398 DECLARE_INTERRUPT(61) \
399 DECLARE_INTERRUPT(62) \
400 DECLARE_INTERRUPT(63) \
401 DECLARE_INTERRUPT(64) \
402 DECLARE_INTERRUPT(65) \
403 DECLARE_INTERRUPT(66) \
404 DECLARE_INTERRUPT(67) \
405 DECLARE_INTERRUPT(68) \
406 DECLARE_INTERRUPT(69) \
407 DECLARE_INTERRUPT(70) \
408 DECLARE_INTERRUPT(71) \
409 DECLARE_INTERRUPT(72) \
410 DECLARE_INTERRUPT(73) \
411 DECLARE_INTERRUPT(74) \
412 DECLARE_INTERRUPT(75) \
413 DECLARE_INTERRUPT(76) \
414 DECLARE_INTERRUPT(77) \
415 DECLARE_INTERRUPT(78) \
416 DECLARE_INTERRUPT(79) \
417 DECLARE_INTERRUPT(80) \
418 DECLARE_INTERRUPT(81) \
419 DECLARE_INTERRUPT(82) \
420 DECLARE_INTERRUPT(83) \
421 DECLARE_INTERRUPT(84) \
422 DECLARE_INTERRUPT(85) \
423 DECLARE_INTERRUPT(86) \
424 DECLARE_INTERRUPT(87) \
425 DECLARE_INTERRUPT(88) \
426 DECLARE_INTERRUPT(89) \
427 DECLARE_INTERRUPT(90) \
428 DECLARE_INTERRUPT(91) \
429 DECLARE_INTERRUPT(92) \
430 DECLARE_INTERRUPT(93) \
431 DECLARE_INTERRUPT(94) \
432 DECLARE_INTERRUPT(95) \
433 DECLARE_INTERRUPT(97) \
434 DECLARE_INTERRUPT(96) \
435 DECLARE_INTERRUPT(98) \
436 DECLARE_INTERRUPT(99) \
437 DECLARE_INTERRUPT(100) \
438 DECLARE_INTERRUPT(101) \
439 DECLARE_INTERRUPT(102) \
440 DECLARE_INTERRUPT(103) \
441 DECLARE_INTERRUPT(104) \
442 DECLARE_INTERRUPT(105) \
443 DECLARE_INTERRUPT(106) \
444 DECLARE_INTERRUPT(107) \
445 DECLARE_INTERRUPT(108) \
446 DECLARE_INTERRUPT(109) \
447 DECLARE_INTERRUPT(110) \
448 DECLARE_INTERRUPT(111) \
449 DECLARE_INTERRUPT(112) \
450 DECLARE_INTERRUPT(113) \
451 DECLARE_INTERRUPT(114) \
452 DECLARE_INTERRUPT(115) \
453 DECLARE_INTERRUPT(116) \
454 DECLARE_INTERRUPT(117) \
455 DECLARE_INTERRUPT(118) \
456 DECLARE_INTERRUPT(119) \
457 DECLARE_INTERRUPT(120) \
458 DECLARE_INTERRUPT(121) \
459 DECLARE_INTERRUPT(122) \
460 DECLARE_INTERRUPT(123) \
461 DECLARE_INTERRUPT(124) \
462 DECLARE_INTERRUPT(125) \
463 DECLARE_INTERRUPT(126) \
464 DECLARE_INTERRUPT(127) \
465 DECLARE_INTERRUPT(128) \
466 DECLARE_INTERRUPT(129) \
467 DECLARE_INTERRUPT(130) \
468 DECLARE_INTERRUPT(131) \
469 DECLARE_INTERRUPT(132) \
470 DECLARE_INTERRUPT(133) \
471 DECLARE_INTERRUPT(134) \
472 DECLARE_INTERRUPT(135) \
473 DECLARE_INTERRUPT(136) \
474 DECLARE_INTERRUPT(137) \
475 DECLARE_INTERRUPT(138) \
476 DECLARE_INTERRUPT(139) \
477 DECLARE_INTERRUPT(140) \
478 DECLARE_INTERRUPT(141) \
479 DECLARE_INTERRUPT(142) \
480 DECLARE_INTERRUPT(143) \
481 DECLARE_INTERRUPT(144) \
482 DECLARE_INTERRUPT(145) \
483 DECLARE_INTERRUPT(146) \
484 DECLARE_INTERRUPT(147) \
485 DECLARE_INTERRUPT(148) \
486 DECLARE_INTERRUPT(149) \
487 DECLARE_INTERRUPT(150) \
488 DECLARE_INTERRUPT(151) \
489 DECLARE_INTERRUPT(152) \
490 DECLARE_INTERRUPT(153) \
491 DECLARE_INTERRUPT(154) \
492 DECLARE_INTERRUPT(155) \
493 DECLARE_INTERRUPT(156) \
494 DECLARE_INTERRUPT(157) \
495 DECLARE_INTERRUPT(158) \
496 DECLARE_INTERRUPT(159) \
497 DECLARE_INTERRUPT(160) \
498 DECLARE_INTERRUPT(161) \
499 DECLARE_INTERRUPT(162) \
500 DECLARE_INTERRUPT(163) \
501 DECLARE_INTERRUPT(164) \
502 DECLARE_INTERRUPT(165) \
503 DECLARE_INTERRUPT(166) \
504 DECLARE_INTERRUPT(167) \
505 DECLARE_INTERRUPT(168) \
506 DECLARE_INTERRUPT(169) \
507 DECLARE_INTERRUPT(170) \
508 DECLARE_INTERRUPT(171) \
509 DECLARE_INTERRUPT(172) \
510 DECLARE_INTERRUPT(173) \
511 DECLARE_INTERRUPT(174) \
512 DECLARE_INTERRUPT(175) \
513 DECLARE_INTERRUPT(176) \
514 DECLARE_INTERRUPT(177) \
515 DECLARE_INTERRUPT(178) \
516 DECLARE_INTERRUPT(179) \
517 DECLARE_INTERRUPT(180) \
518 DECLARE_INTERRUPT(181) \
519 DECLARE_INTERRUPT(182) \
520 DECLARE_INTERRUPT(183) \
521 DECLARE_INTERRUPT(184) \
522 DECLARE_INTERRUPT(185) \
523 DECLARE_INTERRUPT(186) \
524 DECLARE_INTERRUPT(187) \
525 DECLARE_INTERRUPT(188) \
526 DECLARE_INTERRUPT(189) \
527 DECLARE_INTERRUPT(190) \
528 DECLARE_INTERRUPT(191) \
529 DECLARE_INTERRUPT(192) \
530 DECLARE_INTERRUPT(193) \
531 DECLARE_INTERRUPT(194) \
532 DECLARE_INTERRUPT(195) \
533 DECLARE_INTERRUPT(196) \
534 DECLARE_INTERRUPT(197) \
535 DECLARE_INTERRUPT(198) \
536 DECLARE_INTERRUPT(199) \
537 DECLARE_INTERRUPT(200) \
538 DECLARE_INTERRUPT(201) \
539 DECLARE_INTERRUPT(202) \
540 DECLARE_INTERRUPT(203) \
541 DECLARE_INTERRUPT(204) \
542 DECLARE_INTERRUPT(205) \
543 DECLARE_INTERRUPT(206) \
544 DECLARE_INTERRUPT(207) \
545 DECLARE_INTERRUPT(208) \
546 DECLARE_INTERRUPT(209) \
547 DECLARE_INTERRUPT(210) \
548 DECLARE_INTERRUPT(211) \
549 DECLARE_INTERRUPT(212) \
550 DECLARE_INTERRUPT(213) \
551 DECLARE_INTERRUPT(214) \
552 DECLARE_INTERRUPT(215) \
553 DECLARE_INTERRUPT(216) \
554 DECLARE_INTERRUPT(217) \
555 DECLARE_INTERRUPT(218) \
556 DECLARE_INTERRUPT(219) \
557 DECLARE_INTERRUPT(220) \
558 DECLARE_INTERRUPT(221) \
559 DECLARE_INTERRUPT(222) \
560 DECLARE_INTERRUPT(223) \
561 DECLARE_INTERRUPT(224) \
562 DECLARE_INTERRUPT(225) \
563 DECLARE_INTERRUPT(226) \
564 DECLARE_INTERRUPT(227) \
565 DECLARE_INTERRUPT(228) \
566 DECLARE_INTERRUPT(229) \
567 DECLARE_INTERRUPT(230) \
568 DECLARE_INTERRUPT(231) \
569 DECLARE_INTERRUPT(232) \
570 DECLARE_INTERRUPT(233) \
571 DECLARE_INTERRUPT(234) \
572 DECLARE_INTERRUPT(235) \
573 DECLARE_INTERRUPT(236) \
574 DECLARE_INTERRUPT(237) \
575 DECLARE_INTERRUPT(238) \
576 DECLARE_INTERRUPT(239) \
577 DECLARE_INTERRUPT(240) \
578 DECLARE_INTERRUPT(241) \
579 DECLARE_INTERRUPT(242) \
580 DECLARE_INTERRUPT(243) \
581 DECLARE_INTERRUPT(244) \
582 DECLARE_INTERRUPT(245) \
583 DECLARE_INTERRUPT(246) \
584 DECLARE_INTERRUPT(247) \
585 DECLARE_INTERRUPT(248) \
586 DECLARE_INTERRUPT(249) \
587 DECLARE_INTERRUPT(250) \
588 DECLARE_INTERRUPT(251) \
589 DECLARE_INTERRUPT(252) \
590 DECLARE_INTERRUPT(253) \
591 DECLARE_INTERRUPT(254) \
592 DECLARE_INTERRUPT(255));