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git01.mediatek.com / filogic / uboot / 2acf84869b2aba691b108fac92f1c6a7abb4c421 / . / arch / x86 / cpu / interrupts.c
blob: e7887152f7b27f73559263092b5cc09b7fefbdf4 [file] [log] [blame]
wdenk591dda52002-11-18 00:14:45 +0000[diff] [blame]1/*
Graeme Russ45fc1d82011-04-13 19:43:26 +1000[diff] [blame]2 * (C) Copyright 2008-2011
3 * Graeme Russ, <graeme.russ@gmail.com>
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]4 *
wdenk591dda52002-11-18 00:14:45 +0000[diff] [blame]5 * (C) Copyright 2002
Albert ARIBAUD60fbc8d2011-08-04 18:45:45 +0200[diff] [blame]6 * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
wdenk591dda52002-11-18 00:14:45 +0000[diff] [blame]7 *
Graeme Russc39acb42010-04-24 00:05:38 +1000[diff] [blame]8 * Portions of this file are derived from the Linux kernel source
9 * Copyright (C) 1991, 1992 Linus Torvalds
10 *
wdenk591dda52002-11-18 00:14:45 +0000[diff] [blame]11 * See file CREDITS for list of people who contributed to this
12 * project.
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MA 02111-1307 USA
28 */
29
30#include <common.h>
Stefan Reinauer2acf8482012-12-02 04:49:50 +0000[diff] [blame^]31#include <asm/cache.h>
32#include <asm/control_regs.h>
Graeme Russ0c8c62e2008-12-07 10:29:01 +1100[diff] [blame]33#include <asm/interrupt.h>
Graeme Russ68699802011-02-12 15:11:28 +1100[diff] [blame]34#include <asm/io.h>
Graeme Russ93efcb22011-02-12 15:11:32 +1100[diff] [blame]35#include <asm/processor-flags.h>
Graeme Russfdee8b12011-11-08 02:33:13 +0000[diff] [blame]36#include <linux/compiler.h>
wdenk591dda52002-11-18 00:14:45 +0000[diff] [blame]37
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]38#define DECLARE_INTERRUPT(x) \
39 ".globl irq_"#x"\n" \
Graeme Russ1aafcc92009-11-24 20:04:19 +1100[diff] [blame]40 ".hidden irq_"#x"\n" \
41 ".type irq_"#x", @function\n" \
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]42 "irq_"#x":\n" \
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]43 "pushl $"#x"\n" \
44 "jmp irq_common_entry\n"
wdenk591dda52002-11-18 00:14:45 +0000[diff] [blame]45
Graeme Russ43261532010-10-07 20:03:23 +1100[diff] [blame]46void dump_regs(struct irq_regs *regs)
Graeme Russc39acb42010-04-24 00:05:38 +1000[diff] [blame]47{
48 unsigned long cr0 = 0L, cr2 = 0L, cr3 = 0L, cr4 = 0L;
49 unsigned long d0, d1, d2, d3, d6, d7;
Graeme Russ68699802011-02-12 15:11:28 +1100[diff] [blame]50 unsigned long sp;
Graeme Russc39acb42010-04-24 00:05:38 +1000[diff] [blame]51
52 printf("EIP: %04x:[<%08lx>] EFLAGS: %08lx\n",
53 (u16)regs->xcs, regs->eip, regs->eflags);
54
55 printf("EAX: %08lx EBX: %08lx ECX: %08lx EDX: %08lx\n",
56 regs->eax, regs->ebx, regs->ecx, regs->edx);
57 printf("ESI: %08lx EDI: %08lx EBP: %08lx ESP: %08lx\n",
58 regs->esi, regs->edi, regs->ebp, regs->esp);
59 printf(" DS: %04x ES: %04x FS: %04x GS: %04x SS: %04x\n",
Graeme Russfdee8b12011-11-08 02:33:13 +0000[diff] [blame]60 (u16)regs->xds, (u16)regs->xes, (u16)regs->xfs,
61 (u16)regs->xgs, (u16)regs->xss);
Graeme Russc39acb42010-04-24 00:05:38 +1000[diff] [blame]62
63 cr0 = read_cr0();
64 cr2 = read_cr2();
65 cr3 = read_cr3();
66 cr4 = read_cr4();
67
68 printf("CR0: %08lx CR2: %08lx CR3: %08lx CR4: %08lx\n",
69 cr0, cr2, cr3, cr4);
70
71 d0 = get_debugreg(0);
72 d1 = get_debugreg(1);
73 d2 = get_debugreg(2);
74 d3 = get_debugreg(3);
75
76 printf("DR0: %08lx DR1: %08lx DR2: %08lx DR3: %08lx\n",
77 d0, d1, d2, d3);
78
79 d6 = get_debugreg(6);
80 d7 = get_debugreg(7);
81 printf("DR6: %08lx DR7: %08lx\n",
82 d6, d7);
Graeme Russ68699802011-02-12 15:11:28 +1100[diff] [blame]83
84 printf("Stack:\n");
85 sp = regs->esp;
86
87 sp += 64;
88
89 while (sp > (regs->esp - 16)) {
90 if (sp == regs->esp)
91 printf("--->");
92 else
93 printf(" ");
94 printf("0x%8.8lx : 0x%8.8lx\n", sp, (ulong)readl(sp));
95 sp -= 4;
96 }
Graeme Russc39acb42010-04-24 00:05:38 +1000[diff] [blame]97}
98
wdenk591dda52002-11-18 00:14:45 +0000[diff] [blame]99struct idt_entry {
100 u16 base_low;
101 u16 selector;
102 u8 res;
103 u8 access;
104 u16 base_high;
Graeme Russfdee8b12011-11-08 02:33:13 +0000[diff] [blame]105} __packed;
wdenk591dda52002-11-18 00:14:45 +0000[diff] [blame]106
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]107struct desc_ptr {
108 unsigned short size;
109 unsigned long address;
110 unsigned short segment;
Graeme Russfdee8b12011-11-08 02:33:13 +0000[diff] [blame]111} __packed;
wdenk591dda52002-11-18 00:14:45 +0000[diff] [blame]112
Graeme Russaf3f2c82011-12-19 14:26:18 +1100[diff] [blame]113struct idt_entry idt[256] __aligned(16);
wdenk591dda52002-11-18 00:14:45 +0000[diff] [blame]114
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]115struct desc_ptr idt_ptr;
wdenk591dda52002-11-18 00:14:45 +0000[diff] [blame]116
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]117static inline void load_idt(const struct desc_ptr *dtr)
118{
Graeme Russfdee8b12011-11-08 02:33:13 +0000[diff] [blame]119 asm volatile("cs lidt %0" : : "m" (*dtr));
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]120}
wdenk591dda52002-11-18 00:14:45 +0000[diff] [blame]121
Graeme Russ77290ee2009-02-24 21:13:40 +1100[diff] [blame]122void set_vector(u8 intnum, void *routine)
wdenk591dda52002-11-18 00:14:45 +0000[diff] [blame]123{
Graeme Russ078395c2009-11-24 20:04:21 +1100[diff] [blame]124 idt[intnum].base_high = (u16)((u32)(routine) >> 16);
125 idt[intnum].base_low = (u16)((u32)(routine) & 0xffff);
wdenk591dda52002-11-18 00:14:45 +0000[diff] [blame]126}
127
Graeme Russfdee8b12011-11-08 02:33:13 +0000[diff] [blame]128/*
129 * Ideally these would be defined static to avoid a checkpatch warning, but
130 * the compiler cannot see them in the inline asm and complains that they
131 * aren't defined
132 */
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]133void irq_0(void);
134void irq_1(void);
wdenk591dda52002-11-18 00:14:45 +0000[diff] [blame]135
Graeme Russ77290ee2009-02-24 21:13:40 +1100[diff] [blame]136int cpu_init_interrupts(void)
wdenk591dda52002-11-18 00:14:45 +0000[diff] [blame]137{
138 int i;
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]139
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]140 int irq_entry_size = irq_1 - irq_0;
141 void *irq_entry = (void *)irq_0;
142
wdenk591dda52002-11-18 00:14:45 +0000[diff] [blame]143 /* Just in case... */
144 disable_interrupts();
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]145
wdenk591dda52002-11-18 00:14:45 +0000[diff] [blame]146 /* Setup the IDT */
Graeme Russfdee8b12011-11-08 02:33:13 +0000[diff] [blame]147 for (i = 0; i < 256; i++) {
wdenk591dda52002-11-18 00:14:45 +0000[diff] [blame]148 idt[i].access = 0x8e;
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]149 idt[i].res = 0;
150 idt[i].selector = 0x10;
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]151 set_vector(i, irq_entry);
152 irq_entry += irq_entry_size;
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]153 }
154
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]155 idt_ptr.size = 256 * 8;
156 idt_ptr.address = (unsigned long) idt;
157 idt_ptr.segment = 0x18;
158
159 load_idt(&idt_ptr);
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]160
wdenk591dda52002-11-18 00:14:45 +0000[diff] [blame]161 /* It is now safe to enable interrupts */
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]162 enable_interrupts();
163
wdenk591dda52002-11-18 00:14:45 +0000[diff] [blame]164 return 0;
165}
166
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]167void __do_irq(int irq)
168{
169 printf("Unhandled IRQ : %d\n", irq);
170}
171void do_irq(int irq) __attribute__((weak, alias("__do_irq")));
172
wdenk591dda52002-11-18 00:14:45 +0000[diff] [blame]173void enable_interrupts(void)
174{
175 asm("sti\n");
176}
177
178int disable_interrupts(void)
179{
180 long flags;
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]181
wdenk591dda52002-11-18 00:14:45 +0000[diff] [blame]182 asm volatile ("pushfl ; popl %0 ; cli\n" : "=g" (flags) : );
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]183
Graeme Russfdee8b12011-11-08 02:33:13 +0000[diff] [blame]184 return flags & X86_EFLAGS_IF;
wdenk591dda52002-11-18 00:14:45 +0000[diff] [blame]185}
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]186
187/* IRQ Low-Level Service Routine */
Graeme Russ43261532010-10-07 20:03:23 +1100[diff] [blame]188void irq_llsr(struct irq_regs *regs)
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]189{
190 /*
191 * For detailed description of each exception, refer to:
Albert ARIBAUD60fbc8d2011-08-04 18:45:45 +0200[diff] [blame]192 * Intel® 64 and IA-32 Architectures Software Developer's Manual
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]193 * Volume 1: Basic Architecture
194 * Order Number: 253665-029US, November 2008
195 * Table 6-1. Exceptions and Interrupts
196 */
Graeme Russ43261532010-10-07 20:03:23 +1100[diff] [blame]197 switch (regs->irq_id) {
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]198 case 0x00:
Graeme Russc39acb42010-04-24 00:05:38 +1000[diff] [blame]199 printf("Divide Error (Division by zero)\n");
200 dump_regs(regs);
Graeme Russ5e0e2872011-11-08 02:33:12 +0000[diff] [blame]201 hang();
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]202 break;
203 case 0x01:
Graeme Russc39acb42010-04-24 00:05:38 +1000[diff] [blame]204 printf("Debug Interrupt (Single step)\n");
205 dump_regs(regs);
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]206 break;
207 case 0x02:
Graeme Russc39acb42010-04-24 00:05:38 +1000[diff] [blame]208 printf("NMI Interrupt\n");
209 dump_regs(regs);
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]210 break;
211 case 0x03:
Graeme Russc39acb42010-04-24 00:05:38 +1000[diff] [blame]212 printf("Breakpoint\n");
213 dump_regs(regs);
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]214 break;
215 case 0x04:
Graeme Russc39acb42010-04-24 00:05:38 +1000[diff] [blame]216 printf("Overflow\n");
217 dump_regs(regs);
Graeme Russ5e0e2872011-11-08 02:33:12 +0000[diff] [blame]218 hang();
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]219 break;
220 case 0x05:
Graeme Russc39acb42010-04-24 00:05:38 +1000[diff] [blame]221 printf("BOUND Range Exceeded\n");
222 dump_regs(regs);
Graeme Russ5e0e2872011-11-08 02:33:12 +0000[diff] [blame]223 hang();
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]224 break;
225 case 0x06:
Graeme Russc39acb42010-04-24 00:05:38 +1000[diff] [blame]226 printf("Invalid Opcode (UnDefined Opcode)\n");
227 dump_regs(regs);
Graeme Russ5e0e2872011-11-08 02:33:12 +0000[diff] [blame]228 hang();
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]229 break;
230 case 0x07:
Graeme Russc39acb42010-04-24 00:05:38 +1000[diff] [blame]231 printf("Device Not Available (No Math Coprocessor)\n");
232 dump_regs(regs);
Graeme Russ5e0e2872011-11-08 02:33:12 +0000[diff] [blame]233 hang();
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]234 break;
235 case 0x08:
Graeme Russc39acb42010-04-24 00:05:38 +1000[diff] [blame]236 printf("Double fault\n");
237 dump_regs(regs);
Graeme Russ5e0e2872011-11-08 02:33:12 +0000[diff] [blame]238 hang();
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]239 break;
240 case 0x09:
Graeme Russc39acb42010-04-24 00:05:38 +1000[diff] [blame]241 printf("Co-processor segment overrun\n");
242 dump_regs(regs);
Graeme Russ5e0e2872011-11-08 02:33:12 +0000[diff] [blame]243 hang();
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]244 break;
245 case 0x0a:
Graeme Russc39acb42010-04-24 00:05:38 +1000[diff] [blame]246 printf("Invalid TSS\n");
247 dump_regs(regs);
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]248 break;
249 case 0x0b:
Graeme Russc39acb42010-04-24 00:05:38 +1000[diff] [blame]250 printf("Segment Not Present\n");
251 dump_regs(regs);
Graeme Russ5e0e2872011-11-08 02:33:12 +0000[diff] [blame]252 hang();
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]253 break;
254 case 0x0c:
Graeme Russc39acb42010-04-24 00:05:38 +1000[diff] [blame]255 printf("Stack Segment Fault\n");
256 dump_regs(regs);
Graeme Russ5e0e2872011-11-08 02:33:12 +0000[diff] [blame]257 hang();
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]258 break;
259 case 0x0d:
Graeme Russc39acb42010-04-24 00:05:38 +1000[diff] [blame]260 printf("General Protection\n");
261 dump_regs(regs);
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]262 break;
263 case 0x0e:
Graeme Russc39acb42010-04-24 00:05:38 +1000[diff] [blame]264 printf("Page fault\n");
265 dump_regs(regs);
Graeme Russ5e0e2872011-11-08 02:33:12 +0000[diff] [blame]266 hang();
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]267 break;
268 case 0x0f:
Graeme Russc39acb42010-04-24 00:05:38 +1000[diff] [blame]269 printf("Floating-Point Error (Math Fault)\n");
270 dump_regs(regs);
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]271 break;
272 case 0x10:
Graeme Russc39acb42010-04-24 00:05:38 +1000[diff] [blame]273 printf("Alignment check\n");
274 dump_regs(regs);
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]275 break;
276 case 0x11:
Graeme Russc39acb42010-04-24 00:05:38 +1000[diff] [blame]277 printf("Machine Check\n");
278 dump_regs(regs);
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]279 break;
280 case 0x12:
Graeme Russc39acb42010-04-24 00:05:38 +1000[diff] [blame]281 printf("SIMD Floating-Point Exception\n");
282 dump_regs(regs);
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]283 break;
284 case 0x13:
285 case 0x14:
286 case 0x15:
287 case 0x16:
288 case 0x17:
289 case 0x18:
290 case 0x19:
291 case 0x1a:
292 case 0x1b:
293 case 0x1c:
294 case 0x1d:
295 case 0x1e:
296 case 0x1f:
Graeme Russc39acb42010-04-24 00:05:38 +1000[diff] [blame]297 printf("Reserved Exception\n");
298 dump_regs(regs);
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]299 break;
300
301 default:
302 /* Hardware or User IRQ */
Graeme Russ43261532010-10-07 20:03:23 +1100[diff] [blame]303 do_irq(regs->irq_id);
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]304 }
305}
306
307/*
308 * OK - This looks really horrible, but it serves a purpose - It helps create
309 * fully relocatable code.
310 * - The call to irq_llsr will be a relative jump
311 * - The IRQ entries will be guaranteed to be in order
Graeme Russc39acb42010-04-24 00:05:38 +1000[diff] [blame]312 * Interrupt entries are now very small (a push and a jump) but they are
313 * now slower (all registers pushed on stack which provides complete
314 * crash dumps in the low level handlers
Graeme Russ43261532010-10-07 20:03:23 +1100[diff] [blame]315 *
316 * Interrupt Entry Point:
317 * - Interrupt has caused eflags, CS and EIP to be pushed
318 * - Interrupt Vector Handler has pushed orig_eax
319 * - pt_regs.esp needs to be adjusted by 40 bytes:
320 * 12 bytes pushed by CPU (EFLAGSF, CS, EIP)
321 * 4 bytes pushed by vector handler (irq_id)
322 * 24 bytes pushed before SP (SS, GS, FS, ES, DS, EAX)
323 * NOTE: Only longs are pushed on/popped off the stack!
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]324 */
325asm(".globl irq_common_entry\n" \
Graeme Russ1aafcc92009-11-24 20:04:19 +1100[diff] [blame]326 ".hidden irq_common_entry\n" \
327 ".type irq_common_entry, @function\n" \
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]328 "irq_common_entry:\n" \
Graeme Russc39acb42010-04-24 00:05:38 +1000[diff] [blame]329 "cld\n" \
Graeme Russ43261532010-10-07 20:03:23 +1100[diff] [blame]330 "pushl %ss\n" \
Graeme Russc39acb42010-04-24 00:05:38 +1000[diff] [blame]331 "pushl %gs\n" \
332 "pushl %fs\n" \
333 "pushl %es\n" \
334 "pushl %ds\n" \
335 "pushl %eax\n" \
Graeme Russ43261532010-10-07 20:03:23 +1100[diff] [blame]336 "movl %esp, %eax\n" \
337 "addl $40, %eax\n" \
338 "pushl %eax\n" \
Graeme Russc39acb42010-04-24 00:05:38 +1000[diff] [blame]339 "pushl %ebp\n" \
340 "pushl %edi\n" \
341 "pushl %esi\n" \
342 "pushl %edx\n" \
343 "pushl %ecx\n" \
344 "pushl %ebx\n" \
345 "mov %esp, %eax\n" \
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]346 "call irq_llsr\n" \
Graeme Russc39acb42010-04-24 00:05:38 +1000[diff] [blame]347 "popl %ebx\n" \
348 "popl %ecx\n" \
349 "popl %edx\n" \
350 "popl %esi\n" \
351 "popl %edi\n" \
352 "popl %ebp\n" \
353 "popl %eax\n" \
Graeme Russ43261532010-10-07 20:03:23 +1100[diff] [blame]354 "popl %eax\n" \
Graeme Russc39acb42010-04-24 00:05:38 +1000[diff] [blame]355 "popl %ds\n" \
356 "popl %es\n" \
357 "popl %fs\n" \
358 "popl %gs\n" \
Graeme Russ43261532010-10-07 20:03:23 +1100[diff] [blame]359 "popl %ss\n" \
Graeme Russc39acb42010-04-24 00:05:38 +1000[diff] [blame]360 "add $4, %esp\n" \
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]361 "iret\n" \
362 DECLARE_INTERRUPT(0) \
363 DECLARE_INTERRUPT(1) \
364 DECLARE_INTERRUPT(2) \
365 DECLARE_INTERRUPT(3) \
366 DECLARE_INTERRUPT(4) \
367 DECLARE_INTERRUPT(5) \
368 DECLARE_INTERRUPT(6) \
369 DECLARE_INTERRUPT(7) \
370 DECLARE_INTERRUPT(8) \
371 DECLARE_INTERRUPT(9) \
372 DECLARE_INTERRUPT(10) \
373 DECLARE_INTERRUPT(11) \
374 DECLARE_INTERRUPT(12) \
375 DECLARE_INTERRUPT(13) \
376 DECLARE_INTERRUPT(14) \
377 DECLARE_INTERRUPT(15) \
378 DECLARE_INTERRUPT(16) \
379 DECLARE_INTERRUPT(17) \
380 DECLARE_INTERRUPT(18) \
381 DECLARE_INTERRUPT(19) \
382 DECLARE_INTERRUPT(20) \
383 DECLARE_INTERRUPT(21) \
384 DECLARE_INTERRUPT(22) \
385 DECLARE_INTERRUPT(23) \
386 DECLARE_INTERRUPT(24) \
387 DECLARE_INTERRUPT(25) \
388 DECLARE_INTERRUPT(26) \
389 DECLARE_INTERRUPT(27) \
390 DECLARE_INTERRUPT(28) \
391 DECLARE_INTERRUPT(29) \
392 DECLARE_INTERRUPT(30) \
393 DECLARE_INTERRUPT(31) \
394 DECLARE_INTERRUPT(32) \
395 DECLARE_INTERRUPT(33) \
396 DECLARE_INTERRUPT(34) \
397 DECLARE_INTERRUPT(35) \
398 DECLARE_INTERRUPT(36) \
399 DECLARE_INTERRUPT(37) \
400 DECLARE_INTERRUPT(38) \
401 DECLARE_INTERRUPT(39) \
402 DECLARE_INTERRUPT(40) \
403 DECLARE_INTERRUPT(41) \
404 DECLARE_INTERRUPT(42) \
405 DECLARE_INTERRUPT(43) \
406 DECLARE_INTERRUPT(44) \
407 DECLARE_INTERRUPT(45) \
408 DECLARE_INTERRUPT(46) \
409 DECLARE_INTERRUPT(47) \
410 DECLARE_INTERRUPT(48) \
411 DECLARE_INTERRUPT(49) \
412 DECLARE_INTERRUPT(50) \
413 DECLARE_INTERRUPT(51) \
414 DECLARE_INTERRUPT(52) \
415 DECLARE_INTERRUPT(53) \
416 DECLARE_INTERRUPT(54) \
417 DECLARE_INTERRUPT(55) \
418 DECLARE_INTERRUPT(56) \
419 DECLARE_INTERRUPT(57) \
420 DECLARE_INTERRUPT(58) \
421 DECLARE_INTERRUPT(59) \
422 DECLARE_INTERRUPT(60) \
423 DECLARE_INTERRUPT(61) \
424 DECLARE_INTERRUPT(62) \
425 DECLARE_INTERRUPT(63) \
426 DECLARE_INTERRUPT(64) \
427 DECLARE_INTERRUPT(65) \
428 DECLARE_INTERRUPT(66) \
429 DECLARE_INTERRUPT(67) \
430 DECLARE_INTERRUPT(68) \
431 DECLARE_INTERRUPT(69) \
432 DECLARE_INTERRUPT(70) \
433 DECLARE_INTERRUPT(71) \
434 DECLARE_INTERRUPT(72) \
435 DECLARE_INTERRUPT(73) \
436 DECLARE_INTERRUPT(74) \
437 DECLARE_INTERRUPT(75) \
438 DECLARE_INTERRUPT(76) \
439 DECLARE_INTERRUPT(77) \
440 DECLARE_INTERRUPT(78) \
441 DECLARE_INTERRUPT(79) \
442 DECLARE_INTERRUPT(80) \
443 DECLARE_INTERRUPT(81) \
444 DECLARE_INTERRUPT(82) \
445 DECLARE_INTERRUPT(83) \
446 DECLARE_INTERRUPT(84) \
447 DECLARE_INTERRUPT(85) \
448 DECLARE_INTERRUPT(86) \
449 DECLARE_INTERRUPT(87) \
450 DECLARE_INTERRUPT(88) \
451 DECLARE_INTERRUPT(89) \
452 DECLARE_INTERRUPT(90) \
453 DECLARE_INTERRUPT(91) \
454 DECLARE_INTERRUPT(92) \
455 DECLARE_INTERRUPT(93) \
456 DECLARE_INTERRUPT(94) \
457 DECLARE_INTERRUPT(95) \
458 DECLARE_INTERRUPT(97) \
459 DECLARE_INTERRUPT(96) \
460 DECLARE_INTERRUPT(98) \
461 DECLARE_INTERRUPT(99) \
462 DECLARE_INTERRUPT(100) \
463 DECLARE_INTERRUPT(101) \
464 DECLARE_INTERRUPT(102) \
465 DECLARE_INTERRUPT(103) \
466 DECLARE_INTERRUPT(104) \
467 DECLARE_INTERRUPT(105) \
468 DECLARE_INTERRUPT(106) \
469 DECLARE_INTERRUPT(107) \
470 DECLARE_INTERRUPT(108) \
471 DECLARE_INTERRUPT(109) \
472 DECLARE_INTERRUPT(110) \
473 DECLARE_INTERRUPT(111) \
474 DECLARE_INTERRUPT(112) \
475 DECLARE_INTERRUPT(113) \
476 DECLARE_INTERRUPT(114) \
477 DECLARE_INTERRUPT(115) \
478 DECLARE_INTERRUPT(116) \
479 DECLARE_INTERRUPT(117) \
480 DECLARE_INTERRUPT(118) \
481 DECLARE_INTERRUPT(119) \
482 DECLARE_INTERRUPT(120) \
483 DECLARE_INTERRUPT(121) \
484 DECLARE_INTERRUPT(122) \
485 DECLARE_INTERRUPT(123) \
486 DECLARE_INTERRUPT(124) \
487 DECLARE_INTERRUPT(125) \
488 DECLARE_INTERRUPT(126) \
489 DECLARE_INTERRUPT(127) \
490 DECLARE_INTERRUPT(128) \
491 DECLARE_INTERRUPT(129) \
492 DECLARE_INTERRUPT(130) \
493 DECLARE_INTERRUPT(131) \
494 DECLARE_INTERRUPT(132) \
495 DECLARE_INTERRUPT(133) \
496 DECLARE_INTERRUPT(134) \
497 DECLARE_INTERRUPT(135) \
498 DECLARE_INTERRUPT(136) \
499 DECLARE_INTERRUPT(137) \
500 DECLARE_INTERRUPT(138) \
501 DECLARE_INTERRUPT(139) \
502 DECLARE_INTERRUPT(140) \
503 DECLARE_INTERRUPT(141) \
504 DECLARE_INTERRUPT(142) \
505 DECLARE_INTERRUPT(143) \
506 DECLARE_INTERRUPT(144) \
507 DECLARE_INTERRUPT(145) \
508 DECLARE_INTERRUPT(146) \
509 DECLARE_INTERRUPT(147) \
510 DECLARE_INTERRUPT(148) \
511 DECLARE_INTERRUPT(149) \
512 DECLARE_INTERRUPT(150) \
513 DECLARE_INTERRUPT(151) \
514 DECLARE_INTERRUPT(152) \
515 DECLARE_INTERRUPT(153) \
516 DECLARE_INTERRUPT(154) \
517 DECLARE_INTERRUPT(155) \
518 DECLARE_INTERRUPT(156) \
519 DECLARE_INTERRUPT(157) \
520 DECLARE_INTERRUPT(158) \
521 DECLARE_INTERRUPT(159) \
522 DECLARE_INTERRUPT(160) \
523 DECLARE_INTERRUPT(161) \
524 DECLARE_INTERRUPT(162) \
525 DECLARE_INTERRUPT(163) \
526 DECLARE_INTERRUPT(164) \
527 DECLARE_INTERRUPT(165) \
528 DECLARE_INTERRUPT(166) \
529 DECLARE_INTERRUPT(167) \
530 DECLARE_INTERRUPT(168) \
531 DECLARE_INTERRUPT(169) \
532 DECLARE_INTERRUPT(170) \
533 DECLARE_INTERRUPT(171) \
534 DECLARE_INTERRUPT(172) \
535 DECLARE_INTERRUPT(173) \
536 DECLARE_INTERRUPT(174) \
537 DECLARE_INTERRUPT(175) \
538 DECLARE_INTERRUPT(176) \
539 DECLARE_INTERRUPT(177) \
540 DECLARE_INTERRUPT(178) \
541 DECLARE_INTERRUPT(179) \
542 DECLARE_INTERRUPT(180) \
543 DECLARE_INTERRUPT(181) \
544 DECLARE_INTERRUPT(182) \
545 DECLARE_INTERRUPT(183) \
546 DECLARE_INTERRUPT(184) \
547 DECLARE_INTERRUPT(185) \
548 DECLARE_INTERRUPT(186) \
549 DECLARE_INTERRUPT(187) \
550 DECLARE_INTERRUPT(188) \
551 DECLARE_INTERRUPT(189) \
552 DECLARE_INTERRUPT(190) \
553 DECLARE_INTERRUPT(191) \
554 DECLARE_INTERRUPT(192) \
555 DECLARE_INTERRUPT(193) \
556 DECLARE_INTERRUPT(194) \
557 DECLARE_INTERRUPT(195) \
558 DECLARE_INTERRUPT(196) \
559 DECLARE_INTERRUPT(197) \
560 DECLARE_INTERRUPT(198) \
561 DECLARE_INTERRUPT(199) \
562 DECLARE_INTERRUPT(200) \
563 DECLARE_INTERRUPT(201) \
564 DECLARE_INTERRUPT(202) \
565 DECLARE_INTERRUPT(203) \
566 DECLARE_INTERRUPT(204) \
567 DECLARE_INTERRUPT(205) \
568 DECLARE_INTERRUPT(206) \
569 DECLARE_INTERRUPT(207) \
570 DECLARE_INTERRUPT(208) \
571 DECLARE_INTERRUPT(209) \
572 DECLARE_INTERRUPT(210) \
573 DECLARE_INTERRUPT(211) \
574 DECLARE_INTERRUPT(212) \
575 DECLARE_INTERRUPT(213) \
576 DECLARE_INTERRUPT(214) \
577 DECLARE_INTERRUPT(215) \
578 DECLARE_INTERRUPT(216) \
579 DECLARE_INTERRUPT(217) \
580 DECLARE_INTERRUPT(218) \
581 DECLARE_INTERRUPT(219) \
582 DECLARE_INTERRUPT(220) \
583 DECLARE_INTERRUPT(221) \
584 DECLARE_INTERRUPT(222) \
585 DECLARE_INTERRUPT(223) \
586 DECLARE_INTERRUPT(224) \
587 DECLARE_INTERRUPT(225) \
588 DECLARE_INTERRUPT(226) \
589 DECLARE_INTERRUPT(227) \
590 DECLARE_INTERRUPT(228) \
591 DECLARE_INTERRUPT(229) \
592 DECLARE_INTERRUPT(230) \
593 DECLARE_INTERRUPT(231) \
594 DECLARE_INTERRUPT(232) \
595 DECLARE_INTERRUPT(233) \
596 DECLARE_INTERRUPT(234) \
597 DECLARE_INTERRUPT(235) \
598 DECLARE_INTERRUPT(236) \
599 DECLARE_INTERRUPT(237) \
600 DECLARE_INTERRUPT(238) \
601 DECLARE_INTERRUPT(239) \
602 DECLARE_INTERRUPT(240) \
603 DECLARE_INTERRUPT(241) \
604 DECLARE_INTERRUPT(242) \
605 DECLARE_INTERRUPT(243) \
606 DECLARE_INTERRUPT(244) \
607 DECLARE_INTERRUPT(245) \
608 DECLARE_INTERRUPT(246) \
609 DECLARE_INTERRUPT(247) \
610 DECLARE_INTERRUPT(248) \
611 DECLARE_INTERRUPT(249) \
612 DECLARE_INTERRUPT(250) \
613 DECLARE_INTERRUPT(251) \
614 DECLARE_INTERRUPT(252) \
615 DECLARE_INTERRUPT(253) \
616 DECLARE_INTERRUPT(254) \
617 DECLARE_INTERRUPT(255));