Masahiro Yamada | 144a3e0 | 2015-04-21 20:38:20 +0900 | [diff] [blame] | 1 | if ARCH_SOCFPGA |
| 2 | |
Simon Goldschmidt | 17d7852 | 2019-10-22 21:29:48 +0200 | [diff] [blame] | 3 | config ERR_PTR_OFFSET |
| 4 | default 0xfffec000 if TARGET_SOCFPGA_GEN5 # Boot ROM range |
| 5 | |
Simon Goldschmidt | b1c4269 | 2019-04-09 21:02:05 +0200 | [diff] [blame] | 6 | config NR_DRAM_BANKS |
| 7 | default 1 |
| 8 | |
Siew Chin Lim | 2492d59 | 2021-03-01 20:04:11 +0800 | [diff] [blame] | 9 | config SOCFPGA_SECURE_VAB_AUTH |
| 10 | bool "Enable boot image authentication with Secure Device Manager" |
Jit Loon Lim | 977071e | 2024-03-12 22:01:03 +0800 | [diff] [blame] | 11 | depends on TARGET_SOCFPGA_AGILEX || TARGET_SOCFPGA_N5X || \ |
| 12 | TARGET_SOCFPGA_AGILEX5 |
Siew Chin Lim | 2492d59 | 2021-03-01 20:04:11 +0800 | [diff] [blame] | 13 | select FIT_IMAGE_POST_PROCESS |
| 14 | select SHA384 |
Alexandru Gagniuc | 5df5d69 | 2021-09-02 19:54:18 -0500 | [diff] [blame] | 15 | select SHA512 |
Siew Chin Lim | 2492d59 | 2021-03-01 20:04:11 +0800 | [diff] [blame] | 16 | select SPL_FIT_IMAGE_POST_PROCESS |
| 17 | help |
| 18 | All images loaded from FIT will be authenticated by Secure Device |
| 19 | Manager. |
| 20 | |
| 21 | config SOCFPGA_SECURE_VAB_AUTH_ALLOW_NON_FIT_IMAGE |
| 22 | bool "Allow non-FIT VAB signed images" |
| 23 | depends on SOCFPGA_SECURE_VAB_AUTH |
| 24 | |
Simon Goldschmidt | 20fd7de | 2019-06-13 21:50:28 +0200 | [diff] [blame] | 25 | config SPL_SIZE_LIMIT |
Simon Glass | a8f0c94 | 2019-09-25 08:56:28 -0600 | [diff] [blame] | 26 | default 0x10000 if TARGET_SOCFPGA_GEN5 |
Simon Goldschmidt | 20fd7de | 2019-06-13 21:50:28 +0200 | [diff] [blame] | 27 | |
| 28 | config SPL_SIZE_LIMIT_PROVIDE_STACK |
| 29 | default 0x200 if TARGET_SOCFPGA_GEN5 |
| 30 | |
Simon Goldschmidt | b1c4269 | 2019-04-09 21:02:05 +0200 | [diff] [blame] | 31 | config SPL_STACK_R_ADDR |
| 32 | default 0x00800000 if TARGET_SOCFPGA_GEN5 |
| 33 | |
Simon Glass | b59037b | 2023-09-26 08:14:25 -0600 | [diff] [blame] | 34 | config SPL_SYS_MALLOC_F |
| 35 | default y if TARGET_SOCFPGA_GEN5 |
| 36 | |
Simon Goldschmidt | 4f57b9a | 2019-04-09 21:02:06 +0200 | [diff] [blame] | 37 | config SPL_SYS_MALLOC_F_LEN |
| 38 | default 0x800 if TARGET_SOCFPGA_GEN5 |
| 39 | |
Dalon Westergreen | 8d770f4 | 2017-02-10 17:15:34 -0800 | [diff] [blame] | 40 | config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE |
| 41 | default 0xa2 |
| 42 | |
Simon Goldschmidt | b1c4269 | 2019-04-09 21:02:05 +0200 | [diff] [blame] | 43 | config SYS_MALLOC_F_LEN |
| 44 | default 0x2000 if TARGET_SOCFPGA_ARRIA10 |
| 45 | default 0x2000 if TARGET_SOCFPGA_GEN5 |
| 46 | |
Simon Glass | 72cc538 | 2022-10-20 18:22:39 -0600 | [diff] [blame] | 47 | config TEXT_BASE |
Simon Goldschmidt | b1c4269 | 2019-04-09 21:02:05 +0200 | [diff] [blame] | 48 | default 0x01000040 if TARGET_SOCFPGA_ARRIA10 |
| 49 | default 0x01000040 if TARGET_SOCFPGA_GEN5 |
| 50 | |
Ley Foon Tan | 461d298 | 2019-11-27 15:55:32 +0800 | [diff] [blame] | 51 | config TARGET_SOCFPGA_AGILEX |
| 52 | bool |
| 53 | select ARMV8_MULTIENTRY |
| 54 | select ARMV8_SET_SMPEN |
Siew Chin Lim | dbe60eb | 2020-12-24 18:21:12 +0800 | [diff] [blame] | 55 | select BINMAN if SPL_ATF |
Ley Foon Tan | 461d298 | 2019-11-27 15:55:32 +0800 | [diff] [blame] | 56 | select CLK |
Chee Hong Ang | 89ac34d | 2020-08-07 11:50:05 +0800 | [diff] [blame] | 57 | select FPGA_INTEL_SDM_MAILBOX |
Ley Foon Tan | 461d298 | 2019-11-27 15:55:32 +0800 | [diff] [blame] | 58 | select NCORE_CACHE |
| 59 | select SPL_CLK if SPL |
Siew Chin Lim | 8a71416 | 2021-03-01 20:04:10 +0800 | [diff] [blame] | 60 | select TARGET_SOCFPGA_SOC64 |
Ley Foon Tan | 461d298 | 2019-11-27 15:55:32 +0800 | [diff] [blame] | 61 | |
Jit Loon Lim | 977071e | 2024-03-12 22:01:03 +0800 | [diff] [blame] | 62 | config TARGET_SOCFPGA_AGILEX5 |
| 63 | bool |
| 64 | select BINMAN if SPL_ATF |
| 65 | select CLK |
| 66 | select FPGA_INTEL_SDM_MAILBOX |
| 67 | select GICV3 |
| 68 | select SPL_CLK if SPL |
| 69 | select TARGET_SOCFPGA_SOC64 |
| 70 | |
Marek Vasut | 822e795 | 2015-08-02 21:57:57 +0200 | [diff] [blame] | 71 | config TARGET_SOCFPGA_ARRIA5 |
| 72 | bool |
Dinh Nguyen | 677a16f | 2015-12-02 13:31:25 -0600 | [diff] [blame] | 73 | select TARGET_SOCFPGA_GEN5 |
Marek Vasut | 822e795 | 2015-08-02 21:57:57 +0200 | [diff] [blame] | 74 | |
Ley Foon Tan | 5b7cea6 | 2017-04-26 02:44:48 +0800 | [diff] [blame] | 75 | config TARGET_SOCFPGA_ARRIA10 |
| 76 | bool |
Ley Foon Tan | 17b9ba6 | 2019-05-06 09:55:59 +0800 | [diff] [blame] | 77 | select SPL_ALTERA_SDRAM |
Michal Simek | 7e7ba3b | 2018-07-23 15:55:15 +0200 | [diff] [blame] | 78 | select SPL_BOARD_INIT if SPL |
Ley Foon Tan | 1d07b3e | 2020-04-07 15:43:14 +0800 | [diff] [blame] | 79 | select SPL_CACHE if SPL |
Marek Vasut | e1dcd62 | 2018-07-30 15:56:19 +0200 | [diff] [blame] | 80 | select CLK |
| 81 | select SPL_CLK if SPL |
Marek Vasut | 69fbb88 | 2018-08-13 18:32:38 +0200 | [diff] [blame] | 82 | select DM_I2C |
Marek Vasut | 700b2c6 | 2018-08-13 18:32:38 +0200 | [diff] [blame] | 83 | select DM_RESET |
| 84 | select SPL_DM_RESET if SPL |
Marek Vasut | 04c8f4f | 2018-08-13 20:06:46 +0200 | [diff] [blame] | 85 | select REGMAP |
| 86 | select SPL_REGMAP if SPL |
| 87 | select SYSCON |
| 88 | select SPL_SYSCON if SPL |
| 89 | select ETH_DESIGNWARE_SOCFPGA |
Simon Goldschmidt | b1c4269 | 2019-04-09 21:02:05 +0200 | [diff] [blame] | 90 | imply FPGA_SOCFPGA |
Simon Glass | 7611ac6 | 2019-09-25 08:56:27 -0600 | [diff] [blame] | 91 | imply SPL_USE_TINY_PRINTF |
Ley Foon Tan | 5b7cea6 | 2017-04-26 02:44:48 +0800 | [diff] [blame] | 92 | |
Marek Vasut | 822e795 | 2015-08-02 21:57:57 +0200 | [diff] [blame] | 93 | config TARGET_SOCFPGA_CYCLONE5 |
| 94 | bool |
Dinh Nguyen | 677a16f | 2015-12-02 13:31:25 -0600 | [diff] [blame] | 95 | select TARGET_SOCFPGA_GEN5 |
| 96 | |
| 97 | config TARGET_SOCFPGA_GEN5 |
| 98 | bool |
Ley Foon Tan | 17b9ba6 | 2019-05-06 09:55:59 +0800 | [diff] [blame] | 99 | select SPL_ALTERA_SDRAM |
Simon Goldschmidt | b1c4269 | 2019-04-09 21:02:05 +0200 | [diff] [blame] | 100 | imply FPGA_SOCFPGA |
Simon Goldschmidt | 20fd7de | 2019-06-13 21:50:28 +0200 | [diff] [blame] | 101 | imply SPL_SIZE_LIMIT_SUBTRACT_GD |
| 102 | imply SPL_SIZE_LIMIT_SUBTRACT_MALLOC |
Simon Goldschmidt | b1c4269 | 2019-04-09 21:02:05 +0200 | [diff] [blame] | 103 | imply SPL_STACK_R |
| 104 | imply SPL_SYS_MALLOC_SIMPLE |
Simon Glass | 7611ac6 | 2019-09-25 08:56:27 -0600 | [diff] [blame] | 105 | imply SPL_USE_TINY_PRINTF |
Marek Vasut | 822e795 | 2015-08-02 21:57:57 +0200 | [diff] [blame] | 106 | |
Siew Chin Lim | 988bfe4 | 2021-08-10 11:26:42 +0800 | [diff] [blame] | 107 | config TARGET_SOCFPGA_N5X |
| 108 | bool |
| 109 | select ARMV8_MULTIENTRY |
| 110 | select ARMV8_SET_SMPEN |
| 111 | select BINMAN if SPL_ATF |
| 112 | select CLK |
| 113 | select FPGA_INTEL_SDM_MAILBOX |
| 114 | select NCORE_CACHE |
| 115 | select SPL_ALTERA_SDRAM |
| 116 | select SPL_CLK if SPL |
| 117 | select TARGET_SOCFPGA_SOC64 |
| 118 | |
| 119 | config TARGET_SOCFPGA_N5X_SOCDK |
| 120 | bool "Intel eASIC SoCDK (N5X)" |
| 121 | select TARGET_SOCFPGA_N5X |
| 122 | |
Siew Chin Lim | 8a71416 | 2021-03-01 20:04:10 +0800 | [diff] [blame] | 123 | config TARGET_SOCFPGA_SOC64 |
| 124 | bool |
| 125 | |
Ley Foon Tan | 9c407b5 | 2018-05-24 00:17:32 +0800 | [diff] [blame] | 126 | config TARGET_SOCFPGA_STRATIX10 |
| 127 | bool |
| 128 | select ARMV8_MULTIENTRY |
Ley Foon Tan | 9c407b5 | 2018-05-24 00:17:32 +0800 | [diff] [blame] | 129 | select ARMV8_SET_SMPEN |
Siew Chin Lim | dbe60eb | 2020-12-24 18:21:12 +0800 | [diff] [blame] | 130 | select BINMAN if SPL_ATF |
Chee Hong Ang | 1419245 | 2020-08-07 11:50:03 +0800 | [diff] [blame] | 131 | select FPGA_INTEL_SDM_MAILBOX |
Siew Chin Lim | 8a71416 | 2021-03-01 20:04:10 +0800 | [diff] [blame] | 132 | select TARGET_SOCFPGA_SOC64 |
Ley Foon Tan | 9c407b5 | 2018-05-24 00:17:32 +0800 | [diff] [blame] | 133 | |
Masahiro Yamada | 144a3e0 | 2015-04-21 20:38:20 +0900 | [diff] [blame] | 134 | choice |
| 135 | prompt "Altera SOCFPGA board select" |
Joe Hershberger | f069960 | 2015-05-12 14:46:23 -0500 | [diff] [blame] | 136 | optional |
Masahiro Yamada | 144a3e0 | 2015-04-21 20:38:20 +0900 | [diff] [blame] | 137 | |
Ley Foon Tan | 461d298 | 2019-11-27 15:55:32 +0800 | [diff] [blame] | 138 | config TARGET_SOCFPGA_AGILEX_SOCDK |
| 139 | bool "Intel SOCFPGA SoCDK (Agilex)" |
| 140 | select TARGET_SOCFPGA_AGILEX |
| 141 | |
Jit Loon Lim | 977071e | 2024-03-12 22:01:03 +0800 | [diff] [blame] | 142 | config TARGET_SOCFPGA_AGILEX5_SOCDK |
| 143 | bool "Intel SOCFPGA SoCDK (Agilex5)" |
| 144 | select TARGET_SOCFPGA_AGILEX5 |
| 145 | |
Wolfgang Grandegger | 7789aab2 | 2019-05-12 19:25:18 +0200 | [diff] [blame] | 146 | config TARGET_SOCFPGA_ARIES_MCVEVK |
| 147 | bool "Aries MCVEVK (Cyclone V)" |
| 148 | select TARGET_SOCFPGA_CYCLONE5 |
| 149 | |
Ley Foon Tan | 5b7cea6 | 2017-04-26 02:44:48 +0800 | [diff] [blame] | 150 | config TARGET_SOCFPGA_ARRIA10_SOCDK |
| 151 | bool "Altera SOCFPGA SoCDK (Arria 10)" |
| 152 | select TARGET_SOCFPGA_ARRIA10 |
| 153 | |
Holger Brunck | ddef889 | 2020-02-19 19:55:14 +0100 | [diff] [blame] | 154 | config TARGET_SOCFPGA_ARRIA5_SECU1 |
| 155 | bool "ABB SECU1 (Arria V)" |
| 156 | select TARGET_SOCFPGA_ARRIA5 |
| 157 | select VENDOR_KM |
| 158 | |
Marek Vasut | 822e795 | 2015-08-02 21:57:57 +0200 | [diff] [blame] | 159 | config TARGET_SOCFPGA_ARRIA5_SOCDK |
| 160 | bool "Altera SOCFPGA SoCDK (Arria V)" |
| 161 | select TARGET_SOCFPGA_ARRIA5 |
Masahiro Yamada | 144a3e0 | 2015-04-21 20:38:20 +0900 | [diff] [blame] | 162 | |
Paweł Anikiel | 5ee903d | 2022-06-17 12:47:20 +0200 | [diff] [blame] | 163 | config TARGET_SOCFPGA_CHAMELEONV3 |
| 164 | bool "Google Chameleon v3 (Arria 10)" |
| 165 | select TARGET_SOCFPGA_ARRIA10 |
| 166 | |
Marek Vasut | 822e795 | 2015-08-02 21:57:57 +0200 | [diff] [blame] | 167 | config TARGET_SOCFPGA_CYCLONE5_SOCDK |
| 168 | bool "Altera SOCFPGA SoCDK (Cyclone V)" |
| 169 | select TARGET_SOCFPGA_CYCLONE5 |
Masahiro Yamada | 144a3e0 | 2015-04-21 20:38:20 +0900 | [diff] [blame] | 170 | |
Marek Vasut | b06dad2 | 2018-02-24 23:34:00 +0100 | [diff] [blame] | 171 | config TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1 |
| 172 | bool "Devboards DBM-SoC1 (Cyclone V)" |
| 173 | select TARGET_SOCFPGA_CYCLONE5 |
| 174 | |
Marek Vasut | 567356a | 2015-11-23 17:06:27 +0100 | [diff] [blame] | 175 | config TARGET_SOCFPGA_EBV_SOCRATES |
| 176 | bool "EBV SoCrates (Cyclone V)" |
| 177 | select TARGET_SOCFPGA_CYCLONE5 |
| 178 | |
Pavel Machek | 9802e87 | 2016-06-07 12:37:23 +0200 | [diff] [blame] | 179 | config TARGET_SOCFPGA_IS1 |
| 180 | bool "IS1 (Cyclone V)" |
| 181 | select TARGET_SOCFPGA_CYCLONE5 |
| 182 | |
Marek Vasut | 13da18c | 2019-06-27 00:19:31 +0200 | [diff] [blame] | 183 | config TARGET_SOCFPGA_SOFTING_VINING_FPGA |
| 184 | bool "Softing VIN|ING FPGA (Cyclone V)" |
Tom Rini | 22d567e | 2017-01-22 19:43:11 -0500 | [diff] [blame] | 185 | select BOARD_LATE_INIT |
Marek Vasut | ba2ade9 | 2015-12-01 18:09:52 +0100 | [diff] [blame] | 186 | select TARGET_SOCFPGA_CYCLONE5 |
| 187 | |
Marek Vasut | 2e717ec | 2016-06-08 02:57:05 +0200 | [diff] [blame] | 188 | config TARGET_SOCFPGA_SR1500 |
| 189 | bool "SR1500 (Cyclone V)" |
| 190 | select TARGET_SOCFPGA_CYCLONE5 |
| 191 | |
Ley Foon Tan | 9c407b5 | 2018-05-24 00:17:32 +0800 | [diff] [blame] | 192 | config TARGET_SOCFPGA_STRATIX10_SOCDK |
| 193 | bool "Intel SOCFPGA SoCDK (Stratix 10)" |
| 194 | select TARGET_SOCFPGA_STRATIX10 |
| 195 | |
Dinh Nguyen | c3364da | 2015-09-01 17:41:52 -0500 | [diff] [blame] | 196 | config TARGET_SOCFPGA_TERASIC_DE0_NANO |
| 197 | bool "Terasic DE0-Nano-Atlas (Cyclone V)" |
| 198 | select TARGET_SOCFPGA_CYCLONE5 |
| 199 | |
Dalon Westergreen | 7a0fe0d | 2017-04-18 08:11:16 -0700 | [diff] [blame] | 200 | config TARGET_SOCFPGA_TERASIC_DE10_NANO |
| 201 | bool "Terasic DE10-Nano (Cyclone V)" |
| 202 | select TARGET_SOCFPGA_CYCLONE5 |
| 203 | |
Humberto Naves | a563e2e | 2022-05-22 21:54:57 -0400 | [diff] [blame] | 204 | config TARGET_SOCFPGA_TERASIC_DE10_STANDARD |
| 205 | bool "Terasic DE10-Standard (Cyclone V)" |
| 206 | select TARGET_SOCFPGA_CYCLONE5 |
| 207 | |
Anatolij Gustschin | 705bf37 | 2016-11-14 16:07:10 +0100 | [diff] [blame] | 208 | config TARGET_SOCFPGA_TERASIC_DE1_SOC |
| 209 | bool "Terasic DE1-SoC (Cyclone V)" |
| 210 | select TARGET_SOCFPGA_CYCLONE5 |
| 211 | |
Marek Vasut | b415bad | 2015-06-21 17:28:53 +0200 | [diff] [blame] | 212 | config TARGET_SOCFPGA_TERASIC_SOCKIT |
| 213 | bool "Terasic SoCkit (Cyclone V)" |
| 214 | select TARGET_SOCFPGA_CYCLONE5 |
| 215 | |
Masahiro Yamada | 144a3e0 | 2015-04-21 20:38:20 +0900 | [diff] [blame] | 216 | endchoice |
| 217 | |
| 218 | config SYS_BOARD |
Jit Loon Lim | 977071e | 2024-03-12 22:01:03 +0800 | [diff] [blame] | 219 | default "agilex5-socdk" if TARGET_SOCFPGA_AGILEX5_SOCDK |
Ley Foon Tan | 461d298 | 2019-11-27 15:55:32 +0800 | [diff] [blame] | 220 | default "agilex-socdk" if TARGET_SOCFPGA_AGILEX_SOCDK |
Marek Vasut | 3f4c561 | 2015-08-10 21:24:53 +0200 | [diff] [blame] | 221 | default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK |
Ley Foon Tan | 5b7cea6 | 2017-04-26 02:44:48 +0800 | [diff] [blame] | 222 | default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK |
Paweł Anikiel | 5ee903d | 2022-06-17 12:47:20 +0200 | [diff] [blame] | 223 | default "chameleonv3" if TARGET_SOCFPGA_CHAMELEONV3 |
Marek Vasut | 3f4c561 | 2015-08-10 21:24:53 +0200 | [diff] [blame] | 224 | default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK |
Marek Vasut | b06dad2 | 2018-02-24 23:34:00 +0100 | [diff] [blame] | 225 | default "dbm-soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1 |
Dinh Nguyen | c3364da | 2015-09-01 17:41:52 -0500 | [diff] [blame] | 226 | default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO |
Anatolij Gustschin | 705bf37 | 2016-11-14 16:07:10 +0100 | [diff] [blame] | 227 | default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC |
Dalon Westergreen | 7a0fe0d | 2017-04-18 08:11:16 -0700 | [diff] [blame] | 228 | default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO |
Humberto Naves | a563e2e | 2022-05-22 21:54:57 -0400 | [diff] [blame] | 229 | default "de10-standard" if TARGET_SOCFPGA_TERASIC_DE10_STANDARD |
Pavel Machek | 9802e87 | 2016-06-07 12:37:23 +0200 | [diff] [blame] | 230 | default "is1" if TARGET_SOCFPGA_IS1 |
Wolfgang Grandegger | 7789aab2 | 2019-05-12 19:25:18 +0200 | [diff] [blame] | 231 | default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK |
Siew Chin Lim | 988bfe4 | 2021-08-10 11:26:42 +0800 | [diff] [blame] | 232 | default "n5x-socdk" if TARGET_SOCFPGA_N5X_SOCDK |
Holger Brunck | ddef889 | 2020-02-19 19:55:14 +0100 | [diff] [blame] | 233 | default "secu1" if TARGET_SOCFPGA_ARRIA5_SECU1 |
Marek Vasut | b415bad | 2015-06-21 17:28:53 +0200 | [diff] [blame] | 234 | default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT |
Marek Vasut | 567356a | 2015-11-23 17:06:27 +0100 | [diff] [blame] | 235 | default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES |
Stefan Roese | bf5ed2e | 2015-11-18 11:06:09 +0100 | [diff] [blame] | 236 | default "sr1500" if TARGET_SOCFPGA_SR1500 |
Ley Foon Tan | 9c407b5 | 2018-05-24 00:17:32 +0800 | [diff] [blame] | 237 | default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK |
Marek Vasut | 13da18c | 2019-06-27 00:19:31 +0200 | [diff] [blame] | 238 | default "vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA |
Masahiro Yamada | 144a3e0 | 2015-04-21 20:38:20 +0900 | [diff] [blame] | 239 | |
| 240 | config SYS_VENDOR |
Jit Loon Lim | 977071e | 2024-03-12 22:01:03 +0800 | [diff] [blame] | 241 | default "intel" if TARGET_SOCFPGA_AGILEX5_SOCDK |
Ley Foon Tan | 461d298 | 2019-11-27 15:55:32 +0800 | [diff] [blame] | 242 | default "intel" if TARGET_SOCFPGA_AGILEX_SOCDK |
Siew Chin Lim | 988bfe4 | 2021-08-10 11:26:42 +0800 | [diff] [blame] | 243 | default "intel" if TARGET_SOCFPGA_N5X_SOCDK |
Marek Vasut | 822e795 | 2015-08-02 21:57:57 +0200 | [diff] [blame] | 244 | default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK |
Ley Foon Tan | 5b7cea6 | 2017-04-26 02:44:48 +0800 | [diff] [blame] | 245 | default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK |
Marek Vasut | 822e795 | 2015-08-02 21:57:57 +0200 | [diff] [blame] | 246 | default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK |
Ley Foon Tan | 9c407b5 | 2018-05-24 00:17:32 +0800 | [diff] [blame] | 247 | default "altera" if TARGET_SOCFPGA_STRATIX10_SOCDK |
Wolfgang Grandegger | 7789aab2 | 2019-05-12 19:25:18 +0200 | [diff] [blame] | 248 | default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK |
Marek Vasut | b06dad2 | 2018-02-24 23:34:00 +0100 | [diff] [blame] | 249 | default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1 |
Marek Vasut | 567356a | 2015-11-23 17:06:27 +0100 | [diff] [blame] | 250 | default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES |
Paweł Anikiel | 5ee903d | 2022-06-17 12:47:20 +0200 | [diff] [blame] | 251 | default "google" if TARGET_SOCFPGA_CHAMELEONV3 |
Holger Brunck | ddef889 | 2020-02-19 19:55:14 +0100 | [diff] [blame] | 252 | default "keymile" if TARGET_SOCFPGA_ARRIA5_SECU1 |
Marek Vasut | 13da18c | 2019-06-27 00:19:31 +0200 | [diff] [blame] | 253 | default "softing" if TARGET_SOCFPGA_SOFTING_VINING_FPGA |
Dinh Nguyen | c3364da | 2015-09-01 17:41:52 -0500 | [diff] [blame] | 254 | default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO |
Anatolij Gustschin | 705bf37 | 2016-11-14 16:07:10 +0100 | [diff] [blame] | 255 | default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC |
Dalon Westergreen | 7a0fe0d | 2017-04-18 08:11:16 -0700 | [diff] [blame] | 256 | default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO |
Humberto Naves | a563e2e | 2022-05-22 21:54:57 -0400 | [diff] [blame] | 257 | default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_STANDARD |
Marek Vasut | b415bad | 2015-06-21 17:28:53 +0200 | [diff] [blame] | 258 | default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT |
Masahiro Yamada | 144a3e0 | 2015-04-21 20:38:20 +0900 | [diff] [blame] | 259 | |
| 260 | config SYS_SOC |
| 261 | default "socfpga" |
| 262 | |
| 263 | config SYS_CONFIG_NAME |
Jit Loon Lim | 977071e | 2024-03-12 22:01:03 +0800 | [diff] [blame] | 264 | default "socfpga_agilex5_socdk" if TARGET_SOCFPGA_AGILEX5_SOCDK |
Ley Foon Tan | 461d298 | 2019-11-27 15:55:32 +0800 | [diff] [blame] | 265 | default "socfpga_agilex_socdk" if TARGET_SOCFPGA_AGILEX_SOCDK |
Holger Brunck | ddef889 | 2020-02-19 19:55:14 +0100 | [diff] [blame] | 266 | default "socfpga_arria5_secu1" if TARGET_SOCFPGA_ARRIA5_SECU1 |
Dinh Nguyen | 16f6ffd | 2015-09-22 17:01:32 -0500 | [diff] [blame] | 267 | default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK |
Ley Foon Tan | 5b7cea6 | 2017-04-26 02:44:48 +0800 | [diff] [blame] | 268 | default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK |
Paweł Anikiel | 5ee903d | 2022-06-17 12:47:20 +0200 | [diff] [blame] | 269 | default "socfpga_chameleonv3" if TARGET_SOCFPGA_CHAMELEONV3 |
Dinh Nguyen | 16f6ffd | 2015-09-22 17:01:32 -0500 | [diff] [blame] | 270 | default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK |
Marek Vasut | b06dad2 | 2018-02-24 23:34:00 +0100 | [diff] [blame] | 271 | default "socfpga_dbm_soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1 |
Dinh Nguyen | c3364da | 2015-09-01 17:41:52 -0500 | [diff] [blame] | 272 | default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO |
Anatolij Gustschin | 705bf37 | 2016-11-14 16:07:10 +0100 | [diff] [blame] | 273 | default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC |
Dalon Westergreen | 7a0fe0d | 2017-04-18 08:11:16 -0700 | [diff] [blame] | 274 | default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO |
Humberto Naves | a563e2e | 2022-05-22 21:54:57 -0400 | [diff] [blame] | 275 | default "socfpga_de10_standard" if TARGET_SOCFPGA_TERASIC_DE10_STANDARD |
Pavel Machek | 9802e87 | 2016-06-07 12:37:23 +0200 | [diff] [blame] | 276 | default "socfpga_is1" if TARGET_SOCFPGA_IS1 |
Wolfgang Grandegger | 7789aab2 | 2019-05-12 19:25:18 +0200 | [diff] [blame] | 277 | default "socfpga_mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK |
Siew Chin Lim | 988bfe4 | 2021-08-10 11:26:42 +0800 | [diff] [blame] | 278 | default "socfpga_n5x_socdk" if TARGET_SOCFPGA_N5X_SOCDK |
Marek Vasut | b415bad | 2015-06-21 17:28:53 +0200 | [diff] [blame] | 279 | default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT |
Marek Vasut | 567356a | 2015-11-23 17:06:27 +0100 | [diff] [blame] | 280 | default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES |
Stefan Roese | bf5ed2e | 2015-11-18 11:06:09 +0100 | [diff] [blame] | 281 | default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500 |
Ley Foon Tan | 9c407b5 | 2018-05-24 00:17:32 +0800 | [diff] [blame] | 282 | default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK |
Marek Vasut | 13da18c | 2019-06-27 00:19:31 +0200 | [diff] [blame] | 283 | default "socfpga_vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA |
Masahiro Yamada | 144a3e0 | 2015-04-21 20:38:20 +0900 | [diff] [blame] | 284 | |
Masahiro Yamada | 144a3e0 | 2015-04-21 20:38:20 +0900 | [diff] [blame] | 285 | endif |