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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Antonio Nino Diaz0e402d32019-01-30 16:01:49 +00002 * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00007#include <platform_def.h>
8
Achin Gupta4f6ad662013-10-25 09:08:21 +01009#include <arch.h>
Dan Handley714a0d22014-04-09 13:13:04 +010010#include <asm_macros.S>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011#include <bl31/ea_handle.h>
12#include <bl31/interrupt_mgmt.h>
13#include <common/runtime_svc.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010014#include <context.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000015#include <lib/el3_runtime/cpu_data.h>
16#include <lib/smccc.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010017
18 .globl runtime_exceptions
Achin Gupta4f6ad662013-10-25 09:08:21 +010019
Dimitris Papastamos446f7f12017-11-30 14:53:53 +000020 .globl sync_exception_sp_el0
21 .globl irq_sp_el0
22 .globl fiq_sp_el0
23 .globl serror_sp_el0
24
25 .globl sync_exception_sp_elx
26 .globl irq_sp_elx
27 .globl fiq_sp_elx
28 .globl serror_sp_elx
29
30 .globl sync_exception_aarch64
31 .globl irq_aarch64
32 .globl fiq_aarch64
33 .globl serror_aarch64
34
35 .globl sync_exception_aarch32
36 .globl irq_aarch32
37 .globl fiq_aarch32
38 .globl serror_aarch32
39
Jeenu Viswambharan96c7df02017-11-30 12:54:15 +000040 /*
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +010041 * Macro that prepares entry to EL3 upon taking an exception.
42 *
43 * With RAS_EXTENSION, this macro synchronizes pending errors with an ESB
44 * instruction. When an error is thus synchronized, the handling is
45 * delegated to platform EA handler.
46 *
47 * Without RAS_EXTENSION, this macro just saves x30, and unmasks
48 * Asynchronous External Aborts.
49 */
50 .macro check_and_unmask_ea
51#if RAS_EXTENSION
52 /* Synchronize pending External Aborts */
53 esb
54
55 /* Unmask the SError interrupt */
56 msr daifclr, #DAIF_ABT_BIT
57
58 /*
59 * Explicitly save x30 so as to free up a register and to enable
60 * branching
61 */
62 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
63
64 /* Check for SErrors synchronized by the ESB instruction */
65 mrs x30, DISR_EL1
66 tbz x30, #DISR_A_BIT, 1f
67
68 /* Save GP registers and restore them afterwards */
69 bl save_gp_registers
Jeenu Viswambharane86a2472018-07-05 15:24:45 +010070 bl handle_lower_el_ea_esb
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +010071 bl restore_gp_registers
72
731:
74#else
75 /* Unmask the SError interrupt */
76 msr daifclr, #DAIF_ABT_BIT
77
78 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
79#endif
80 .endm
81
Douglas Raillard0980eed2016-11-09 17:48:27 +000082 /* ---------------------------------------------------------------------
83 * This macro handles Synchronous exceptions.
84 * Only SMC exceptions are supported.
85 * ---------------------------------------------------------------------
Achin Gupta9cf2bb72014-05-09 11:07:09 +010086 */
87 .macro handle_sync_exception
dp-arm3cac7862016-09-19 11:18:44 +010088#if ENABLE_RUNTIME_INSTRUMENTATION
dp-arm3cac7862016-09-19 11:18:44 +010089 /*
Douglas Raillard0980eed2016-11-09 17:48:27 +000090 * Read the timestamp value and store it in per-cpu data. The value
91 * will be extracted from per-cpu data by the C level SMC handler and
92 * saved to the PMF timestamp region.
dp-arm3cac7862016-09-19 11:18:44 +010093 */
94 mrs x30, cntpct_el0
95 str x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29]
96 mrs x29, tpidr_el3
97 str x30, [x29, #CPU_DATA_PMF_TS0_OFFSET]
98 ldr x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29]
99#endif
100
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100101 mrs x30, esr_el3
102 ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH
103
Douglas Raillard0980eed2016-11-09 17:48:27 +0000104 /* Handle SMC exceptions separately from other synchronous exceptions */
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100105 cmp x30, #EC_AARCH32_SMC
106 b.eq smc_handler32
107
108 cmp x30, #EC_AARCH64_SMC
109 b.eq smc_handler64
110
Jeenu Viswambharane86a2472018-07-05 15:24:45 +0100111 /* Synchronous exceptions other than the above are assumed to be EA */
Julius Werner67ebde72017-07-27 14:59:34 -0700112 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
Jeenu Viswambharane86a2472018-07-05 15:24:45 +0100113 b enter_lower_el_sync_ea
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100114 .endm
115
116
Douglas Raillard0980eed2016-11-09 17:48:27 +0000117 /* ---------------------------------------------------------------------
118 * This macro handles FIQ or IRQ interrupts i.e. EL3, S-EL1 and NS
119 * interrupts.
120 * ---------------------------------------------------------------------
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100121 */
122 .macro handle_interrupt_exception label
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000123
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100124 bl save_gp_registers
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000125
Antonio Nino Diaz25cda672019-02-19 11:53:51 +0000126 /* Save ARMv8.3-PAuth registers and load firmware key */
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000127#if CTX_INCLUDE_PAUTH_REGS
128 bl pauth_context_save
129#endif
Antonio Nino Diaz25cda672019-02-19 11:53:51 +0000130#if ENABLE_PAUTH
131 bl pauth_load_bl_apiakey
132#endif
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000133
Douglas Raillard0980eed2016-11-09 17:48:27 +0000134 /* Save the EL3 system registers needed to return from this exception */
Achin Gupta979992e2015-05-13 17:57:18 +0100135 mrs x0, spsr_el3
136 mrs x1, elr_el3
137 stp x0, x1, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
138
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100139 /* Switch to the runtime stack i.e. SP_EL0 */
140 ldr x2, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
141 mov x20, sp
142 msr spsel, #0
143 mov sp, x2
144
145 /*
Douglas Raillard0980eed2016-11-09 17:48:27 +0000146 * Find out whether this is a valid interrupt type.
147 * If the interrupt controller reports a spurious interrupt then return
148 * to where we came from.
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100149 */
Dan Handley701fea72014-05-27 16:17:21 +0100150 bl plat_ic_get_pending_interrupt_type
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100151 cmp x0, #INTR_TYPE_INVAL
152 b.eq interrupt_exit_\label
153
154 /*
Douglas Raillard0980eed2016-11-09 17:48:27 +0000155 * Get the registered handler for this interrupt type.
156 * A NULL return value could be 'cause of the following conditions:
Achin Gupta979992e2015-05-13 17:57:18 +0100157 *
Douglas Raillard0980eed2016-11-09 17:48:27 +0000158 * a. An interrupt of a type was routed correctly but a handler for its
159 * type was not registered.
Achin Gupta979992e2015-05-13 17:57:18 +0100160 *
Douglas Raillard0980eed2016-11-09 17:48:27 +0000161 * b. An interrupt of a type was not routed correctly so a handler for
162 * its type was not registered.
Achin Gupta979992e2015-05-13 17:57:18 +0100163 *
Douglas Raillard0980eed2016-11-09 17:48:27 +0000164 * c. An interrupt of a type was routed correctly to EL3, but was
165 * deasserted before its pending state could be read. Another
166 * interrupt of a different type pended at the same time and its
167 * type was reported as pending instead. However, a handler for this
168 * type was not registered.
Achin Gupta979992e2015-05-13 17:57:18 +0100169 *
Douglas Raillard0980eed2016-11-09 17:48:27 +0000170 * a. and b. can only happen due to a programming error. The
171 * occurrence of c. could be beyond the control of Trusted Firmware.
172 * It makes sense to return from this exception instead of reporting an
173 * error.
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100174 */
175 bl get_interrupt_type_handler
Achin Gupta979992e2015-05-13 17:57:18 +0100176 cbz x0, interrupt_exit_\label
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100177 mov x21, x0
178
179 mov x0, #INTR_ID_UNAVAILABLE
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100180
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100181 /* Set the current security state in the 'flags' parameter */
182 mrs x2, scr_el3
183 ubfx x1, x2, #0, #1
184
185 /* Restore the reference to the 'handle' i.e. SP_EL3 */
186 mov x2, x20
187
Douglas Raillard0980eed2016-11-09 17:48:27 +0000188 /* x3 will point to a cookie (not used now) */
Soby Mathew799f0ab2014-05-27 16:54:31 +0100189 mov x3, xzr
190
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100191 /* Call the interrupt type handler */
192 blr x21
193
194interrupt_exit_\label:
195 /* Return from exception, possibly in a different security state */
196 b el3_exit
197
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100198 .endm
199
200
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100201vector_base runtime_exceptions
202
Douglas Raillard0980eed2016-11-09 17:48:27 +0000203 /* ---------------------------------------------------------------------
204 * Current EL with SP_EL0 : 0x0 - 0x200
205 * ---------------------------------------------------------------------
Achin Gupta4f6ad662013-10-25 09:08:21 +0100206 */
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100207vector_entry sync_exception_sp_el0
Douglas Raillard0980eed2016-11-09 17:48:27 +0000208 /* We don't expect any synchronous exceptions from EL3 */
Julius Werner67ebde72017-07-27 14:59:34 -0700209 b report_unhandled_exception
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100210end_vector_entry sync_exception_sp_el0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100211
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100212vector_entry irq_sp_el0
Douglas Raillard0980eed2016-11-09 17:48:27 +0000213 /*
214 * EL3 code is non-reentrant. Any asynchronous exception is a serious
215 * error. Loop infinitely.
216 */
Julius Werner67ebde72017-07-27 14:59:34 -0700217 b report_unhandled_interrupt
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100218end_vector_entry irq_sp_el0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100219
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100220
221vector_entry fiq_sp_el0
Julius Werner67ebde72017-07-27 14:59:34 -0700222 b report_unhandled_interrupt
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100223end_vector_entry fiq_sp_el0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100224
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100225
226vector_entry serror_sp_el0
Jeenu Viswambharan911fcc92018-07-06 16:50:06 +0100227 no_ret plat_handle_el3_ea
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100228end_vector_entry serror_sp_el0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100229
Douglas Raillard0980eed2016-11-09 17:48:27 +0000230 /* ---------------------------------------------------------------------
231 * Current EL with SP_ELx: 0x200 - 0x400
232 * ---------------------------------------------------------------------
Achin Gupta4f6ad662013-10-25 09:08:21 +0100233 */
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100234vector_entry sync_exception_sp_elx
Douglas Raillard0980eed2016-11-09 17:48:27 +0000235 /*
236 * This exception will trigger if anything went wrong during a previous
237 * exception entry or exit or while handling an earlier unexpected
238 * synchronous exception. There is a high probability that SP_EL3 is
239 * corrupted.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000240 */
Julius Werner67ebde72017-07-27 14:59:34 -0700241 b report_unhandled_exception
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100242end_vector_entry sync_exception_sp_elx
Achin Gupta4f6ad662013-10-25 09:08:21 +0100243
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100244vector_entry irq_sp_elx
Julius Werner67ebde72017-07-27 14:59:34 -0700245 b report_unhandled_interrupt
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100246end_vector_entry irq_sp_elx
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000247
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100248vector_entry fiq_sp_elx
Julius Werner67ebde72017-07-27 14:59:34 -0700249 b report_unhandled_interrupt
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100250end_vector_entry fiq_sp_elx
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000251
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100252vector_entry serror_sp_elx
Jeenu Viswambharan911fcc92018-07-06 16:50:06 +0100253 no_ret plat_handle_el3_ea
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100254end_vector_entry serror_sp_elx
Achin Gupta4f6ad662013-10-25 09:08:21 +0100255
Douglas Raillard0980eed2016-11-09 17:48:27 +0000256 /* ---------------------------------------------------------------------
Sandrine Bailleux046cd3f2014-08-06 11:27:23 +0100257 * Lower EL using AArch64 : 0x400 - 0x600
Douglas Raillard0980eed2016-11-09 17:48:27 +0000258 * ---------------------------------------------------------------------
Achin Gupta4f6ad662013-10-25 09:08:21 +0100259 */
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100260vector_entry sync_exception_aarch64
Douglas Raillard0980eed2016-11-09 17:48:27 +0000261 /*
262 * This exception vector will be the entry point for SMCs and traps
263 * that are unhandled at lower ELs most commonly. SP_EL3 should point
264 * to a valid cpu context where the general purpose and system register
265 * state can be saved.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000266 */
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100267 check_and_unmask_ea
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000268 handle_sync_exception
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100269end_vector_entry sync_exception_aarch64
Achin Gupta4f6ad662013-10-25 09:08:21 +0100270
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100271vector_entry irq_aarch64
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100272 check_and_unmask_ea
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100273 handle_interrupt_exception irq_aarch64
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100274end_vector_entry irq_aarch64
Achin Gupta4f6ad662013-10-25 09:08:21 +0100275
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100276vector_entry fiq_aarch64
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100277 check_and_unmask_ea
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100278 handle_interrupt_exception fiq_aarch64
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100279end_vector_entry fiq_aarch64
Achin Gupta4f6ad662013-10-25 09:08:21 +0100280
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100281vector_entry serror_aarch64
Jeenu Viswambharan96c7df02017-11-30 12:54:15 +0000282 msr daifclr, #DAIF_ABT_BIT
Jeenu Viswambharane86a2472018-07-05 15:24:45 +0100283 b enter_lower_el_async_ea
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100284end_vector_entry serror_aarch64
Achin Gupta4f6ad662013-10-25 09:08:21 +0100285
Douglas Raillard0980eed2016-11-09 17:48:27 +0000286 /* ---------------------------------------------------------------------
Sandrine Bailleux046cd3f2014-08-06 11:27:23 +0100287 * Lower EL using AArch32 : 0x600 - 0x800
Douglas Raillard0980eed2016-11-09 17:48:27 +0000288 * ---------------------------------------------------------------------
Achin Gupta4f6ad662013-10-25 09:08:21 +0100289 */
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100290vector_entry sync_exception_aarch32
Douglas Raillard0980eed2016-11-09 17:48:27 +0000291 /*
292 * This exception vector will be the entry point for SMCs and traps
293 * that are unhandled at lower ELs most commonly. SP_EL3 should point
294 * to a valid cpu context where the general purpose and system register
295 * state can be saved.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000296 */
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100297 check_and_unmask_ea
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000298 handle_sync_exception
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100299end_vector_entry sync_exception_aarch32
Achin Gupta4f6ad662013-10-25 09:08:21 +0100300
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100301vector_entry irq_aarch32
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100302 check_and_unmask_ea
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100303 handle_interrupt_exception irq_aarch32
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100304end_vector_entry irq_aarch32
Achin Gupta4f6ad662013-10-25 09:08:21 +0100305
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100306vector_entry fiq_aarch32
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100307 check_and_unmask_ea
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100308 handle_interrupt_exception fiq_aarch32
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100309end_vector_entry fiq_aarch32
Achin Gupta4f6ad662013-10-25 09:08:21 +0100310
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100311vector_entry serror_aarch32
Jeenu Viswambharan96c7df02017-11-30 12:54:15 +0000312 msr daifclr, #DAIF_ABT_BIT
Jeenu Viswambharane86a2472018-07-05 15:24:45 +0100313 b enter_lower_el_async_ea
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100314end_vector_entry serror_aarch32
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000315
Antonio Nino Diaz35c8cfc2018-04-23 15:43:29 +0100316 /* ---------------------------------------------------------------------
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000317 * The following code handles secure monitor calls.
Douglas Raillard0980eed2016-11-09 17:48:27 +0000318 * Depending upon the execution state from where the SMC has been
319 * invoked, it frees some general purpose registers to perform the
320 * remaining tasks. They involve finding the runtime service handler
321 * that is the target of the SMC & switching to runtime stacks (SP_EL0)
322 * before calling the handler.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000323 *
Douglas Raillard0980eed2016-11-09 17:48:27 +0000324 * Note that x30 has been explicitly saved and can be used here
325 * ---------------------------------------------------------------------
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000326 */
Andrew Thoelke38bde412014-03-18 13:46:55 +0000327func smc_handler
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000328smc_handler32:
329 /* Check whether aarch32 issued an SMC64 */
330 tbnz x0, #FUNCID_CC_SHIFT, smc_prohibited
331
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000332smc_handler64:
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000333 /* NOTE: The code below must preserve x0-x4 */
334
335 /* Save general purpose registers */
336 bl save_gp_registers
337
Antonio Nino Diaz25cda672019-02-19 11:53:51 +0000338 /* Save ARMv8.3-PAuth registers and load firmware key */
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000339#if CTX_INCLUDE_PAUTH_REGS
340 bl pauth_context_save
341#endif
Antonio Nino Diaz25cda672019-02-19 11:53:51 +0000342#if ENABLE_PAUTH
343 bl pauth_load_bl_apiakey
344#endif
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000345
Douglas Raillard0980eed2016-11-09 17:48:27 +0000346 /*
347 * Populate the parameters for the SMC handler.
348 * We already have x0-x4 in place. x5 will point to a cookie (not used
349 * now). x6 will point to the context structure (SP_EL3) and x7 will
Dimitris Papastamos04159512018-01-22 11:53:04 +0000350 * contain flags we need to pass to the handler.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000351 */
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000352 mov x5, xzr
353 mov x6, sp
354
355 /* Get the unique owning entity number */
356 ubfx x16, x0, #FUNCID_OEN_SHIFT, #FUNCID_OEN_WIDTH
357 ubfx x15, x0, #FUNCID_TYPE_SHIFT, #FUNCID_TYPE_WIDTH
358 orr x16, x16, x15, lsl #FUNCID_OEN_WIDTH
359
Antonio Nino Diaz0e402d32019-01-30 16:01:49 +0000360 /* Load descriptor index from array of indices */
361 adr x14, rt_svc_descs_indices
362 ldrb w15, [x14, x16]
Antonio Nino Diaz35c8cfc2018-04-23 15:43:29 +0100363
Antonio Nino Diaz0e402d32019-01-30 16:01:49 +0000364 /* Any index greater than 127 is invalid. Check bit 7. */
365 tbnz w15, 7, smc_unknown
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000366
367 /*
Antonio Nino Diaz0e402d32019-01-30 16:01:49 +0000368 * Get the descriptor using the index
369 * x11 = (base + off), w15 = index
Antonio Nino Diaz35c8cfc2018-04-23 15:43:29 +0100370 *
Antonio Nino Diaz0e402d32019-01-30 16:01:49 +0000371 * handler = (base + off) + (index << log2(size))
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000372 */
Antonio Nino Diaz0e402d32019-01-30 16:01:49 +0000373 adr x11, (__RT_SVC_DESCS_START__ + RT_SVC_DESC_HANDLE)
374 lsl w10, w15, #RT_SVC_SIZE_LOG2
375 ldr x15, [x11, w10, uxtw]
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000376
Douglas Raillard0980eed2016-11-09 17:48:27 +0000377 /*
Antonio Nino Diaz35c8cfc2018-04-23 15:43:29 +0100378 * Restore the saved C runtime stack value which will become the new
379 * SP_EL0 i.e. EL3 runtime stack. It was saved in the 'cpu_context'
380 * structure prior to the last ERET from EL3.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000381 */
Antonio Nino Diaz35c8cfc2018-04-23 15:43:29 +0100382 ldr x12, [x6, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
383
384 /* Switch to SP_EL0 */
385 msr spsel, #0
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000386
Douglas Raillard0980eed2016-11-09 17:48:27 +0000387 /*
388 * Save the SPSR_EL3, ELR_EL3, & SCR_EL3 in case there is a world
389 * switch during SMC handling.
390 * TODO: Revisit if all system registers can be saved later.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000391 */
392 mrs x16, spsr_el3
393 mrs x17, elr_el3
394 mrs x18, scr_el3
395 stp x16, x17, [x6, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
Achin Guptae1aa5162014-06-26 09:58:52 +0100396 str x18, [x6, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3]
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000397
398 /* Copy SCR_EL3.NS bit to the flag to indicate caller's security */
399 bfi x7, x18, #0, #1
400
401 mov sp, x12
402
Douglas Raillard0980eed2016-11-09 17:48:27 +0000403 /*
404 * Call the Secure Monitor Call handler and then drop directly into
405 * el3_exit() which will program any remaining architectural state
406 * prior to issuing the ERET to the desired lower EL.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000407 */
408#if DEBUG
409 cbz x15, rt_svc_fw_critical_error
410#endif
411 blr x15
412
Yatharth Kochar6c0566c2015-10-02 17:56:48 +0100413 b el3_exit
Achin Gupta4f6ad662013-10-25 09:08:21 +0100414
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000415smc_unknown:
416 /*
Jeenu Viswambharan23d05a82017-11-29 16:59:34 +0000417 * Unknown SMC call. Populate return value with SMC_UNK, restore
418 * GP registers, and return to caller.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000419 */
Antonio Nino Diaze4794b72018-02-14 14:22:29 +0000420 mov x0, #SMC_UNK
Jeenu Viswambharan23d05a82017-11-29 16:59:34 +0000421 str x0, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
Alexei Fedorov3287c4f2019-03-18 15:59:34 +0000422#if CTX_INCLUDE_PAUTH_REGS
423 bl pauth_context_save
424#endif
Jeenu Viswambharan23d05a82017-11-29 16:59:34 +0000425 b restore_gp_registers_eret
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000426
427smc_prohibited:
Soby Mathew6c5192a2014-04-30 15:36:37 +0100428 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
Antonio Nino Diaze4794b72018-02-14 14:22:29 +0000429 mov x0, #SMC_UNK
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000430 eret
431
432rt_svc_fw_critical_error:
Douglas Raillard0980eed2016-11-09 17:48:27 +0000433 /* Switch to SP_ELx */
434 msr spsel, #1
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000435 no_ret report_unhandled_exception
Kévin Petita877c252015-03-24 14:03:57 +0000436endfunc smc_handler