blob: ba8e53b588cbc34f356525e2bc4efd8fa8e98472 [file] [log] [blame]
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +02001/*
Lad Prabhakare1c0f742020-12-21 13:51:58 +00002 * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +02003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00007#include <common/debug.h>
8#include <lib/mmio.h>
9
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +020010#include "cpg_registers.h"
Biju Das623935c2020-12-13 20:36:30 +000011#include "rcar_def.h"
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +020012#include "rcar_private.h"
13
14static void bl2_secure_cpg_init(void);
15
Lad Prabhakare1c0f742020-12-21 13:51:58 +000016#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_H3) || \
17 (RCAR_LSI == RCAR_H3N) || (RCAR_LSI == RZ_G2H)
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +020018static void bl2_realtime_cpg_init_h3(void);
19static void bl2_system_cpg_init_h3(void);
20#endif
21
Biju Das54f6a432020-12-07 16:31:01 +000022#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3) || (RCAR_LSI == RZ_G2M)
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +020023static void bl2_realtime_cpg_init_m3(void);
24static void bl2_system_cpg_init_m3(void);
25#endif
26
Lad Prabhakar21d04f02021-03-19 12:01:00 +000027#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N) || (RCAR_LSI == RZ_G2N)
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +020028static void bl2_realtime_cpg_init_m3n(void);
29static void bl2_system_cpg_init_m3n(void);
30#endif
31
Valentine Barshakf2184142018-10-30 02:06:17 +030032#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_V3M)
33static void bl2_realtime_cpg_init_v3m(void);
34static void bl2_system_cpg_init_v3m(void);
35#endif
36
Lad Prabhakarea647342021-03-19 12:14:01 +000037#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RZ_G2E)
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +020038static void bl2_realtime_cpg_init_e3(void);
39static void bl2_system_cpg_init_e3(void);
40#endif
41
Marek Vasut4ae342c2019-01-05 13:56:03 +010042#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_D3)
43static void bl2_realtime_cpg_init_d3(void);
44static void bl2_system_cpg_init_d3(void);
45#endif
46
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +020047typedef struct {
48 uintptr_t adr;
49 uint32_t val;
50} reg_setting_t;
51
52static void bl2_secure_cpg_init(void)
53{
54 uint32_t stop_cr2, reset_cr2;
Marek Vasut4ae342c2019-01-05 13:56:03 +010055 uint32_t stop_cr4, reset_cr4;
56 uint32_t stop_cr5, reset_cr5;
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +020057
Marek Vasut4ae342c2019-01-05 13:56:03 +010058#if (RCAR_LSI == RCAR_D3)
59 reset_cr2 = 0x00000000U;
60 stop_cr2 = 0xFFFFFFFFU;
Lad Prabhakarea647342021-03-19 12:14:01 +000061#elif (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RZ_G2E)
ldts0a596b42018-11-06 10:17:12 +010062 reset_cr2 = 0x10000000U;
63 stop_cr2 = 0xEFFFFFFFU;
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +020064#else
65 reset_cr2 = 0x14000000U;
66 stop_cr2 = 0xEBFFFFFFU;
67#endif
Marek Vasut4ae342c2019-01-05 13:56:03 +010068
69#if (RCAR_LSI == RCAR_D3)
70 reset_cr4 = 0x00000000U;
71 stop_cr4 = 0xFFFFFFFFU;
72 reset_cr5 = 0x00000000U;
73 stop_cr5 = 0xFFFFFFFFU;
74#else
75 reset_cr4 = 0x80000003U;
76 stop_cr4 = 0x7FFFFFFFU;
77 reset_cr5 = 0x40000000U;
78 stop_cr5 = 0xBFFFFFFFU;
79#endif
80
Biju Das623935c2020-12-13 20:36:30 +000081 /* Secure Module Stop Control Registers */
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +020082 cpg_write(SCMSTPCR0, 0xFFFFFFFFU);
83 cpg_write(SCMSTPCR1, 0xFFFFFFFFU);
84 cpg_write(SCMSTPCR2, stop_cr2);
85 cpg_write(SCMSTPCR3, 0xFFFFFFFFU);
Marek Vasut4ae342c2019-01-05 13:56:03 +010086 cpg_write(SCMSTPCR4, stop_cr4);
87 cpg_write(SCMSTPCR5, stop_cr5);
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +020088 cpg_write(SCMSTPCR6, 0xFFFFFFFFU);
89 cpg_write(SCMSTPCR7, 0xFFFFFFFFU);
90 cpg_write(SCMSTPCR8, 0xFFFFFFFFU);
91 cpg_write(SCMSTPCR9, 0xFFFDFFFFU);
92 cpg_write(SCMSTPCR10, 0xFFFFFFFFU);
93 cpg_write(SCMSTPCR11, 0xFFFFFFFFU);
94
Biju Das623935c2020-12-13 20:36:30 +000095 /* Secure Software Reset Access Enable Control Registers */
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +020096 cpg_write(SCSRSTECR0, 0x00000000U);
97 cpg_write(SCSRSTECR1, 0x00000000U);
98 cpg_write(SCSRSTECR2, reset_cr2);
99 cpg_write(SCSRSTECR3, 0x00000000U);
Marek Vasut4ae342c2019-01-05 13:56:03 +0100100 cpg_write(SCSRSTECR4, reset_cr4);
101 cpg_write(SCSRSTECR5, reset_cr5);
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200102 cpg_write(SCSRSTECR6, 0x00000000U);
103 cpg_write(SCSRSTECR7, 0x00000000U);
104 cpg_write(SCSRSTECR8, 0x00000000U);
105 cpg_write(SCSRSTECR9, 0x00020000U);
106 cpg_write(SCSRSTECR10, 0x00000000U);
107 cpg_write(SCSRSTECR11, 0x00000000U);
108}
109
Lad Prabhakare1c0f742020-12-21 13:51:58 +0000110#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_H3) || \
111 (RCAR_LSI == RCAR_H3N) || (RCAR_LSI == RZ_G2H)
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200112static void bl2_realtime_cpg_init_h3(void)
113{
Marek Vasut9cadc782019-08-06 19:13:22 +0200114 uint32_t cut = mmio_read_32(RCAR_PRR) & PRR_CUT_MASK;
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200115 uint32_t cr0, cr8;
116
Marek Vasut9cadc782019-08-06 19:13:22 +0200117 cr0 = (cut == PRR_PRODUCT_10 || cut == PRR_PRODUCT_11) ?
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200118 0x00200000U : 0x00210000U;
Marek Vasut9cadc782019-08-06 19:13:22 +0200119 cr8 = (cut == PRR_PRODUCT_10 || cut == PRR_PRODUCT_11) ?
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200120 0x01F1FFF4U : 0x01F1FFF7U;
121
122 cpg_write(RMSTPCR0, cr0);
123 cpg_write(RMSTPCR1, 0xFFFFFFFFU);
124 cpg_write(RMSTPCR2, 0x040E0FDCU);
125 cpg_write(RMSTPCR3, 0xFFFFFFDFU);
126 cpg_write(RMSTPCR4, 0x80000004U);
127 cpg_write(RMSTPCR5, 0xC3FFFFFFU);
128 cpg_write(RMSTPCR6, 0xFFFFFFFFU);
129 cpg_write(RMSTPCR7, 0xFFFFFFFFU);
130 cpg_write(RMSTPCR8, cr8);
131 cpg_write(RMSTPCR9, 0xFFFFFFFEU);
132 cpg_write(RMSTPCR10, 0xFFFEFFE0U);
133 cpg_write(RMSTPCR11, 0x000000B7U);
134}
135
136static void bl2_system_cpg_init_h3(void)
137{
138 /** System Module Stop Control Registers */
139 cpg_write(SMSTPCR0, 0x00210000U);
140 cpg_write(SMSTPCR1, 0xFFFFFFFFU);
141 cpg_write(SMSTPCR2, 0x040E2FDCU);
142 cpg_write(SMSTPCR3, 0xFFFFFBDFU);
143 cpg_write(SMSTPCR4, 0x80000004U);
144 cpg_write(SMSTPCR5, 0xC3FFFFFFU);
145 cpg_write(SMSTPCR6, 0xFFFFFFFFU);
146 cpg_write(SMSTPCR7, 0xFFFFFFFFU);
147 cpg_write(SMSTPCR8, 0x01F1FFF5U);
148 cpg_write(SMSTPCR9, 0xFFFFFFFFU);
149 cpg_write(SMSTPCR10, 0xFFFEFFE0U);
150 cpg_write(SMSTPCR11, 0x000000B7U);
151}
152#endif
153
Biju Das54f6a432020-12-07 16:31:01 +0000154#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3) || (RCAR_LSI == RZ_G2M)
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200155static void bl2_realtime_cpg_init_m3(void)
156{
Biju Das623935c2020-12-13 20:36:30 +0000157 /* Realtime Module Stop Control Registers */
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200158 cpg_write(RMSTPCR0, 0x00200000U);
159 cpg_write(RMSTPCR1, 0xFFFFFFFFU);
160 cpg_write(RMSTPCR2, 0x040E0FDCU);
161 cpg_write(RMSTPCR3, 0xFFFFFFDFU);
162 cpg_write(RMSTPCR4, 0x80000004U);
163 cpg_write(RMSTPCR5, 0xC3FFFFFFU);
164 cpg_write(RMSTPCR6, 0xFFFFFFFFU);
165 cpg_write(RMSTPCR7, 0xFFFFFFFFU);
166 cpg_write(RMSTPCR8, 0x01F1FFF7U);
167 cpg_write(RMSTPCR9, 0xFFFFFFFEU);
168 cpg_write(RMSTPCR10, 0xFFFEFFE0U);
169 cpg_write(RMSTPCR11, 0x000000B7U);
170}
171
172static void bl2_system_cpg_init_m3(void)
173{
Biju Das623935c2020-12-13 20:36:30 +0000174 /* System Module Stop Control Registers */
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200175 cpg_write(SMSTPCR0, 0x00200000U);
176 cpg_write(SMSTPCR1, 0xFFFFFFFFU);
177 cpg_write(SMSTPCR2, 0x040E2FDCU);
178 cpg_write(SMSTPCR3, 0xFFFFFBDFU);
179 cpg_write(SMSTPCR4, 0x80000004U);
180 cpg_write(SMSTPCR5, 0xC3FFFFFFU);
181 cpg_write(SMSTPCR6, 0xFFFFFFFFU);
182 cpg_write(SMSTPCR7, 0xFFFFFFFFU);
183 cpg_write(SMSTPCR8, 0x01F1FFF7U);
184 cpg_write(SMSTPCR9, 0xFFFFFFFFU);
185 cpg_write(SMSTPCR10, 0xFFFEFFE0U);
186 cpg_write(SMSTPCR11, 0x000000B7U);
187}
188#endif
189
Lad Prabhakar21d04f02021-03-19 12:01:00 +0000190#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N) || (RCAR_LSI == RZ_G2N)
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200191static void bl2_realtime_cpg_init_m3n(void)
192{
Biju Das623935c2020-12-13 20:36:30 +0000193 /* Realtime Module Stop Control Registers */
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200194 cpg_write(RMSTPCR0, 0x00210000U);
195 cpg_write(RMSTPCR1, 0xFFFFFFFFU);
196 cpg_write(RMSTPCR2, 0x040E0FDCU);
197 cpg_write(RMSTPCR3, 0xFFFFFFDFU);
198 cpg_write(RMSTPCR4, 0x80000004U);
199 cpg_write(RMSTPCR5, 0xC3FFFFFFU);
200 cpg_write(RMSTPCR6, 0xFFFFFFFFU);
201 cpg_write(RMSTPCR7, 0xFFFFFFFFU);
202 cpg_write(RMSTPCR8, 0x00F1FFF7U);
203 cpg_write(RMSTPCR9, 0xFFFFFFFFU);
204 cpg_write(RMSTPCR10, 0xFFFFFFE0U);
205 cpg_write(RMSTPCR11, 0x000000B7U);
206}
207
208static void bl2_system_cpg_init_m3n(void)
209{
210 /* System Module Stop Control Registers */
211 cpg_write(SMSTPCR0, 0x00210000U);
212 cpg_write(SMSTPCR1, 0xFFFFFFFFU);
213 cpg_write(SMSTPCR2, 0x040E2FDCU);
214 cpg_write(SMSTPCR3, 0xFFFFFBDFU);
215 cpg_write(SMSTPCR4, 0x80000004U);
216 cpg_write(SMSTPCR5, 0xC3FFFFFFU);
217 cpg_write(SMSTPCR6, 0xFFFFFFFFU);
218 cpg_write(SMSTPCR7, 0xFFFFFFFFU);
219 cpg_write(SMSTPCR8, 0x00F1FFF7U);
220 cpg_write(SMSTPCR9, 0xFFFFFFFFU);
221 cpg_write(SMSTPCR10, 0xFFFFFFE0U);
222 cpg_write(SMSTPCR11, 0x000000B7U);
223}
224#endif
225
Valentine Barshakf2184142018-10-30 02:06:17 +0300226#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_V3M)
227static void bl2_realtime_cpg_init_v3m(void)
228{
229 /* Realtime Module Stop Control Registers */
230 cpg_write(RMSTPCR0, 0x00230000U);
231 cpg_write(RMSTPCR1, 0xFFFFFFFFU);
232 cpg_write(RMSTPCR2, 0x14062FD8U);
233 cpg_write(RMSTPCR3, 0xFFFFFFDFU);
234 cpg_write(RMSTPCR4, 0x80000184U);
235 cpg_write(RMSTPCR5, 0x83FFFFFFU);
236 cpg_write(RMSTPCR6, 0xFFFFFFFFU);
237 cpg_write(RMSTPCR7, 0xFFFFFFFFU);
238 cpg_write(RMSTPCR8, 0x7FF3FFF4U);
239 cpg_write(RMSTPCR9, 0xFFFFFFFEU);
240}
241
242static void bl2_system_cpg_init_v3m(void)
243{
244 /* System Module Stop Control Registers */
245 cpg_write(SMSTPCR0, 0x00210000U);
246 cpg_write(SMSTPCR1, 0xFFFFFFFFU);
247 cpg_write(SMSTPCR2, 0x340E2FDCU);
248 cpg_write(SMSTPCR3, 0xFFFFFBDFU);
249 cpg_write(SMSTPCR4, 0x80000004U);
250 cpg_write(SMSTPCR5, 0xC3FFFFFFU);
251 cpg_write(SMSTPCR6, 0xFFFFFFFFU);
252 cpg_write(SMSTPCR7, 0xFFFFFFFFU);
253 cpg_write(SMSTPCR8, 0x01F1FFF5U);
254 cpg_write(SMSTPCR9, 0xFFFFFFFEU);
255}
256#endif
257
Lad Prabhakarea647342021-03-19 12:14:01 +0000258#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RZ_G2E)
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200259static void bl2_realtime_cpg_init_e3(void)
260{
261 /* Realtime Module Stop Control Registers */
262 cpg_write(RMSTPCR0, 0x00210000U);
263 cpg_write(RMSTPCR1, 0xFFFFFFFFU);
264 cpg_write(RMSTPCR2, 0x000E0FDCU);
265 cpg_write(RMSTPCR3, 0xFFFFFFDFU);
266 cpg_write(RMSTPCR4, 0x80000004U);
267 cpg_write(RMSTPCR5, 0xC3FFFFFFU);
268 cpg_write(RMSTPCR6, 0xFFFFFFFFU);
269 cpg_write(RMSTPCR7, 0xFFFFFFFFU);
270 cpg_write(RMSTPCR8, 0x00F1FFF7U);
271 cpg_write(RMSTPCR9, 0xFFFFFFDFU);
272 cpg_write(RMSTPCR10, 0xFFFFFFE8U);
273 cpg_write(RMSTPCR11, 0x000000B7U);
274}
275
276static void bl2_system_cpg_init_e3(void)
277{
278 /* System Module Stop Control Registers */
279 cpg_write(SMSTPCR0, 0x00210000U);
280 cpg_write(SMSTPCR1, 0xFFFFFFFFU);
281 cpg_write(SMSTPCR2, 0x000E2FDCU);
282 cpg_write(SMSTPCR3, 0xFFFFFBDFU);
283 cpg_write(SMSTPCR4, 0x80000004U);
284 cpg_write(SMSTPCR5, 0xC3FFFFFFU);
285 cpg_write(SMSTPCR6, 0xFFFFFFFFU);
286 cpg_write(SMSTPCR7, 0xFFFFFFFFU);
287 cpg_write(SMSTPCR8, 0x00F1FFF7U);
288 cpg_write(SMSTPCR9, 0xFFFFFFDFU);
289 cpg_write(SMSTPCR10, 0xFFFFFFE8U);
290 cpg_write(SMSTPCR11, 0x000000B7U);
291}
292#endif
293
Marek Vasut4ae342c2019-01-05 13:56:03 +0100294#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_D3)
295static void bl2_realtime_cpg_init_d3(void)
296{
297 /* Realtime Module Stop Control Registers */
298 cpg_write(RMSTPCR0, 0x00010000U);
299 cpg_write(RMSTPCR1, 0xFFFFFFFFU);
300 cpg_write(RMSTPCR2, 0x00060FDCU);
301 cpg_write(RMSTPCR3, 0xFFFFFFDFU);
302 cpg_write(RMSTPCR4, 0x80000184U);
303 cpg_write(RMSTPCR5, 0x83FFFFFFU);
304 cpg_write(RMSTPCR6, 0xFFFFFFFFU);
305 cpg_write(RMSTPCR7, 0xFFFFFFFFU);
306 cpg_write(RMSTPCR8, 0x00F1FFF7U);
307 cpg_write(RMSTPCR9, 0xF3F5E016U);
308 cpg_write(RMSTPCR10, 0xFFFEFFE0U);
309 cpg_write(RMSTPCR11, 0x000000B7U);
310}
311
312static void bl2_system_cpg_init_d3(void)
313{
314 /* System Module Stop Control Registers */
315 cpg_write(SMSTPCR0, 0x00010000U);
316 cpg_write(SMSTPCR1, 0xFFFFFFFFU);
317 cpg_write(SMSTPCR2, 0x00060FDCU);
318 cpg_write(SMSTPCR3, 0xFFFFFBDFU);
319 cpg_write(SMSTPCR4, 0x00000084U);
320 cpg_write(SMSTPCR5, 0x83FFFFFFU);
321 cpg_write(SMSTPCR6, 0xFFFFFFFFU);
322 cpg_write(SMSTPCR7, 0xFFFFFFFFU);
323 cpg_write(SMSTPCR8, 0x00F1FFF7U);
324 cpg_write(SMSTPCR9, 0xF3F5E016U);
325 cpg_write(SMSTPCR10, 0xFFFEFFE0U);
326 cpg_write(SMSTPCR11, 0x000000B7U);
327}
328#endif
329
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200330void bl2_cpg_init(void)
331{
332 uint32_t boot_cpu = mmio_read_32(RCAR_MODEMR) & MODEMR_BOOT_CPU_MASK;
333#if RCAR_LSI == RCAR_AUTO
Marek Vasut9cadc782019-08-06 19:13:22 +0200334 uint32_t product = mmio_read_32(RCAR_PRR) & PRR_PRODUCT_MASK;
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200335#endif
336 bl2_secure_cpg_init();
337
338 if (boot_cpu == MODEMR_BOOT_CPU_CA57 ||
339 boot_cpu == MODEMR_BOOT_CPU_CA53) {
340#if RCAR_LSI == RCAR_AUTO
341
342 switch (product) {
Marek Vasut9cadc782019-08-06 19:13:22 +0200343 case PRR_PRODUCT_H3:
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200344 bl2_realtime_cpg_init_h3();
345 break;
Marek Vasut9cadc782019-08-06 19:13:22 +0200346 case PRR_PRODUCT_M3:
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200347 bl2_realtime_cpg_init_m3();
348 break;
Marek Vasut9cadc782019-08-06 19:13:22 +0200349 case PRR_PRODUCT_M3N:
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200350 bl2_realtime_cpg_init_m3n();
351 break;
Marek Vasut9cadc782019-08-06 19:13:22 +0200352 case PRR_PRODUCT_V3M:
Valentine Barshakf2184142018-10-30 02:06:17 +0300353 bl2_realtime_cpg_init_v3m();
354 break;
Marek Vasut9cadc782019-08-06 19:13:22 +0200355 case PRR_PRODUCT_E3:
Marek Vasut2b9b0fc2019-01-05 13:57:16 +0100356 bl2_realtime_cpg_init_e3();
357 break;
Marek Vasut9cadc782019-08-06 19:13:22 +0200358 case PRR_PRODUCT_D3:
Marek Vasut4ae342c2019-01-05 13:56:03 +0100359 bl2_realtime_cpg_init_d3();
360 break;
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200361 default:
362 panic();
363 break;
364 }
Lad Prabhakare1c0f742020-12-21 13:51:58 +0000365#elif (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N) || (RCAR_LSI == RZ_G2H)
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200366 bl2_realtime_cpg_init_h3();
Biju Das54f6a432020-12-07 16:31:01 +0000367#elif (RCAR_LSI == RCAR_M3) || (RCAR_LSI == RZ_G2M)
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200368 bl2_realtime_cpg_init_m3();
Lad Prabhakar21d04f02021-03-19 12:01:00 +0000369#elif RCAR_LSI == RCAR_M3N || (RCAR_LSI == RZ_G2N)
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200370 bl2_realtime_cpg_init_m3n();
Valentine Barshakf2184142018-10-30 02:06:17 +0300371#elif RCAR_LSI == RCAR_V3M
372 bl2_realtime_cpg_init_v3m();
Lad Prabhakarea647342021-03-19 12:14:01 +0000373#elif RCAR_LSI == RCAR_E3 || RCAR_LSI == RZ_G2E
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200374 bl2_realtime_cpg_init_e3();
Marek Vasut4ae342c2019-01-05 13:56:03 +0100375#elif RCAR_LSI == RCAR_D3
376 bl2_realtime_cpg_init_d3();
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200377#else
378#error "Don't have CPG initialize routine(unknown)."
379#endif
380 }
381}
382
383void bl2_system_cpg_init(void)
384{
385#if RCAR_LSI == RCAR_AUTO
Marek Vasut9cadc782019-08-06 19:13:22 +0200386 uint32_t product = mmio_read_32(RCAR_PRR) & PRR_PRODUCT_MASK;
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200387
388 switch (product) {
Marek Vasut9cadc782019-08-06 19:13:22 +0200389 case PRR_PRODUCT_H3:
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200390 bl2_system_cpg_init_h3();
391 break;
Marek Vasut9cadc782019-08-06 19:13:22 +0200392 case PRR_PRODUCT_M3:
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200393 bl2_system_cpg_init_m3();
394 break;
Marek Vasut9cadc782019-08-06 19:13:22 +0200395 case PRR_PRODUCT_M3N:
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200396 bl2_system_cpg_init_m3n();
397 break;
Marek Vasut9cadc782019-08-06 19:13:22 +0200398 case PRR_PRODUCT_V3M:
Valentine Barshakf2184142018-10-30 02:06:17 +0300399 bl2_system_cpg_init_v3m();
400 break;
Marek Vasut9cadc782019-08-06 19:13:22 +0200401 case PRR_PRODUCT_E3:
Marek Vasut2b9b0fc2019-01-05 13:57:16 +0100402 bl2_system_cpg_init_e3();
403 break;
Marek Vasut9cadc782019-08-06 19:13:22 +0200404 case PRR_PRODUCT_D3:
Marek Vasut4ae342c2019-01-05 13:56:03 +0100405 bl2_system_cpg_init_d3();
406 break;
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200407 default:
408 panic();
409 break;
410 }
Lad Prabhakare1c0f742020-12-21 13:51:58 +0000411#elif (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N) || (RCAR_LSI == RZ_G2H)
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200412 bl2_system_cpg_init_h3();
Biju Das54f6a432020-12-07 16:31:01 +0000413#elif (RCAR_LSI == RCAR_M3) || (RCAR_LSI == RZ_G2M)
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200414 bl2_system_cpg_init_m3();
Lad Prabhakar21d04f02021-03-19 12:01:00 +0000415#elif RCAR_LSI == RCAR_M3N || (RCAR_LSI == RZ_G2N)
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200416 bl2_system_cpg_init_m3n();
Valentine Barshakf2184142018-10-30 02:06:17 +0300417#elif RCAR_LSI == RCAR_V3M
418 bl2_system_cpg_init_v3m();
Lad Prabhakarea647342021-03-19 12:14:01 +0000419#elif RCAR_LSI == RCAR_E3 || RCAR_LSI == RZ_G2E
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200420 bl2_system_cpg_init_e3();
Marek Vasut4ae342c2019-01-05 13:56:03 +0100421#elif RCAR_LSI == RCAR_D3
422 bl2_system_cpg_init_d3();
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200423#else
424#error "Don't have CPG initialize routine(unknown)."
425#endif
426}