rcar-gen3: initial commit for the rcar-gen3 boards
Reference code:
==============
rar_gen3: IPL and Secure Monitor Rev1.0.22
https://github.com/renesas-rcar/arm-trusted-firmware [rcar_gen3]
Author: Takuya Sakata <takuya.sakata.wz@bp.renesas.com>
Date: Thu Aug 30 21:26:41 2018 +0900
Update IPL and Secure Monitor Rev1.0.22
General Information:
===================
This port has been tested on the Salvator-X Soc_id r8a7795 revision
ES1.1 (uses an SPD).
Build Tested:
-------------
ATFW_OPT="LSI=H3 RCAR_DRAM_SPLIT=1 RCAR_LOSSY_ENABLE=1"
MBEDTLS_DIR=$mbedtls
$ make clean bl2 bl31 rcar PLAT=rcar ${ATFW_OPT} SPD=opteed
Other dependencies:
------------------
* mbed_tls:
git@github.com:ARMmbed/mbedtls.git [devel]
Merge: 68dbc94 f34a4c1
Author: Simon Butcher <simon.butcher@arm.com>
Date: Thu Aug 30 00:57:28 2018 +0100
* optee_os:
https://github.com/BayLibre/optee_os
Until it gets merged into OP-TEE, the port requires Renesas' Trusted
Environment with a modification to support power management.
Author: Jorge Ramirez-Ortiz <jramirez@baylibre.com>
Date: Thu Aug 30 16:49:49 2018 +0200
plat-rcar: cpu-suspend: handle the power level
Signed-off-by: Jorge Ramirez-Ortiz <jramirez@baylibre.com>
* u-boot:
The port has beent tested using mainline uboot.
Author: Fabio Estevam <festevam@gmail.com>
Date: Tue Sep 4 10:23:12 2018 -0300
*linux:
The port has beent tested using mainline kernel.
Author: Linus Torvalds <torvalds@linux-foundation.org>
Date: Sun Sep 16 11:52:37 2018 -0700
Linux 4.19-rc4
Overview
---------
BOOTROM starts the cpu at EL3; In this port BL2 will therefore be entered
at this exception level (the Renesas' ATF reference tree [1] resets into
EL1 before entering BL2 - see its bl2.ld.S)
BL2 initializes DDR (and i2c to talk to the PMIC on some platforms)
before determining the boot reason (cold or warm).
During suspend all CPUs are switched off and the DDR is put in
backup mode (some kind of self-refresh mode). This means that BL2 is
always entered in a cold boot scenario.
Once BL2 boots, it determines the boot reason, writes it to shared
memory (BOOT_KIND_BASE) together with the BL31 parameters
(PARAMS_BASE) and jumps to BL31.
To all effects, BL31 is as if it is being entered in reset mode since
it still needs to initialize the rest of the cores; this is the reason
behind using direct shared memory access to BOOT_KIND_BASE and
PARAMS_BASE instead of using registers to get to those locations (see
el3_common_macros.S and bl31_entrypoint.S for the RESET_TO_BL31 use
case).
Depending on the boot reason BL31 initializes the rest of the cores:
in case of suspend, it uses a MBOX memory region to recover the
program counters.
[1] https://github.com/renesas-rcar/arm-trusted-firmware
Tests
-----
* cpuidle
-------
enable kernel's cpuidle arm_idle driver and boot
* system suspend
--------------
$ cat suspend.sh
#!/bin/bash
i2cset -f -y 7 0x30 0x20 0x0F
read -p "Switch off SW23 and press return " foo
echo mem > /sys/power/state
* cpu hotplug:
------------
$ cat offline.sh
#!/bin/bash
nbr=$1
echo 0 > /sys/devices/system/cpu/cpu$nbr/online
printf "ONLINE: " && cat /sys/devices/system/cpu/online
printf "OFFLINE: " && cat /sys/devices/system/cpu/offline
$ cat online.sh
#!/bin/bash
nbr=$1
echo 1 > /sys/devices/system/cpu/cpu$nbr/online
printf "ONLINE: " && cat /sys/devices/system/cpu/online
printf "OFFLINE: " && cat /sys/devices/system/cpu/offline
Signed-off-by: ldts <jramirez@baylibre.com>
diff --git a/plat/renesas/rcar/bl2_cpg_init.c b/plat/renesas/rcar/bl2_cpg_init.c
new file mode 100644
index 0000000..eb533ce
--- /dev/null
+++ b/plat/renesas/rcar/bl2_cpg_init.c
@@ -0,0 +1,300 @@
+/*
+ * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <debug.h>
+#include <mmio.h>
+#include "rcar_def.h"
+#include "cpg_registers.h"
+#include "rcar_private.h"
+
+static void bl2_secure_cpg_init(void);
+
+#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N)
+static void bl2_realtime_cpg_init_h3(void);
+static void bl2_system_cpg_init_h3(void);
+#endif
+
+#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3)
+static void bl2_realtime_cpg_init_m3(void);
+static void bl2_system_cpg_init_m3(void);
+#endif
+
+#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N)
+static void bl2_realtime_cpg_init_m3n(void);
+static void bl2_system_cpg_init_m3n(void);
+#endif
+
+#if (RCAR_LSI == RCAR_E3)
+static void bl2_realtime_cpg_init_e3(void);
+static void bl2_system_cpg_init_e3(void);
+#endif
+
+typedef struct {
+ uintptr_t adr;
+ uint32_t val;
+} reg_setting_t;
+
+static void bl2_secure_cpg_init(void)
+{
+ uint32_t stop_cr2, reset_cr2;
+
+#if (RCAR_LSI == RCAR_E3)
+ reset_cr2 = 0x10000000U stop_cr2 = 0xEFFFFFFFU;
+#else
+ reset_cr2 = 0x14000000U;
+ stop_cr2 = 0xEBFFFFFFU;
+#endif
+ /** Secure Module Stop Control Registers */
+ cpg_write(SCMSTPCR0, 0xFFFFFFFFU);
+ cpg_write(SCMSTPCR1, 0xFFFFFFFFU);
+ cpg_write(SCMSTPCR2, stop_cr2);
+ cpg_write(SCMSTPCR3, 0xFFFFFFFFU);
+ cpg_write(SCMSTPCR4, 0x7FFFFFFFU);
+ cpg_write(SCMSTPCR5, 0xBFFFFFFFU);
+ cpg_write(SCMSTPCR6, 0xFFFFFFFFU);
+ cpg_write(SCMSTPCR7, 0xFFFFFFFFU);
+ cpg_write(SCMSTPCR8, 0xFFFFFFFFU);
+ cpg_write(SCMSTPCR9, 0xFFFDFFFFU);
+ cpg_write(SCMSTPCR10, 0xFFFFFFFFU);
+ cpg_write(SCMSTPCR11, 0xFFFFFFFFU);
+
+ /** Secure Software Reset Access Enable Control Registers */
+ cpg_write(SCSRSTECR0, 0x00000000U);
+ cpg_write(SCSRSTECR1, 0x00000000U);
+ cpg_write(SCSRSTECR2, reset_cr2);
+ cpg_write(SCSRSTECR3, 0x00000000U);
+ cpg_write(SCSRSTECR4, 0x80000003U);
+ cpg_write(SCSRSTECR5, 0x40000000U);
+ cpg_write(SCSRSTECR6, 0x00000000U);
+ cpg_write(SCSRSTECR7, 0x00000000U);
+ cpg_write(SCSRSTECR8, 0x00000000U);
+ cpg_write(SCSRSTECR9, 0x00020000U);
+ cpg_write(SCSRSTECR10, 0x00000000U);
+ cpg_write(SCSRSTECR11, 0x00000000U);
+}
+
+#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N)
+static void bl2_realtime_cpg_init_h3(void)
+{
+ uint32_t cut = mmio_read_32(RCAR_PRR) & RCAR_CUT_MASK;
+ uint32_t cr0, cr8;
+
+ cr0 = (cut == RCAR_CUT_VER10 || cut == RCAR_CUT_VER11) ?
+ 0x00200000U : 0x00210000U;
+ cr8 = (cut == RCAR_CUT_VER10 || cut == RCAR_CUT_VER11) ?
+ 0x01F1FFF4U : 0x01F1FFF7U;
+
+ cpg_write(RMSTPCR0, cr0);
+ cpg_write(RMSTPCR1, 0xFFFFFFFFU);
+ cpg_write(RMSTPCR2, 0x040E0FDCU);
+ cpg_write(RMSTPCR3, 0xFFFFFFDFU);
+ cpg_write(RMSTPCR4, 0x80000004U);
+ cpg_write(RMSTPCR5, 0xC3FFFFFFU);
+ cpg_write(RMSTPCR6, 0xFFFFFFFFU);
+ cpg_write(RMSTPCR7, 0xFFFFFFFFU);
+ cpg_write(RMSTPCR8, cr8);
+ cpg_write(RMSTPCR9, 0xFFFFFFFEU);
+ cpg_write(RMSTPCR10, 0xFFFEFFE0U);
+ cpg_write(RMSTPCR11, 0x000000B7U);
+}
+
+static void bl2_system_cpg_init_h3(void)
+{
+ /** System Module Stop Control Registers */
+ cpg_write(SMSTPCR0, 0x00210000U);
+ cpg_write(SMSTPCR1, 0xFFFFFFFFU);
+ cpg_write(SMSTPCR2, 0x040E2FDCU);
+ cpg_write(SMSTPCR3, 0xFFFFFBDFU);
+ cpg_write(SMSTPCR4, 0x80000004U);
+ cpg_write(SMSTPCR5, 0xC3FFFFFFU);
+ cpg_write(SMSTPCR6, 0xFFFFFFFFU);
+ cpg_write(SMSTPCR7, 0xFFFFFFFFU);
+ cpg_write(SMSTPCR8, 0x01F1FFF5U);
+ cpg_write(SMSTPCR9, 0xFFFFFFFFU);
+ cpg_write(SMSTPCR10, 0xFFFEFFE0U);
+ cpg_write(SMSTPCR11, 0x000000B7U);
+}
+#endif
+
+#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3)
+static void bl2_realtime_cpg_init_m3(void)
+{
+ /** Realtime Module Stop Control Registers */
+ cpg_write(RMSTPCR0, 0x00200000U);
+ cpg_write(RMSTPCR1, 0xFFFFFFFFU);
+ cpg_write(RMSTPCR2, 0x040E0FDCU);
+ cpg_write(RMSTPCR3, 0xFFFFFFDFU);
+ cpg_write(RMSTPCR4, 0x80000004U);
+ cpg_write(RMSTPCR5, 0xC3FFFFFFU);
+ cpg_write(RMSTPCR6, 0xFFFFFFFFU);
+ cpg_write(RMSTPCR7, 0xFFFFFFFFU);
+ cpg_write(RMSTPCR8, 0x01F1FFF7U);
+ cpg_write(RMSTPCR9, 0xFFFFFFFEU);
+ cpg_write(RMSTPCR10, 0xFFFEFFE0U);
+ cpg_write(RMSTPCR11, 0x000000B7U);
+}
+
+static void bl2_system_cpg_init_m3(void)
+{
+ /** System Module Stop Control Registers */
+ cpg_write(SMSTPCR0, 0x00200000U);
+ cpg_write(SMSTPCR1, 0xFFFFFFFFU);
+ cpg_write(SMSTPCR2, 0x040E2FDCU);
+ cpg_write(SMSTPCR3, 0xFFFFFBDFU);
+ cpg_write(SMSTPCR4, 0x80000004U);
+ cpg_write(SMSTPCR5, 0xC3FFFFFFU);
+ cpg_write(SMSTPCR6, 0xFFFFFFFFU);
+ cpg_write(SMSTPCR7, 0xFFFFFFFFU);
+ cpg_write(SMSTPCR8, 0x01F1FFF7U);
+ cpg_write(SMSTPCR9, 0xFFFFFFFFU);
+ cpg_write(SMSTPCR10, 0xFFFEFFE0U);
+ cpg_write(SMSTPCR11, 0x000000B7U);
+}
+#endif
+
+#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N)
+static void bl2_realtime_cpg_init_m3n(void)
+{
+ /** Realtime Module Stop Control Registers */
+ cpg_write(RMSTPCR0, 0x00210000U);
+ cpg_write(RMSTPCR1, 0xFFFFFFFFU);
+ cpg_write(RMSTPCR2, 0x040E0FDCU);
+ cpg_write(RMSTPCR3, 0xFFFFFFDFU);
+ cpg_write(RMSTPCR4, 0x80000004U);
+ cpg_write(RMSTPCR5, 0xC3FFFFFFU);
+ cpg_write(RMSTPCR6, 0xFFFFFFFFU);
+ cpg_write(RMSTPCR7, 0xFFFFFFFFU);
+ cpg_write(RMSTPCR8, 0x00F1FFF7U);
+ cpg_write(RMSTPCR9, 0xFFFFFFFFU);
+ cpg_write(RMSTPCR10, 0xFFFFFFE0U);
+ cpg_write(RMSTPCR11, 0x000000B7U);
+}
+
+static void bl2_system_cpg_init_m3n(void)
+{
+ /* System Module Stop Control Registers */
+ cpg_write(SMSTPCR0, 0x00210000U);
+ cpg_write(SMSTPCR1, 0xFFFFFFFFU);
+ cpg_write(SMSTPCR2, 0x040E2FDCU);
+ cpg_write(SMSTPCR3, 0xFFFFFBDFU);
+ cpg_write(SMSTPCR4, 0x80000004U);
+ cpg_write(SMSTPCR5, 0xC3FFFFFFU);
+ cpg_write(SMSTPCR6, 0xFFFFFFFFU);
+ cpg_write(SMSTPCR7, 0xFFFFFFFFU);
+ cpg_write(SMSTPCR8, 0x00F1FFF7U);
+ cpg_write(SMSTPCR9, 0xFFFFFFFFU);
+ cpg_write(SMSTPCR10, 0xFFFFFFE0U);
+ cpg_write(SMSTPCR11, 0x000000B7U);
+}
+#endif
+
+#if (RCAR_LSI == RCAR_E3)
+static void bl2_realtime_cpg_init_e3(void)
+{
+ /* Realtime Module Stop Control Registers */
+ cpg_write(RMSTPCR0, 0x00210000U);
+ cpg_write(RMSTPCR1, 0xFFFFFFFFU);
+ cpg_write(RMSTPCR2, 0x000E0FDCU);
+ cpg_write(RMSTPCR3, 0xFFFFFFDFU);
+ cpg_write(RMSTPCR4, 0x80000004U);
+ cpg_write(RMSTPCR5, 0xC3FFFFFFU);
+ cpg_write(RMSTPCR6, 0xFFFFFFFFU);
+ cpg_write(RMSTPCR7, 0xFFFFFFFFU);
+ cpg_write(RMSTPCR8, 0x00F1FFF7U);
+ cpg_write(RMSTPCR9, 0xFFFFFFDFU);
+ cpg_write(RMSTPCR10, 0xFFFFFFE8U);
+ cpg_write(RMSTPCR11, 0x000000B7U);
+}
+
+static void bl2_system_cpg_init_e3(void)
+{
+ /* System Module Stop Control Registers */
+ cpg_write(SMSTPCR0, 0x00210000U);
+ cpg_write(SMSTPCR1, 0xFFFFFFFFU);
+ cpg_write(SMSTPCR2, 0x000E2FDCU);
+ cpg_write(SMSTPCR3, 0xFFFFFBDFU);
+ cpg_write(SMSTPCR4, 0x80000004U);
+ cpg_write(SMSTPCR5, 0xC3FFFFFFU);
+ cpg_write(SMSTPCR6, 0xFFFFFFFFU);
+ cpg_write(SMSTPCR7, 0xFFFFFFFFU);
+ cpg_write(SMSTPCR8, 0x00F1FFF7U);
+ cpg_write(SMSTPCR9, 0xFFFFFFDFU);
+ cpg_write(SMSTPCR10, 0xFFFFFFE8U);
+ cpg_write(SMSTPCR11, 0x000000B7U);
+}
+#endif
+
+void bl2_cpg_init(void)
+{
+ uint32_t boot_cpu = mmio_read_32(RCAR_MODEMR) & MODEMR_BOOT_CPU_MASK;
+#if RCAR_LSI == RCAR_AUTO
+ uint32_t product = mmio_read_32(RCAR_PRR) & RCAR_PRODUCT_MASK;
+#endif
+ bl2_secure_cpg_init();
+
+ if (boot_cpu == MODEMR_BOOT_CPU_CA57 ||
+ boot_cpu == MODEMR_BOOT_CPU_CA53) {
+#if RCAR_LSI == RCAR_AUTO
+
+ switch (product) {
+ case RCAR_PRODUCT_H3:
+ bl2_realtime_cpg_init_h3();
+ break;
+ case RCAR_PRODUCT_M3:
+ bl2_realtime_cpg_init_m3();
+ break;
+ case RCAR_PRODUCT_M3N:
+ bl2_realtime_cpg_init_m3n();
+ break;
+ default:
+ panic();
+ break;
+ }
+#elif (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N)
+ bl2_realtime_cpg_init_h3();
+#elif RCAR_LSI == RCAR_M3
+ bl2_realtime_cpg_init_m3();
+#elif RCAR_LSI == RCAR_M3N
+ bl2_realtime_cpg_init_m3n();
+#elif RCAR_LSI == RCAR_E3
+ bl2_realtime_cpg_init_e3();
+#else
+#error "Don't have CPG initialize routine(unknown)."
+#endif
+ }
+}
+
+void bl2_system_cpg_init(void)
+{
+#if RCAR_LSI == RCAR_AUTO
+ uint32_t product = mmio_read_32(RCAR_PRR) & RCAR_PRODUCT_MASK;
+
+ switch (product) {
+ case RCAR_PRODUCT_H3:
+ bl2_system_cpg_init_h3();
+ break;
+ case RCAR_PRODUCT_M3:
+ bl2_system_cpg_init_m3();
+ break;
+ case RCAR_PRODUCT_M3N:
+ bl2_system_cpg_init_m3n();
+ break;
+ default:
+ panic();
+ break;
+ }
+#elif (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N)
+ bl2_system_cpg_init_h3();
+#elif RCAR_LSI == RCAR_M3
+ bl2_system_cpg_init_m3();
+#elif RCAR_LSI == RCAR_M3N
+ bl2_system_cpg_init_m3n();
+#elif RCAR_LSI == RCAR_E3
+ bl2_system_cpg_init_e3();
+#else
+#error "Don't have CPG initialize routine(unknown)."
+#endif
+}