commit 623935c6a182f3ae0fac75891c24fb3d30fc1d7c
author Biju Das <biju.das.jz@bp.renesas.com> Sun Dec 13 20:36:30 2020 +0000
committer Biju Das <biju.das.jz@bp.renesas.com> Wed Jan 13 13:03:48 2021 +0000
tree 7f1550a76043deb3f64c12ce930aa3283692fafa
parent 0fdbb5e12e27df3de80045f3eef889112a1e7b25

plat: renesas: rcar: Fix coding style

Sort the header includes alphabetically and fix checkpatch warnings.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I08fd0d12ee1d8d61391e8afc33f8c67fcf70c4e5

plat/renesas/rcar/bl2_cpg_init.c

diff --git a/plat/renesas/rcar/bl2_cpg_init.c b/plat/renesas/rcar/bl2_cpg_init.c
index c3ca9ea..1754344 100644
--- a/plat/renesas/rcar/bl2_cpg_init.c
+++ b/plat/renesas/rcar/bl2_cpg_init.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -7,8 +7,8 @@
 #include <common/debug.h>
 #include <lib/mmio.h>
 
-#include "rcar_def.h"
 #include "cpg_registers.h"
+#include "rcar_def.h"
 #include "rcar_private.h"
 
 static void bl2_secure_cpg_init(void);
@@ -77,7 +77,7 @@
 	stop_cr5 = 0xBFFFFFFFU;
 #endif
 
-	/** Secure Module Stop Control Registers */
+	/* Secure Module Stop Control Registers */
 	cpg_write(SCMSTPCR0, 0xFFFFFFFFU);
 	cpg_write(SCMSTPCR1, 0xFFFFFFFFU);
 	cpg_write(SCMSTPCR2, stop_cr2);
@@ -91,7 +91,7 @@
 	cpg_write(SCMSTPCR10, 0xFFFFFFFFU);
 	cpg_write(SCMSTPCR11, 0xFFFFFFFFU);
 
-	/** Secure Software Reset Access Enable Control Registers */
+	/* Secure Software Reset Access Enable Control Registers */
 	cpg_write(SCSRSTECR0, 0x00000000U);
 	cpg_write(SCSRSTECR1, 0x00000000U);
 	cpg_write(SCSRSTECR2, reset_cr2);
@@ -152,7 +152,7 @@
 #if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3)
 static void bl2_realtime_cpg_init_m3(void)
 {
-	/** Realtime Module Stop Control Registers */
+	/* Realtime Module Stop Control Registers */
 	cpg_write(RMSTPCR0, 0x00200000U);
 	cpg_write(RMSTPCR1, 0xFFFFFFFFU);
 	cpg_write(RMSTPCR2, 0x040E0FDCU);
@@ -169,7 +169,7 @@
 
 static void bl2_system_cpg_init_m3(void)
 {
-	/** System Module Stop Control Registers */
+	/* System Module Stop Control Registers */
 	cpg_write(SMSTPCR0, 0x00200000U);
 	cpg_write(SMSTPCR1, 0xFFFFFFFFU);
 	cpg_write(SMSTPCR2, 0x040E2FDCU);
@@ -188,7 +188,7 @@
 #if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N)
 static void bl2_realtime_cpg_init_m3n(void)
 {
-	/** Realtime Module Stop Control Registers */
+	/* Realtime Module Stop Control Registers */
 	cpg_write(RMSTPCR0, 0x00210000U);
 	cpg_write(RMSTPCR1, 0xFFFFFFFFU);
 	cpg_write(RMSTPCR2, 0x040E0FDCU);