blob: 880ad360450176d2057dd71e834859784afc19c1 [file] [log] [blame]
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +02001/*
2 * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <debug.h>
8#include <mmio.h>
9#include "rcar_def.h"
10#include "cpg_registers.h"
11#include "rcar_private.h"
12
13static void bl2_secure_cpg_init(void);
14
15#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N)
16static void bl2_realtime_cpg_init_h3(void);
17static void bl2_system_cpg_init_h3(void);
18#endif
19
20#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3)
21static void bl2_realtime_cpg_init_m3(void);
22static void bl2_system_cpg_init_m3(void);
23#endif
24
25#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N)
26static void bl2_realtime_cpg_init_m3n(void);
27static void bl2_system_cpg_init_m3n(void);
28#endif
29
30#if (RCAR_LSI == RCAR_E3)
31static void bl2_realtime_cpg_init_e3(void);
32static void bl2_system_cpg_init_e3(void);
33#endif
34
35typedef struct {
36 uintptr_t adr;
37 uint32_t val;
38} reg_setting_t;
39
40static void bl2_secure_cpg_init(void)
41{
42 uint32_t stop_cr2, reset_cr2;
43
44#if (RCAR_LSI == RCAR_E3)
ldts0a596b42018-11-06 10:17:12 +010045 reset_cr2 = 0x10000000U;
46 stop_cr2 = 0xEFFFFFFFU;
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +020047#else
48 reset_cr2 = 0x14000000U;
49 stop_cr2 = 0xEBFFFFFFU;
50#endif
51 /** Secure Module Stop Control Registers */
52 cpg_write(SCMSTPCR0, 0xFFFFFFFFU);
53 cpg_write(SCMSTPCR1, 0xFFFFFFFFU);
54 cpg_write(SCMSTPCR2, stop_cr2);
55 cpg_write(SCMSTPCR3, 0xFFFFFFFFU);
56 cpg_write(SCMSTPCR4, 0x7FFFFFFFU);
57 cpg_write(SCMSTPCR5, 0xBFFFFFFFU);
58 cpg_write(SCMSTPCR6, 0xFFFFFFFFU);
59 cpg_write(SCMSTPCR7, 0xFFFFFFFFU);
60 cpg_write(SCMSTPCR8, 0xFFFFFFFFU);
61 cpg_write(SCMSTPCR9, 0xFFFDFFFFU);
62 cpg_write(SCMSTPCR10, 0xFFFFFFFFU);
63 cpg_write(SCMSTPCR11, 0xFFFFFFFFU);
64
65 /** Secure Software Reset Access Enable Control Registers */
66 cpg_write(SCSRSTECR0, 0x00000000U);
67 cpg_write(SCSRSTECR1, 0x00000000U);
68 cpg_write(SCSRSTECR2, reset_cr2);
69 cpg_write(SCSRSTECR3, 0x00000000U);
70 cpg_write(SCSRSTECR4, 0x80000003U);
71 cpg_write(SCSRSTECR5, 0x40000000U);
72 cpg_write(SCSRSTECR6, 0x00000000U);
73 cpg_write(SCSRSTECR7, 0x00000000U);
74 cpg_write(SCSRSTECR8, 0x00000000U);
75 cpg_write(SCSRSTECR9, 0x00020000U);
76 cpg_write(SCSRSTECR10, 0x00000000U);
77 cpg_write(SCSRSTECR11, 0x00000000U);
78}
79
80#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N)
81static void bl2_realtime_cpg_init_h3(void)
82{
83 uint32_t cut = mmio_read_32(RCAR_PRR) & RCAR_CUT_MASK;
84 uint32_t cr0, cr8;
85
86 cr0 = (cut == RCAR_CUT_VER10 || cut == RCAR_CUT_VER11) ?
87 0x00200000U : 0x00210000U;
88 cr8 = (cut == RCAR_CUT_VER10 || cut == RCAR_CUT_VER11) ?
89 0x01F1FFF4U : 0x01F1FFF7U;
90
91 cpg_write(RMSTPCR0, cr0);
92 cpg_write(RMSTPCR1, 0xFFFFFFFFU);
93 cpg_write(RMSTPCR2, 0x040E0FDCU);
94 cpg_write(RMSTPCR3, 0xFFFFFFDFU);
95 cpg_write(RMSTPCR4, 0x80000004U);
96 cpg_write(RMSTPCR5, 0xC3FFFFFFU);
97 cpg_write(RMSTPCR6, 0xFFFFFFFFU);
98 cpg_write(RMSTPCR7, 0xFFFFFFFFU);
99 cpg_write(RMSTPCR8, cr8);
100 cpg_write(RMSTPCR9, 0xFFFFFFFEU);
101 cpg_write(RMSTPCR10, 0xFFFEFFE0U);
102 cpg_write(RMSTPCR11, 0x000000B7U);
103}
104
105static void bl2_system_cpg_init_h3(void)
106{
107 /** System Module Stop Control Registers */
108 cpg_write(SMSTPCR0, 0x00210000U);
109 cpg_write(SMSTPCR1, 0xFFFFFFFFU);
110 cpg_write(SMSTPCR2, 0x040E2FDCU);
111 cpg_write(SMSTPCR3, 0xFFFFFBDFU);
112 cpg_write(SMSTPCR4, 0x80000004U);
113 cpg_write(SMSTPCR5, 0xC3FFFFFFU);
114 cpg_write(SMSTPCR6, 0xFFFFFFFFU);
115 cpg_write(SMSTPCR7, 0xFFFFFFFFU);
116 cpg_write(SMSTPCR8, 0x01F1FFF5U);
117 cpg_write(SMSTPCR9, 0xFFFFFFFFU);
118 cpg_write(SMSTPCR10, 0xFFFEFFE0U);
119 cpg_write(SMSTPCR11, 0x000000B7U);
120}
121#endif
122
123#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3)
124static void bl2_realtime_cpg_init_m3(void)
125{
126 /** Realtime Module Stop Control Registers */
127 cpg_write(RMSTPCR0, 0x00200000U);
128 cpg_write(RMSTPCR1, 0xFFFFFFFFU);
129 cpg_write(RMSTPCR2, 0x040E0FDCU);
130 cpg_write(RMSTPCR3, 0xFFFFFFDFU);
131 cpg_write(RMSTPCR4, 0x80000004U);
132 cpg_write(RMSTPCR5, 0xC3FFFFFFU);
133 cpg_write(RMSTPCR6, 0xFFFFFFFFU);
134 cpg_write(RMSTPCR7, 0xFFFFFFFFU);
135 cpg_write(RMSTPCR8, 0x01F1FFF7U);
136 cpg_write(RMSTPCR9, 0xFFFFFFFEU);
137 cpg_write(RMSTPCR10, 0xFFFEFFE0U);
138 cpg_write(RMSTPCR11, 0x000000B7U);
139}
140
141static void bl2_system_cpg_init_m3(void)
142{
143 /** System Module Stop Control Registers */
144 cpg_write(SMSTPCR0, 0x00200000U);
145 cpg_write(SMSTPCR1, 0xFFFFFFFFU);
146 cpg_write(SMSTPCR2, 0x040E2FDCU);
147 cpg_write(SMSTPCR3, 0xFFFFFBDFU);
148 cpg_write(SMSTPCR4, 0x80000004U);
149 cpg_write(SMSTPCR5, 0xC3FFFFFFU);
150 cpg_write(SMSTPCR6, 0xFFFFFFFFU);
151 cpg_write(SMSTPCR7, 0xFFFFFFFFU);
152 cpg_write(SMSTPCR8, 0x01F1FFF7U);
153 cpg_write(SMSTPCR9, 0xFFFFFFFFU);
154 cpg_write(SMSTPCR10, 0xFFFEFFE0U);
155 cpg_write(SMSTPCR11, 0x000000B7U);
156}
157#endif
158
159#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N)
160static void bl2_realtime_cpg_init_m3n(void)
161{
162 /** Realtime Module Stop Control Registers */
163 cpg_write(RMSTPCR0, 0x00210000U);
164 cpg_write(RMSTPCR1, 0xFFFFFFFFU);
165 cpg_write(RMSTPCR2, 0x040E0FDCU);
166 cpg_write(RMSTPCR3, 0xFFFFFFDFU);
167 cpg_write(RMSTPCR4, 0x80000004U);
168 cpg_write(RMSTPCR5, 0xC3FFFFFFU);
169 cpg_write(RMSTPCR6, 0xFFFFFFFFU);
170 cpg_write(RMSTPCR7, 0xFFFFFFFFU);
171 cpg_write(RMSTPCR8, 0x00F1FFF7U);
172 cpg_write(RMSTPCR9, 0xFFFFFFFFU);
173 cpg_write(RMSTPCR10, 0xFFFFFFE0U);
174 cpg_write(RMSTPCR11, 0x000000B7U);
175}
176
177static void bl2_system_cpg_init_m3n(void)
178{
179 /* System Module Stop Control Registers */
180 cpg_write(SMSTPCR0, 0x00210000U);
181 cpg_write(SMSTPCR1, 0xFFFFFFFFU);
182 cpg_write(SMSTPCR2, 0x040E2FDCU);
183 cpg_write(SMSTPCR3, 0xFFFFFBDFU);
184 cpg_write(SMSTPCR4, 0x80000004U);
185 cpg_write(SMSTPCR5, 0xC3FFFFFFU);
186 cpg_write(SMSTPCR6, 0xFFFFFFFFU);
187 cpg_write(SMSTPCR7, 0xFFFFFFFFU);
188 cpg_write(SMSTPCR8, 0x00F1FFF7U);
189 cpg_write(SMSTPCR9, 0xFFFFFFFFU);
190 cpg_write(SMSTPCR10, 0xFFFFFFE0U);
191 cpg_write(SMSTPCR11, 0x000000B7U);
192}
193#endif
194
195#if (RCAR_LSI == RCAR_E3)
196static void bl2_realtime_cpg_init_e3(void)
197{
198 /* Realtime Module Stop Control Registers */
199 cpg_write(RMSTPCR0, 0x00210000U);
200 cpg_write(RMSTPCR1, 0xFFFFFFFFU);
201 cpg_write(RMSTPCR2, 0x000E0FDCU);
202 cpg_write(RMSTPCR3, 0xFFFFFFDFU);
203 cpg_write(RMSTPCR4, 0x80000004U);
204 cpg_write(RMSTPCR5, 0xC3FFFFFFU);
205 cpg_write(RMSTPCR6, 0xFFFFFFFFU);
206 cpg_write(RMSTPCR7, 0xFFFFFFFFU);
207 cpg_write(RMSTPCR8, 0x00F1FFF7U);
208 cpg_write(RMSTPCR9, 0xFFFFFFDFU);
209 cpg_write(RMSTPCR10, 0xFFFFFFE8U);
210 cpg_write(RMSTPCR11, 0x000000B7U);
211}
212
213static void bl2_system_cpg_init_e3(void)
214{
215 /* System Module Stop Control Registers */
216 cpg_write(SMSTPCR0, 0x00210000U);
217 cpg_write(SMSTPCR1, 0xFFFFFFFFU);
218 cpg_write(SMSTPCR2, 0x000E2FDCU);
219 cpg_write(SMSTPCR3, 0xFFFFFBDFU);
220 cpg_write(SMSTPCR4, 0x80000004U);
221 cpg_write(SMSTPCR5, 0xC3FFFFFFU);
222 cpg_write(SMSTPCR6, 0xFFFFFFFFU);
223 cpg_write(SMSTPCR7, 0xFFFFFFFFU);
224 cpg_write(SMSTPCR8, 0x00F1FFF7U);
225 cpg_write(SMSTPCR9, 0xFFFFFFDFU);
226 cpg_write(SMSTPCR10, 0xFFFFFFE8U);
227 cpg_write(SMSTPCR11, 0x000000B7U);
228}
229#endif
230
231void bl2_cpg_init(void)
232{
233 uint32_t boot_cpu = mmio_read_32(RCAR_MODEMR) & MODEMR_BOOT_CPU_MASK;
234#if RCAR_LSI == RCAR_AUTO
235 uint32_t product = mmio_read_32(RCAR_PRR) & RCAR_PRODUCT_MASK;
236#endif
237 bl2_secure_cpg_init();
238
239 if (boot_cpu == MODEMR_BOOT_CPU_CA57 ||
240 boot_cpu == MODEMR_BOOT_CPU_CA53) {
241#if RCAR_LSI == RCAR_AUTO
242
243 switch (product) {
244 case RCAR_PRODUCT_H3:
245 bl2_realtime_cpg_init_h3();
246 break;
247 case RCAR_PRODUCT_M3:
248 bl2_realtime_cpg_init_m3();
249 break;
250 case RCAR_PRODUCT_M3N:
251 bl2_realtime_cpg_init_m3n();
252 break;
253 default:
254 panic();
255 break;
256 }
257#elif (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N)
258 bl2_realtime_cpg_init_h3();
259#elif RCAR_LSI == RCAR_M3
260 bl2_realtime_cpg_init_m3();
261#elif RCAR_LSI == RCAR_M3N
262 bl2_realtime_cpg_init_m3n();
263#elif RCAR_LSI == RCAR_E3
264 bl2_realtime_cpg_init_e3();
265#else
266#error "Don't have CPG initialize routine(unknown)."
267#endif
268 }
269}
270
271void bl2_system_cpg_init(void)
272{
273#if RCAR_LSI == RCAR_AUTO
274 uint32_t product = mmio_read_32(RCAR_PRR) & RCAR_PRODUCT_MASK;
275
276 switch (product) {
277 case RCAR_PRODUCT_H3:
278 bl2_system_cpg_init_h3();
279 break;
280 case RCAR_PRODUCT_M3:
281 bl2_system_cpg_init_m3();
282 break;
283 case RCAR_PRODUCT_M3N:
284 bl2_system_cpg_init_m3n();
285 break;
286 default:
287 panic();
288 break;
289 }
290#elif (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N)
291 bl2_system_cpg_init_h3();
292#elif RCAR_LSI == RCAR_M3
293 bl2_system_cpg_init_m3();
294#elif RCAR_LSI == RCAR_M3N
295 bl2_system_cpg_init_m3n();
296#elif RCAR_LSI == RCAR_E3
297 bl2_system_cpg_init_e3();
298#else
299#error "Don't have CPG initialize routine(unknown)."
300#endif
301}