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git01.mediatek.com / filogic / atf / bf084dca997b9e4abe166ca48d8d02fcfe968f14 / . / plat / renesas / rcar / bl2_cpg_init.c
blob: eb533cef555cc126d2185214458c271f9b45dfa7 [file] [log] [blame]
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200[diff] [blame^]1/*
2 * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <debug.h>
8#include <mmio.h>
9#include "rcar_def.h"
10#include "cpg_registers.h"
11#include "rcar_private.h"
12
13static void bl2_secure_cpg_init(void);
14
15#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N)
16static void bl2_realtime_cpg_init_h3(void);
17static void bl2_system_cpg_init_h3(void);
18#endif
19
20#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3)
21static void bl2_realtime_cpg_init_m3(void);
22static void bl2_system_cpg_init_m3(void);
23#endif
24
25#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N)
26static void bl2_realtime_cpg_init_m3n(void);
27static void bl2_system_cpg_init_m3n(void);
28#endif
29
30#if (RCAR_LSI == RCAR_E3)
31static void bl2_realtime_cpg_init_e3(void);
32static void bl2_system_cpg_init_e3(void);
33#endif
34
35typedef struct {
36 uintptr_t adr;
37 uint32_t val;
38} reg_setting_t;
39
40static void bl2_secure_cpg_init(void)
41{
42 uint32_t stop_cr2, reset_cr2;
43
44#if (RCAR_LSI == RCAR_E3)
45 reset_cr2 = 0x10000000U stop_cr2 = 0xEFFFFFFFU;
46#else
47 reset_cr2 = 0x14000000U;
48 stop_cr2 = 0xEBFFFFFFU;
49#endif
50 /** Secure Module Stop Control Registers */
51 cpg_write(SCMSTPCR0, 0xFFFFFFFFU);
52 cpg_write(SCMSTPCR1, 0xFFFFFFFFU);
53 cpg_write(SCMSTPCR2, stop_cr2);
54 cpg_write(SCMSTPCR3, 0xFFFFFFFFU);
55 cpg_write(SCMSTPCR4, 0x7FFFFFFFU);
56 cpg_write(SCMSTPCR5, 0xBFFFFFFFU);
57 cpg_write(SCMSTPCR6, 0xFFFFFFFFU);
58 cpg_write(SCMSTPCR7, 0xFFFFFFFFU);
59 cpg_write(SCMSTPCR8, 0xFFFFFFFFU);
60 cpg_write(SCMSTPCR9, 0xFFFDFFFFU);
61 cpg_write(SCMSTPCR10, 0xFFFFFFFFU);
62 cpg_write(SCMSTPCR11, 0xFFFFFFFFU);
63
64 /** Secure Software Reset Access Enable Control Registers */
65 cpg_write(SCSRSTECR0, 0x00000000U);
66 cpg_write(SCSRSTECR1, 0x00000000U);
67 cpg_write(SCSRSTECR2, reset_cr2);
68 cpg_write(SCSRSTECR3, 0x00000000U);
69 cpg_write(SCSRSTECR4, 0x80000003U);
70 cpg_write(SCSRSTECR5, 0x40000000U);
71 cpg_write(SCSRSTECR6, 0x00000000U);
72 cpg_write(SCSRSTECR7, 0x00000000U);
73 cpg_write(SCSRSTECR8, 0x00000000U);
74 cpg_write(SCSRSTECR9, 0x00020000U);
75 cpg_write(SCSRSTECR10, 0x00000000U);
76 cpg_write(SCSRSTECR11, 0x00000000U);
77}
78
79#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N)
80static void bl2_realtime_cpg_init_h3(void)
81{
82 uint32_t cut = mmio_read_32(RCAR_PRR) & RCAR_CUT_MASK;
83 uint32_t cr0, cr8;
84
85 cr0 = (cut == RCAR_CUT_VER10 || cut == RCAR_CUT_VER11) ?
86 0x00200000U : 0x00210000U;
87 cr8 = (cut == RCAR_CUT_VER10 || cut == RCAR_CUT_VER11) ?
88 0x01F1FFF4U : 0x01F1FFF7U;
89
90 cpg_write(RMSTPCR0, cr0);
91 cpg_write(RMSTPCR1, 0xFFFFFFFFU);
92 cpg_write(RMSTPCR2, 0x040E0FDCU);
93 cpg_write(RMSTPCR3, 0xFFFFFFDFU);
94 cpg_write(RMSTPCR4, 0x80000004U);
95 cpg_write(RMSTPCR5, 0xC3FFFFFFU);
96 cpg_write(RMSTPCR6, 0xFFFFFFFFU);
97 cpg_write(RMSTPCR7, 0xFFFFFFFFU);
98 cpg_write(RMSTPCR8, cr8);
99 cpg_write(RMSTPCR9, 0xFFFFFFFEU);
100 cpg_write(RMSTPCR10, 0xFFFEFFE0U);
101 cpg_write(RMSTPCR11, 0x000000B7U);
102}
103
104static void bl2_system_cpg_init_h3(void)
105{
106 /** System Module Stop Control Registers */
107 cpg_write(SMSTPCR0, 0x00210000U);
108 cpg_write(SMSTPCR1, 0xFFFFFFFFU);
109 cpg_write(SMSTPCR2, 0x040E2FDCU);
110 cpg_write(SMSTPCR3, 0xFFFFFBDFU);
111 cpg_write(SMSTPCR4, 0x80000004U);
112 cpg_write(SMSTPCR5, 0xC3FFFFFFU);
113 cpg_write(SMSTPCR6, 0xFFFFFFFFU);
114 cpg_write(SMSTPCR7, 0xFFFFFFFFU);
115 cpg_write(SMSTPCR8, 0x01F1FFF5U);
116 cpg_write(SMSTPCR9, 0xFFFFFFFFU);
117 cpg_write(SMSTPCR10, 0xFFFEFFE0U);
118 cpg_write(SMSTPCR11, 0x000000B7U);
119}
120#endif
121
122#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3)
123static void bl2_realtime_cpg_init_m3(void)
124{
125 /** Realtime Module Stop Control Registers */
126 cpg_write(RMSTPCR0, 0x00200000U);
127 cpg_write(RMSTPCR1, 0xFFFFFFFFU);
128 cpg_write(RMSTPCR2, 0x040E0FDCU);
129 cpg_write(RMSTPCR3, 0xFFFFFFDFU);
130 cpg_write(RMSTPCR4, 0x80000004U);
131 cpg_write(RMSTPCR5, 0xC3FFFFFFU);
132 cpg_write(RMSTPCR6, 0xFFFFFFFFU);
133 cpg_write(RMSTPCR7, 0xFFFFFFFFU);
134 cpg_write(RMSTPCR8, 0x01F1FFF7U);
135 cpg_write(RMSTPCR9, 0xFFFFFFFEU);
136 cpg_write(RMSTPCR10, 0xFFFEFFE0U);
137 cpg_write(RMSTPCR11, 0x000000B7U);
138}
139
140static void bl2_system_cpg_init_m3(void)
141{
142 /** System Module Stop Control Registers */
143 cpg_write(SMSTPCR0, 0x00200000U);
144 cpg_write(SMSTPCR1, 0xFFFFFFFFU);
145 cpg_write(SMSTPCR2, 0x040E2FDCU);
146 cpg_write(SMSTPCR3, 0xFFFFFBDFU);
147 cpg_write(SMSTPCR4, 0x80000004U);
148 cpg_write(SMSTPCR5, 0xC3FFFFFFU);
149 cpg_write(SMSTPCR6, 0xFFFFFFFFU);
150 cpg_write(SMSTPCR7, 0xFFFFFFFFU);
151 cpg_write(SMSTPCR8, 0x01F1FFF7U);
152 cpg_write(SMSTPCR9, 0xFFFFFFFFU);
153 cpg_write(SMSTPCR10, 0xFFFEFFE0U);
154 cpg_write(SMSTPCR11, 0x000000B7U);
155}
156#endif
157
158#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N)
159static void bl2_realtime_cpg_init_m3n(void)
160{
161 /** Realtime Module Stop Control Registers */
162 cpg_write(RMSTPCR0, 0x00210000U);
163 cpg_write(RMSTPCR1, 0xFFFFFFFFU);
164 cpg_write(RMSTPCR2, 0x040E0FDCU);
165 cpg_write(RMSTPCR3, 0xFFFFFFDFU);
166 cpg_write(RMSTPCR4, 0x80000004U);
167 cpg_write(RMSTPCR5, 0xC3FFFFFFU);
168 cpg_write(RMSTPCR6, 0xFFFFFFFFU);
169 cpg_write(RMSTPCR7, 0xFFFFFFFFU);
170 cpg_write(RMSTPCR8, 0x00F1FFF7U);
171 cpg_write(RMSTPCR9, 0xFFFFFFFFU);
172 cpg_write(RMSTPCR10, 0xFFFFFFE0U);
173 cpg_write(RMSTPCR11, 0x000000B7U);
174}
175
176static void bl2_system_cpg_init_m3n(void)
177{
178 /* System Module Stop Control Registers */
179 cpg_write(SMSTPCR0, 0x00210000U);
180 cpg_write(SMSTPCR1, 0xFFFFFFFFU);
181 cpg_write(SMSTPCR2, 0x040E2FDCU);
182 cpg_write(SMSTPCR3, 0xFFFFFBDFU);
183 cpg_write(SMSTPCR4, 0x80000004U);
184 cpg_write(SMSTPCR5, 0xC3FFFFFFU);
185 cpg_write(SMSTPCR6, 0xFFFFFFFFU);
186 cpg_write(SMSTPCR7, 0xFFFFFFFFU);
187 cpg_write(SMSTPCR8, 0x00F1FFF7U);
188 cpg_write(SMSTPCR9, 0xFFFFFFFFU);
189 cpg_write(SMSTPCR10, 0xFFFFFFE0U);
190 cpg_write(SMSTPCR11, 0x000000B7U);
191}
192#endif
193
194#if (RCAR_LSI == RCAR_E3)
195static void bl2_realtime_cpg_init_e3(void)
196{
197 /* Realtime Module Stop Control Registers */
198 cpg_write(RMSTPCR0, 0x00210000U);
199 cpg_write(RMSTPCR1, 0xFFFFFFFFU);
200 cpg_write(RMSTPCR2, 0x000E0FDCU);
201 cpg_write(RMSTPCR3, 0xFFFFFFDFU);
202 cpg_write(RMSTPCR4, 0x80000004U);
203 cpg_write(RMSTPCR5, 0xC3FFFFFFU);
204 cpg_write(RMSTPCR6, 0xFFFFFFFFU);
205 cpg_write(RMSTPCR7, 0xFFFFFFFFU);
206 cpg_write(RMSTPCR8, 0x00F1FFF7U);
207 cpg_write(RMSTPCR9, 0xFFFFFFDFU);
208 cpg_write(RMSTPCR10, 0xFFFFFFE8U);
209 cpg_write(RMSTPCR11, 0x000000B7U);
210}
211
212static void bl2_system_cpg_init_e3(void)
213{
214 /* System Module Stop Control Registers */
215 cpg_write(SMSTPCR0, 0x00210000U);
216 cpg_write(SMSTPCR1, 0xFFFFFFFFU);
217 cpg_write(SMSTPCR2, 0x000E2FDCU);
218 cpg_write(SMSTPCR3, 0xFFFFFBDFU);
219 cpg_write(SMSTPCR4, 0x80000004U);
220 cpg_write(SMSTPCR5, 0xC3FFFFFFU);
221 cpg_write(SMSTPCR6, 0xFFFFFFFFU);
222 cpg_write(SMSTPCR7, 0xFFFFFFFFU);
223 cpg_write(SMSTPCR8, 0x00F1FFF7U);
224 cpg_write(SMSTPCR9, 0xFFFFFFDFU);
225 cpg_write(SMSTPCR10, 0xFFFFFFE8U);
226 cpg_write(SMSTPCR11, 0x000000B7U);
227}
228#endif
229
230void bl2_cpg_init(void)
231{
232 uint32_t boot_cpu = mmio_read_32(RCAR_MODEMR) & MODEMR_BOOT_CPU_MASK;
233#if RCAR_LSI == RCAR_AUTO
234 uint32_t product = mmio_read_32(RCAR_PRR) & RCAR_PRODUCT_MASK;
235#endif
236 bl2_secure_cpg_init();
237
238 if (boot_cpu == MODEMR_BOOT_CPU_CA57 ||
239 boot_cpu == MODEMR_BOOT_CPU_CA53) {
240#if RCAR_LSI == RCAR_AUTO
241
242 switch (product) {
243 case RCAR_PRODUCT_H3:
244 bl2_realtime_cpg_init_h3();
245 break;
246 case RCAR_PRODUCT_M3:
247 bl2_realtime_cpg_init_m3();
248 break;
249 case RCAR_PRODUCT_M3N:
250 bl2_realtime_cpg_init_m3n();
251 break;
252 default:
253 panic();
254 break;
255 }
256#elif (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N)
257 bl2_realtime_cpg_init_h3();
258#elif RCAR_LSI == RCAR_M3
259 bl2_realtime_cpg_init_m3();
260#elif RCAR_LSI == RCAR_M3N
261 bl2_realtime_cpg_init_m3n();
262#elif RCAR_LSI == RCAR_E3
263 bl2_realtime_cpg_init_e3();
264#else
265#error "Don't have CPG initialize routine(unknown)."
266#endif
267 }
268}
269
270void bl2_system_cpg_init(void)
271{
272#if RCAR_LSI == RCAR_AUTO
273 uint32_t product = mmio_read_32(RCAR_PRR) & RCAR_PRODUCT_MASK;
274
275 switch (product) {
276 case RCAR_PRODUCT_H3:
277 bl2_system_cpg_init_h3();
278 break;
279 case RCAR_PRODUCT_M3:
280 bl2_system_cpg_init_m3();
281 break;
282 case RCAR_PRODUCT_M3N:
283 bl2_system_cpg_init_m3n();
284 break;
285 default:
286 panic();
287 break;
288 }
289#elif (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N)
290 bl2_system_cpg_init_h3();
291#elif RCAR_LSI == RCAR_M3
292 bl2_system_cpg_init_m3();
293#elif RCAR_LSI == RCAR_M3N
294 bl2_system_cpg_init_m3n();
295#elif RCAR_LSI == RCAR_E3
296 bl2_system_cpg_init_e3();
297#else
298#error "Don't have CPG initialize routine(unknown)."
299#endif
300}