blob: 673217297fba2664adb9144ccddedd77dd10c64b [file] [log] [blame]
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +02001/*
2 * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00007#include <common/debug.h>
8#include <lib/mmio.h>
9
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +020010#include "rcar_def.h"
11#include "cpg_registers.h"
12#include "rcar_private.h"
13
14static void bl2_secure_cpg_init(void);
15
16#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N)
17static void bl2_realtime_cpg_init_h3(void);
18static void bl2_system_cpg_init_h3(void);
19#endif
20
21#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3)
22static void bl2_realtime_cpg_init_m3(void);
23static void bl2_system_cpg_init_m3(void);
24#endif
25
26#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N)
27static void bl2_realtime_cpg_init_m3n(void);
28static void bl2_system_cpg_init_m3n(void);
29#endif
30
Marek Vasut2b9b0fc2019-01-05 13:57:16 +010031#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_E3)
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +020032static void bl2_realtime_cpg_init_e3(void);
33static void bl2_system_cpg_init_e3(void);
34#endif
35
Marek Vasut4ae342c2019-01-05 13:56:03 +010036#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_D3)
37static void bl2_realtime_cpg_init_d3(void);
38static void bl2_system_cpg_init_d3(void);
39#endif
40
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +020041typedef struct {
42 uintptr_t adr;
43 uint32_t val;
44} reg_setting_t;
45
46static void bl2_secure_cpg_init(void)
47{
48 uint32_t stop_cr2, reset_cr2;
Marek Vasut4ae342c2019-01-05 13:56:03 +010049 uint32_t stop_cr4, reset_cr4;
50 uint32_t stop_cr5, reset_cr5;
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +020051
Marek Vasut4ae342c2019-01-05 13:56:03 +010052#if (RCAR_LSI == RCAR_D3)
53 reset_cr2 = 0x00000000U;
54 stop_cr2 = 0xFFFFFFFFU;
55#elif (RCAR_LSI == RCAR_E3)
ldts0a596b42018-11-06 10:17:12 +010056 reset_cr2 = 0x10000000U;
57 stop_cr2 = 0xEFFFFFFFU;
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +020058#else
59 reset_cr2 = 0x14000000U;
60 stop_cr2 = 0xEBFFFFFFU;
61#endif
Marek Vasut4ae342c2019-01-05 13:56:03 +010062
63#if (RCAR_LSI == RCAR_D3)
64 reset_cr4 = 0x00000000U;
65 stop_cr4 = 0xFFFFFFFFU;
66 reset_cr5 = 0x00000000U;
67 stop_cr5 = 0xFFFFFFFFU;
68#else
69 reset_cr4 = 0x80000003U;
70 stop_cr4 = 0x7FFFFFFFU;
71 reset_cr5 = 0x40000000U;
72 stop_cr5 = 0xBFFFFFFFU;
73#endif
74
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +020075 /** Secure Module Stop Control Registers */
76 cpg_write(SCMSTPCR0, 0xFFFFFFFFU);
77 cpg_write(SCMSTPCR1, 0xFFFFFFFFU);
78 cpg_write(SCMSTPCR2, stop_cr2);
79 cpg_write(SCMSTPCR3, 0xFFFFFFFFU);
Marek Vasut4ae342c2019-01-05 13:56:03 +010080 cpg_write(SCMSTPCR4, stop_cr4);
81 cpg_write(SCMSTPCR5, stop_cr5);
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +020082 cpg_write(SCMSTPCR6, 0xFFFFFFFFU);
83 cpg_write(SCMSTPCR7, 0xFFFFFFFFU);
84 cpg_write(SCMSTPCR8, 0xFFFFFFFFU);
85 cpg_write(SCMSTPCR9, 0xFFFDFFFFU);
86 cpg_write(SCMSTPCR10, 0xFFFFFFFFU);
87 cpg_write(SCMSTPCR11, 0xFFFFFFFFU);
88
89 /** Secure Software Reset Access Enable Control Registers */
90 cpg_write(SCSRSTECR0, 0x00000000U);
91 cpg_write(SCSRSTECR1, 0x00000000U);
92 cpg_write(SCSRSTECR2, reset_cr2);
93 cpg_write(SCSRSTECR3, 0x00000000U);
Marek Vasut4ae342c2019-01-05 13:56:03 +010094 cpg_write(SCSRSTECR4, reset_cr4);
95 cpg_write(SCSRSTECR5, reset_cr5);
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +020096 cpg_write(SCSRSTECR6, 0x00000000U);
97 cpg_write(SCSRSTECR7, 0x00000000U);
98 cpg_write(SCSRSTECR8, 0x00000000U);
99 cpg_write(SCSRSTECR9, 0x00020000U);
100 cpg_write(SCSRSTECR10, 0x00000000U);
101 cpg_write(SCSRSTECR11, 0x00000000U);
102}
103
104#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N)
105static void bl2_realtime_cpg_init_h3(void)
106{
107 uint32_t cut = mmio_read_32(RCAR_PRR) & RCAR_CUT_MASK;
108 uint32_t cr0, cr8;
109
110 cr0 = (cut == RCAR_CUT_VER10 || cut == RCAR_CUT_VER11) ?
111 0x00200000U : 0x00210000U;
112 cr8 = (cut == RCAR_CUT_VER10 || cut == RCAR_CUT_VER11) ?
113 0x01F1FFF4U : 0x01F1FFF7U;
114
115 cpg_write(RMSTPCR0, cr0);
116 cpg_write(RMSTPCR1, 0xFFFFFFFFU);
117 cpg_write(RMSTPCR2, 0x040E0FDCU);
118 cpg_write(RMSTPCR3, 0xFFFFFFDFU);
119 cpg_write(RMSTPCR4, 0x80000004U);
120 cpg_write(RMSTPCR5, 0xC3FFFFFFU);
121 cpg_write(RMSTPCR6, 0xFFFFFFFFU);
122 cpg_write(RMSTPCR7, 0xFFFFFFFFU);
123 cpg_write(RMSTPCR8, cr8);
124 cpg_write(RMSTPCR9, 0xFFFFFFFEU);
125 cpg_write(RMSTPCR10, 0xFFFEFFE0U);
126 cpg_write(RMSTPCR11, 0x000000B7U);
127}
128
129static void bl2_system_cpg_init_h3(void)
130{
131 /** System Module Stop Control Registers */
132 cpg_write(SMSTPCR0, 0x00210000U);
133 cpg_write(SMSTPCR1, 0xFFFFFFFFU);
134 cpg_write(SMSTPCR2, 0x040E2FDCU);
135 cpg_write(SMSTPCR3, 0xFFFFFBDFU);
136 cpg_write(SMSTPCR4, 0x80000004U);
137 cpg_write(SMSTPCR5, 0xC3FFFFFFU);
138 cpg_write(SMSTPCR6, 0xFFFFFFFFU);
139 cpg_write(SMSTPCR7, 0xFFFFFFFFU);
140 cpg_write(SMSTPCR8, 0x01F1FFF5U);
141 cpg_write(SMSTPCR9, 0xFFFFFFFFU);
142 cpg_write(SMSTPCR10, 0xFFFEFFE0U);
143 cpg_write(SMSTPCR11, 0x000000B7U);
144}
145#endif
146
147#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3)
148static void bl2_realtime_cpg_init_m3(void)
149{
150 /** Realtime Module Stop Control Registers */
151 cpg_write(RMSTPCR0, 0x00200000U);
152 cpg_write(RMSTPCR1, 0xFFFFFFFFU);
153 cpg_write(RMSTPCR2, 0x040E0FDCU);
154 cpg_write(RMSTPCR3, 0xFFFFFFDFU);
155 cpg_write(RMSTPCR4, 0x80000004U);
156 cpg_write(RMSTPCR5, 0xC3FFFFFFU);
157 cpg_write(RMSTPCR6, 0xFFFFFFFFU);
158 cpg_write(RMSTPCR7, 0xFFFFFFFFU);
159 cpg_write(RMSTPCR8, 0x01F1FFF7U);
160 cpg_write(RMSTPCR9, 0xFFFFFFFEU);
161 cpg_write(RMSTPCR10, 0xFFFEFFE0U);
162 cpg_write(RMSTPCR11, 0x000000B7U);
163}
164
165static void bl2_system_cpg_init_m3(void)
166{
167 /** System Module Stop Control Registers */
168 cpg_write(SMSTPCR0, 0x00200000U);
169 cpg_write(SMSTPCR1, 0xFFFFFFFFU);
170 cpg_write(SMSTPCR2, 0x040E2FDCU);
171 cpg_write(SMSTPCR3, 0xFFFFFBDFU);
172 cpg_write(SMSTPCR4, 0x80000004U);
173 cpg_write(SMSTPCR5, 0xC3FFFFFFU);
174 cpg_write(SMSTPCR6, 0xFFFFFFFFU);
175 cpg_write(SMSTPCR7, 0xFFFFFFFFU);
176 cpg_write(SMSTPCR8, 0x01F1FFF7U);
177 cpg_write(SMSTPCR9, 0xFFFFFFFFU);
178 cpg_write(SMSTPCR10, 0xFFFEFFE0U);
179 cpg_write(SMSTPCR11, 0x000000B7U);
180}
181#endif
182
183#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N)
184static void bl2_realtime_cpg_init_m3n(void)
185{
186 /** Realtime Module Stop Control Registers */
187 cpg_write(RMSTPCR0, 0x00210000U);
188 cpg_write(RMSTPCR1, 0xFFFFFFFFU);
189 cpg_write(RMSTPCR2, 0x040E0FDCU);
190 cpg_write(RMSTPCR3, 0xFFFFFFDFU);
191 cpg_write(RMSTPCR4, 0x80000004U);
192 cpg_write(RMSTPCR5, 0xC3FFFFFFU);
193 cpg_write(RMSTPCR6, 0xFFFFFFFFU);
194 cpg_write(RMSTPCR7, 0xFFFFFFFFU);
195 cpg_write(RMSTPCR8, 0x00F1FFF7U);
196 cpg_write(RMSTPCR9, 0xFFFFFFFFU);
197 cpg_write(RMSTPCR10, 0xFFFFFFE0U);
198 cpg_write(RMSTPCR11, 0x000000B7U);
199}
200
201static void bl2_system_cpg_init_m3n(void)
202{
203 /* System Module Stop Control Registers */
204 cpg_write(SMSTPCR0, 0x00210000U);
205 cpg_write(SMSTPCR1, 0xFFFFFFFFU);
206 cpg_write(SMSTPCR2, 0x040E2FDCU);
207 cpg_write(SMSTPCR3, 0xFFFFFBDFU);
208 cpg_write(SMSTPCR4, 0x80000004U);
209 cpg_write(SMSTPCR5, 0xC3FFFFFFU);
210 cpg_write(SMSTPCR6, 0xFFFFFFFFU);
211 cpg_write(SMSTPCR7, 0xFFFFFFFFU);
212 cpg_write(SMSTPCR8, 0x00F1FFF7U);
213 cpg_write(SMSTPCR9, 0xFFFFFFFFU);
214 cpg_write(SMSTPCR10, 0xFFFFFFE0U);
215 cpg_write(SMSTPCR11, 0x000000B7U);
216}
217#endif
218
Marek Vasut2b9b0fc2019-01-05 13:57:16 +0100219#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_E3)
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200220static void bl2_realtime_cpg_init_e3(void)
221{
222 /* Realtime Module Stop Control Registers */
223 cpg_write(RMSTPCR0, 0x00210000U);
224 cpg_write(RMSTPCR1, 0xFFFFFFFFU);
225 cpg_write(RMSTPCR2, 0x000E0FDCU);
226 cpg_write(RMSTPCR3, 0xFFFFFFDFU);
227 cpg_write(RMSTPCR4, 0x80000004U);
228 cpg_write(RMSTPCR5, 0xC3FFFFFFU);
229 cpg_write(RMSTPCR6, 0xFFFFFFFFU);
230 cpg_write(RMSTPCR7, 0xFFFFFFFFU);
231 cpg_write(RMSTPCR8, 0x00F1FFF7U);
232 cpg_write(RMSTPCR9, 0xFFFFFFDFU);
233 cpg_write(RMSTPCR10, 0xFFFFFFE8U);
234 cpg_write(RMSTPCR11, 0x000000B7U);
235}
236
237static void bl2_system_cpg_init_e3(void)
238{
239 /* System Module Stop Control Registers */
240 cpg_write(SMSTPCR0, 0x00210000U);
241 cpg_write(SMSTPCR1, 0xFFFFFFFFU);
242 cpg_write(SMSTPCR2, 0x000E2FDCU);
243 cpg_write(SMSTPCR3, 0xFFFFFBDFU);
244 cpg_write(SMSTPCR4, 0x80000004U);
245 cpg_write(SMSTPCR5, 0xC3FFFFFFU);
246 cpg_write(SMSTPCR6, 0xFFFFFFFFU);
247 cpg_write(SMSTPCR7, 0xFFFFFFFFU);
248 cpg_write(SMSTPCR8, 0x00F1FFF7U);
249 cpg_write(SMSTPCR9, 0xFFFFFFDFU);
250 cpg_write(SMSTPCR10, 0xFFFFFFE8U);
251 cpg_write(SMSTPCR11, 0x000000B7U);
252}
253#endif
254
Marek Vasut4ae342c2019-01-05 13:56:03 +0100255#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_D3)
256static void bl2_realtime_cpg_init_d3(void)
257{
258 /* Realtime Module Stop Control Registers */
259 cpg_write(RMSTPCR0, 0x00010000U);
260 cpg_write(RMSTPCR1, 0xFFFFFFFFU);
261 cpg_write(RMSTPCR2, 0x00060FDCU);
262 cpg_write(RMSTPCR3, 0xFFFFFFDFU);
263 cpg_write(RMSTPCR4, 0x80000184U);
264 cpg_write(RMSTPCR5, 0x83FFFFFFU);
265 cpg_write(RMSTPCR6, 0xFFFFFFFFU);
266 cpg_write(RMSTPCR7, 0xFFFFFFFFU);
267 cpg_write(RMSTPCR8, 0x00F1FFF7U);
268 cpg_write(RMSTPCR9, 0xF3F5E016U);
269 cpg_write(RMSTPCR10, 0xFFFEFFE0U);
270 cpg_write(RMSTPCR11, 0x000000B7U);
271}
272
273static void bl2_system_cpg_init_d3(void)
274{
275 /* System Module Stop Control Registers */
276 cpg_write(SMSTPCR0, 0x00010000U);
277 cpg_write(SMSTPCR1, 0xFFFFFFFFU);
278 cpg_write(SMSTPCR2, 0x00060FDCU);
279 cpg_write(SMSTPCR3, 0xFFFFFBDFU);
280 cpg_write(SMSTPCR4, 0x00000084U);
281 cpg_write(SMSTPCR5, 0x83FFFFFFU);
282 cpg_write(SMSTPCR6, 0xFFFFFFFFU);
283 cpg_write(SMSTPCR7, 0xFFFFFFFFU);
284 cpg_write(SMSTPCR8, 0x00F1FFF7U);
285 cpg_write(SMSTPCR9, 0xF3F5E016U);
286 cpg_write(SMSTPCR10, 0xFFFEFFE0U);
287 cpg_write(SMSTPCR11, 0x000000B7U);
288}
289#endif
290
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200291void bl2_cpg_init(void)
292{
293 uint32_t boot_cpu = mmio_read_32(RCAR_MODEMR) & MODEMR_BOOT_CPU_MASK;
294#if RCAR_LSI == RCAR_AUTO
295 uint32_t product = mmio_read_32(RCAR_PRR) & RCAR_PRODUCT_MASK;
296#endif
297 bl2_secure_cpg_init();
298
299 if (boot_cpu == MODEMR_BOOT_CPU_CA57 ||
300 boot_cpu == MODEMR_BOOT_CPU_CA53) {
301#if RCAR_LSI == RCAR_AUTO
302
303 switch (product) {
304 case RCAR_PRODUCT_H3:
305 bl2_realtime_cpg_init_h3();
306 break;
307 case RCAR_PRODUCT_M3:
308 bl2_realtime_cpg_init_m3();
309 break;
310 case RCAR_PRODUCT_M3N:
311 bl2_realtime_cpg_init_m3n();
312 break;
Marek Vasut2b9b0fc2019-01-05 13:57:16 +0100313 case RCAR_PRODUCT_E3:
314 bl2_realtime_cpg_init_e3();
315 break;
Marek Vasut4ae342c2019-01-05 13:56:03 +0100316 case RCAR_PRODUCT_D3:
317 bl2_realtime_cpg_init_d3();
318 break;
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200319 default:
320 panic();
321 break;
322 }
323#elif (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N)
324 bl2_realtime_cpg_init_h3();
325#elif RCAR_LSI == RCAR_M3
326 bl2_realtime_cpg_init_m3();
327#elif RCAR_LSI == RCAR_M3N
328 bl2_realtime_cpg_init_m3n();
329#elif RCAR_LSI == RCAR_E3
330 bl2_realtime_cpg_init_e3();
Marek Vasut4ae342c2019-01-05 13:56:03 +0100331#elif RCAR_LSI == RCAR_D3
332 bl2_realtime_cpg_init_d3();
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200333#else
334#error "Don't have CPG initialize routine(unknown)."
335#endif
336 }
337}
338
339void bl2_system_cpg_init(void)
340{
341#if RCAR_LSI == RCAR_AUTO
342 uint32_t product = mmio_read_32(RCAR_PRR) & RCAR_PRODUCT_MASK;
343
344 switch (product) {
345 case RCAR_PRODUCT_H3:
346 bl2_system_cpg_init_h3();
347 break;
348 case RCAR_PRODUCT_M3:
349 bl2_system_cpg_init_m3();
350 break;
351 case RCAR_PRODUCT_M3N:
352 bl2_system_cpg_init_m3n();
353 break;
Marek Vasut2b9b0fc2019-01-05 13:57:16 +0100354 case RCAR_PRODUCT_E3:
355 bl2_system_cpg_init_e3();
356 break;
Marek Vasut4ae342c2019-01-05 13:56:03 +0100357 case RCAR_PRODUCT_D3:
358 bl2_system_cpg_init_d3();
359 break;
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200360 default:
361 panic();
362 break;
363 }
364#elif (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N)
365 bl2_system_cpg_init_h3();
366#elif RCAR_LSI == RCAR_M3
367 bl2_system_cpg_init_m3();
368#elif RCAR_LSI == RCAR_M3N
369 bl2_system_cpg_init_m3n();
370#elif RCAR_LSI == RCAR_E3
371 bl2_system_cpg_init_e3();
Marek Vasut4ae342c2019-01-05 13:56:03 +0100372#elif RCAR_LSI == RCAR_D3
373 bl2_system_cpg_init_d3();
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200374#else
375#error "Don't have CPG initialize routine(unknown)."
376#endif
377}