Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 1 | /* |
Jit Loon Lim | 86f6fb3 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 2 | * Copyright (c) 2019-2023, ARM Limited and Contributors. All rights reserved. |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <assert.h> |
| 8 | #include <common/debug.h> |
| 9 | #include <common/runtime_svc.h> |
Hadi Asyrafi | 6794230 | 2019-10-22 13:28:51 +0800 | [diff] [blame] | 10 | #include <lib/mmio.h> |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 11 | #include <tools_share/uuid.h> |
| 12 | |
Sieu Mun Tang | 9f22cbf | 2022-03-02 11:04:09 +0800 | [diff] [blame] | 13 | #include "socfpga_fcs.h" |
Hadi Asyrafi | 6f8a2b2 | 2019-10-23 18:34:14 +0800 | [diff] [blame] | 14 | #include "socfpga_mailbox.h" |
Jit Loon Lim | 86f6fb3 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 15 | #include "socfpga_plat_def.h" |
Hadi Asyrafi | 36a9f30 | 2019-12-24 10:42:52 +0800 | [diff] [blame] | 16 | #include "socfpga_reset_manager.h" |
Hadi Asyrafi | ab1132f | 2019-10-22 10:31:45 +0800 | [diff] [blame] | 17 | #include "socfpga_sip_svc.h" |
Jit Loon Lim | 86f6fb3 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 18 | #include "socfpga_system_manager.h" |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 19 | |
| 20 | /* Total buffer the driver can hold */ |
| 21 | #define FPGA_CONFIG_BUFFER_SIZE 4 |
| 22 | |
Sieu Mun Tang | c366760 | 2022-05-13 14:55:05 +0800 | [diff] [blame] | 23 | static config_type request_type = NO_REQUEST; |
Abdul Halim, Muhammad Hadi Asyrafi | 20a07f3 | 2020-05-18 11:16:48 +0800 | [diff] [blame] | 24 | static int current_block, current_buffer; |
Abdul Halim, Muhammad Hadi Asyrafi | b251c33 | 2020-05-29 12:13:17 +0800 | [diff] [blame] | 25 | static int read_block, max_blocks; |
Abdul Halim, Muhammad Hadi Asyrafi | 20a07f3 | 2020-05-18 11:16:48 +0800 | [diff] [blame] | 26 | static uint32_t send_id, rcv_id; |
| 27 | static uint32_t bytes_per_block, blocks_submitted; |
Sieu Mun Tang | 5406498 | 2022-04-28 22:40:58 +0800 | [diff] [blame] | 28 | static bool bridge_disable; |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 29 | |
Sieu Mun Tang | e6d5de9 | 2022-04-28 22:21:01 +0800 | [diff] [blame] | 30 | /* RSU static variables */ |
Chee Hong Ang | 2cfd8ec | 2020-05-13 11:44:04 +0800 | [diff] [blame] | 31 | static uint32_t rsu_dcmf_ver[4] = {0}; |
Sieu Mun Tang | e6d5de9 | 2022-04-28 22:21:01 +0800 | [diff] [blame] | 32 | static uint16_t rsu_dcmf_stat[4] = {0}; |
Sieu Mun Tang | c366760 | 2022-05-13 14:55:05 +0800 | [diff] [blame] | 33 | static uint32_t rsu_max_retry; |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 34 | |
| 35 | /* SiP Service UUID */ |
| 36 | DEFINE_SVC_UUID2(intl_svc_uid, |
| 37 | 0xa85273b0, 0xe85a, 0x4862, 0xa6, 0x2a, |
| 38 | 0xfa, 0x88, 0x88, 0x17, 0x68, 0x81); |
| 39 | |
Hadi Asyrafi | cee6aa9 | 2019-12-17 15:25:04 +0800 | [diff] [blame] | 40 | static uint64_t socfpga_sip_handler(uint32_t smc_fid, |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 41 | uint64_t x1, |
| 42 | uint64_t x2, |
| 43 | uint64_t x3, |
| 44 | uint64_t x4, |
| 45 | void *cookie, |
| 46 | void *handle, |
| 47 | uint64_t flags) |
| 48 | { |
| 49 | ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); |
| 50 | SMC_RET1(handle, SMC_UNK); |
| 51 | } |
| 52 | |
| 53 | struct fpga_config_info fpga_config_buffers[FPGA_CONFIG_BUFFER_SIZE]; |
| 54 | |
Hadi Asyrafi | f3a7c14 | 2019-11-12 16:29:03 +0800 | [diff] [blame] | 55 | static int intel_fpga_sdm_write_buffer(struct fpga_config_info *buffer) |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 56 | { |
Abdul Halim, Muhammad Hadi Asyrafi | d84bfef | 2020-02-25 16:28:10 +0800 | [diff] [blame] | 57 | uint32_t args[3]; |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 58 | |
| 59 | while (max_blocks > 0 && buffer->size > buffer->size_written) { |
Hadi Asyrafi | f3a7c14 | 2019-11-12 16:29:03 +0800 | [diff] [blame] | 60 | args[0] = (1<<8); |
| 61 | args[1] = buffer->addr + buffer->size_written; |
| 62 | if (buffer->size - buffer->size_written <= bytes_per_block) { |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 63 | args[2] = buffer->size - buffer->size_written; |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 64 | current_buffer++; |
| 65 | current_buffer %= FPGA_CONFIG_BUFFER_SIZE; |
Sieu Mun Tang | 28af165 | 2022-05-09 10:48:53 +0800 | [diff] [blame] | 66 | } else { |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 67 | args[2] = bytes_per_block; |
Sieu Mun Tang | 28af165 | 2022-05-09 10:48:53 +0800 | [diff] [blame] | 68 | } |
Hadi Asyrafi | f3a7c14 | 2019-11-12 16:29:03 +0800 | [diff] [blame] | 69 | |
| 70 | buffer->size_written += args[2]; |
Abdul Halim, Muhammad Hadi Asyrafi | 20a07f3 | 2020-05-18 11:16:48 +0800 | [diff] [blame] | 71 | mailbox_send_cmd_async(&send_id, MBOX_RECONFIG_DATA, args, |
Abdul Halim, Muhammad Hadi Asyrafi | 118ab21 | 2020-10-15 15:27:18 +0800 | [diff] [blame] | 72 | 3U, CMD_INDIRECT); |
Hadi Asyrafi | f3a7c14 | 2019-11-12 16:29:03 +0800 | [diff] [blame] | 73 | |
| 74 | buffer->subblocks_sent++; |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 75 | max_blocks--; |
| 76 | } |
Hadi Asyrafi | f3a7c14 | 2019-11-12 16:29:03 +0800 | [diff] [blame] | 77 | |
| 78 | return !max_blocks; |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 79 | } |
| 80 | |
| 81 | static int intel_fpga_sdm_write_all(void) |
| 82 | { |
Sieu Mun Tang | 28af165 | 2022-05-09 10:48:53 +0800 | [diff] [blame] | 83 | for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { |
Hadi Asyrafi | f3a7c14 | 2019-11-12 16:29:03 +0800 | [diff] [blame] | 84 | if (intel_fpga_sdm_write_buffer( |
Sieu Mun Tang | 28af165 | 2022-05-09 10:48:53 +0800 | [diff] [blame] | 85 | &fpga_config_buffers[current_buffer])) { |
Hadi Asyrafi | f3a7c14 | 2019-11-12 16:29:03 +0800 | [diff] [blame] | 86 | break; |
Sieu Mun Tang | 28af165 | 2022-05-09 10:48:53 +0800 | [diff] [blame] | 87 | } |
| 88 | } |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 89 | return 0; |
| 90 | } |
| 91 | |
Sieu Mun Tang | c366760 | 2022-05-13 14:55:05 +0800 | [diff] [blame] | 92 | static uint32_t intel_mailbox_fpga_config_isdone(void) |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 93 | { |
Hadi Asyrafi | 0c6dae2 | 2019-12-17 23:33:39 +0800 | [diff] [blame] | 94 | uint32_t ret; |
| 95 | |
Sieu Mun Tang | c366760 | 2022-05-13 14:55:05 +0800 | [diff] [blame] | 96 | switch (request_type) { |
| 97 | case RECONFIGURATION: |
| 98 | ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, |
| 99 | true); |
| 100 | break; |
| 101 | case BITSTREAM_AUTH: |
| 102 | ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, |
| 103 | false); |
| 104 | break; |
| 105 | default: |
| 106 | ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS, |
| 107 | false); |
| 108 | break; |
Kris Chaplin | e768dfa | 2021-06-25 11:31:52 +0100 | [diff] [blame] | 109 | } |
Hadi Asyrafi | f3a7c14 | 2019-11-12 16:29:03 +0800 | [diff] [blame] | 110 | |
Abdul Halim, Muhammad Hadi Asyrafi | 959143d | 2020-12-29 16:49:23 +0800 | [diff] [blame] | 111 | if (ret != 0U) { |
Kris Chaplin | e768dfa | 2021-06-25 11:31:52 +0100 | [diff] [blame] | 112 | if (ret == MBOX_CFGSTAT_STATE_CONFIG) { |
Hadi Asyrafi | f3a7c14 | 2019-11-12 16:29:03 +0800 | [diff] [blame] | 113 | return INTEL_SIP_SMC_STATUS_BUSY; |
Kris Chaplin | e768dfa | 2021-06-25 11:31:52 +0100 | [diff] [blame] | 114 | } else { |
Sieu Mun Tang | c366760 | 2022-05-13 14:55:05 +0800 | [diff] [blame] | 115 | request_type = NO_REQUEST; |
Hadi Asyrafi | f3a7c14 | 2019-11-12 16:29:03 +0800 | [diff] [blame] | 116 | return INTEL_SIP_SMC_STATUS_ERROR; |
Kris Chaplin | e768dfa | 2021-06-25 11:31:52 +0100 | [diff] [blame] | 117 | } |
Hadi Asyrafi | f3a7c14 | 2019-11-12 16:29:03 +0800 | [diff] [blame] | 118 | } |
| 119 | |
Sieu Mun Tang | c366760 | 2022-05-13 14:55:05 +0800 | [diff] [blame] | 120 | if (bridge_disable != 0U) { |
Sieu Mun Tang | 82cf5df | 2022-05-05 17:07:21 +0800 | [diff] [blame] | 121 | socfpga_bridges_enable(~0); /* Enable bridge */ |
Sieu Mun Tang | 5406498 | 2022-04-28 22:40:58 +0800 | [diff] [blame] | 122 | bridge_disable = false; |
Hadi Asyrafi | 36a9f30 | 2019-12-24 10:42:52 +0800 | [diff] [blame] | 123 | } |
Sieu Mun Tang | c366760 | 2022-05-13 14:55:05 +0800 | [diff] [blame] | 124 | request_type = NO_REQUEST; |
Hadi Asyrafi | 36a9f30 | 2019-12-24 10:42:52 +0800 | [diff] [blame] | 125 | |
Hadi Asyrafi | f3a7c14 | 2019-11-12 16:29:03 +0800 | [diff] [blame] | 126 | return INTEL_SIP_SMC_STATUS_OK; |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 127 | } |
| 128 | |
| 129 | static int mark_last_buffer_xfer_completed(uint32_t *buffer_addr_completed) |
| 130 | { |
| 131 | int i; |
| 132 | |
| 133 | for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { |
| 134 | if (fpga_config_buffers[i].block_number == current_block) { |
| 135 | fpga_config_buffers[i].subblocks_sent--; |
| 136 | if (fpga_config_buffers[i].subblocks_sent == 0 |
| 137 | && fpga_config_buffers[i].size <= |
| 138 | fpga_config_buffers[i].size_written) { |
| 139 | fpga_config_buffers[i].write_requested = 0; |
| 140 | current_block++; |
| 141 | *buffer_addr_completed = |
| 142 | fpga_config_buffers[i].addr; |
| 143 | return 0; |
| 144 | } |
| 145 | } |
| 146 | } |
| 147 | |
| 148 | return -1; |
| 149 | } |
| 150 | |
Hadi Asyrafi | cee6aa9 | 2019-12-17 15:25:04 +0800 | [diff] [blame] | 151 | static int intel_fpga_config_completed_write(uint32_t *completed_addr, |
Abdul Halim, Muhammad Hadi Asyrafi | 20a07f3 | 2020-05-18 11:16:48 +0800 | [diff] [blame] | 152 | uint32_t *count, uint32_t *job_id) |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 153 | { |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 154 | uint32_t resp[5]; |
Sieu Mun Tang | 2468266 | 2022-02-19 21:49:48 +0800 | [diff] [blame] | 155 | unsigned int resp_len = ARRAY_SIZE(resp); |
| 156 | int status = INTEL_SIP_SMC_STATUS_OK; |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 157 | int all_completed = 1; |
Sieu Mun Tang | 2468266 | 2022-02-19 21:49:48 +0800 | [diff] [blame] | 158 | *count = 0; |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 159 | |
Tien Hock, Loh | 500b232 | 2019-10-30 14:49:40 +0800 | [diff] [blame] | 160 | while (*count < 3) { |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 161 | |
Sieu Mun Tang | 2468266 | 2022-02-19 21:49:48 +0800 | [diff] [blame] | 162 | status = mailbox_read_response(job_id, |
| 163 | resp, &resp_len); |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 164 | |
Sieu Mun Tang | 9f22cbf | 2022-03-02 11:04:09 +0800 | [diff] [blame] | 165 | if (status < 0) { |
Tien Hock, Loh | 500b232 | 2019-10-30 14:49:40 +0800 | [diff] [blame] | 166 | break; |
Sieu Mun Tang | 9f22cbf | 2022-03-02 11:04:09 +0800 | [diff] [blame] | 167 | } |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 168 | |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 169 | max_blocks++; |
Tien Hock, Loh | 500b232 | 2019-10-30 14:49:40 +0800 | [diff] [blame] | 170 | |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 171 | if (mark_last_buffer_xfer_completed( |
Sieu Mun Tang | 9f22cbf | 2022-03-02 11:04:09 +0800 | [diff] [blame] | 172 | &completed_addr[*count]) == 0) { |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 173 | *count = *count + 1; |
Sieu Mun Tang | 9f22cbf | 2022-03-02 11:04:09 +0800 | [diff] [blame] | 174 | } else { |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 175 | break; |
Sieu Mun Tang | 9f22cbf | 2022-03-02 11:04:09 +0800 | [diff] [blame] | 176 | } |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 177 | } |
| 178 | |
| 179 | if (*count <= 0) { |
Sieu Mun Tang | 9f22cbf | 2022-03-02 11:04:09 +0800 | [diff] [blame] | 180 | if (status != MBOX_NO_RESPONSE && |
| 181 | status != MBOX_TIMEOUT && resp_len != 0) { |
Tien Hock, Loh | 500b232 | 2019-10-30 14:49:40 +0800 | [diff] [blame] | 182 | mailbox_clear_response(); |
Sieu Mun Tang | c366760 | 2022-05-13 14:55:05 +0800 | [diff] [blame] | 183 | request_type = NO_REQUEST; |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 184 | return INTEL_SIP_SMC_STATUS_ERROR; |
| 185 | } |
| 186 | |
| 187 | *count = 0; |
| 188 | } |
| 189 | |
| 190 | intel_fpga_sdm_write_all(); |
| 191 | |
Sieu Mun Tang | 28af165 | 2022-05-09 10:48:53 +0800 | [diff] [blame] | 192 | if (*count > 0) { |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 193 | status = INTEL_SIP_SMC_STATUS_OK; |
Sieu Mun Tang | 28af165 | 2022-05-09 10:48:53 +0800 | [diff] [blame] | 194 | } else if (*count == 0) { |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 195 | status = INTEL_SIP_SMC_STATUS_BUSY; |
Sieu Mun Tang | 28af165 | 2022-05-09 10:48:53 +0800 | [diff] [blame] | 196 | } |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 197 | |
| 198 | for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { |
| 199 | if (fpga_config_buffers[i].write_requested != 0) { |
| 200 | all_completed = 0; |
| 201 | break; |
| 202 | } |
| 203 | } |
| 204 | |
Sieu Mun Tang | 28af165 | 2022-05-09 10:48:53 +0800 | [diff] [blame] | 205 | if (all_completed == 1) { |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 206 | return INTEL_SIP_SMC_STATUS_OK; |
Sieu Mun Tang | 28af165 | 2022-05-09 10:48:53 +0800 | [diff] [blame] | 207 | } |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 208 | |
| 209 | return status; |
| 210 | } |
| 211 | |
Sieu Mun Tang | 5406498 | 2022-04-28 22:40:58 +0800 | [diff] [blame] | 212 | static int intel_fpga_config_start(uint32_t flag) |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 213 | { |
Sieu Mun Tang | 2468266 | 2022-02-19 21:49:48 +0800 | [diff] [blame] | 214 | uint32_t argument = 0x1; |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 215 | uint32_t response[3]; |
| 216 | int status = 0; |
Sieu Mun Tang | 2468266 | 2022-02-19 21:49:48 +0800 | [diff] [blame] | 217 | unsigned int size = 0; |
| 218 | unsigned int resp_len = ARRAY_SIZE(response); |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 219 | |
Sieu Mun Tang | c366760 | 2022-05-13 14:55:05 +0800 | [diff] [blame] | 220 | request_type = RECONFIGURATION; |
| 221 | |
Sieu Mun Tang | 5406498 | 2022-04-28 22:40:58 +0800 | [diff] [blame] | 222 | if (!CONFIG_TEST_FLAG(flag, PARTIAL_CONFIG)) { |
| 223 | bridge_disable = true; |
Abdul Halim, Muhammad Hadi Asyrafi | b251c33 | 2020-05-29 12:13:17 +0800 | [diff] [blame] | 224 | } |
Hadi Asyrafi | 36a9f30 | 2019-12-24 10:42:52 +0800 | [diff] [blame] | 225 | |
Sieu Mun Tang | 5406498 | 2022-04-28 22:40:58 +0800 | [diff] [blame] | 226 | if (CONFIG_TEST_FLAG(flag, AUTHENTICATION)) { |
| 227 | size = 1; |
| 228 | bridge_disable = false; |
Sieu Mun Tang | c366760 | 2022-05-13 14:55:05 +0800 | [diff] [blame] | 229 | request_type = BITSTREAM_AUTH; |
Sieu Mun Tang | 5406498 | 2022-04-28 22:40:58 +0800 | [diff] [blame] | 230 | } |
| 231 | |
Tien Hock, Loh | 500b232 | 2019-10-30 14:49:40 +0800 | [diff] [blame] | 232 | mailbox_clear_response(); |
| 233 | |
Sieu Mun Tang | 2468266 | 2022-02-19 21:49:48 +0800 | [diff] [blame] | 234 | mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_CANCEL, NULL, 0U, |
| 235 | CMD_CASUAL, NULL, NULL); |
Tien Hock, Loh | 500b232 | 2019-10-30 14:49:40 +0800 | [diff] [blame] | 236 | |
Sieu Mun Tang | 2468266 | 2022-02-19 21:49:48 +0800 | [diff] [blame] | 237 | status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_RECONFIG, &argument, size, |
| 238 | CMD_CASUAL, response, &resp_len); |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 239 | |
Abdul Halim, Muhammad Hadi Asyrafi | fbc3913 | 2020-11-20 11:06:00 +0800 | [diff] [blame] | 240 | if (status < 0) { |
Sieu Mun Tang | 5406498 | 2022-04-28 22:40:58 +0800 | [diff] [blame] | 241 | bridge_disable = false; |
Sieu Mun Tang | c366760 | 2022-05-13 14:55:05 +0800 | [diff] [blame] | 242 | request_type = NO_REQUEST; |
Abdul Halim, Muhammad Hadi Asyrafi | fbc3913 | 2020-11-20 11:06:00 +0800 | [diff] [blame] | 243 | return INTEL_SIP_SMC_STATUS_ERROR; |
| 244 | } |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 245 | |
| 246 | max_blocks = response[0]; |
| 247 | bytes_per_block = response[1]; |
| 248 | |
| 249 | for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { |
| 250 | fpga_config_buffers[i].size = 0; |
| 251 | fpga_config_buffers[i].size_written = 0; |
| 252 | fpga_config_buffers[i].addr = 0; |
| 253 | fpga_config_buffers[i].write_requested = 0; |
| 254 | fpga_config_buffers[i].block_number = 0; |
| 255 | fpga_config_buffers[i].subblocks_sent = 0; |
| 256 | } |
| 257 | |
| 258 | blocks_submitted = 0; |
| 259 | current_block = 0; |
Tien Hock, Loh | 500b232 | 2019-10-30 14:49:40 +0800 | [diff] [blame] | 260 | read_block = 0; |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 261 | current_buffer = 0; |
| 262 | |
Sieu Mun Tang | 5406498 | 2022-04-28 22:40:58 +0800 | [diff] [blame] | 263 | /* Disable bridge on full reconfiguration */ |
| 264 | if (bridge_disable) { |
Sieu Mun Tang | 82cf5df | 2022-05-05 17:07:21 +0800 | [diff] [blame] | 265 | socfpga_bridges_disable(~0); |
Hadi Asyrafi | 36a9f30 | 2019-12-24 10:42:52 +0800 | [diff] [blame] | 266 | } |
| 267 | |
Abdul Halim, Muhammad Hadi Asyrafi | fbc3913 | 2020-11-20 11:06:00 +0800 | [diff] [blame] | 268 | return INTEL_SIP_SMC_STATUS_OK; |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 269 | } |
| 270 | |
Hadi Asyrafi | f3a7c14 | 2019-11-12 16:29:03 +0800 | [diff] [blame] | 271 | static bool is_fpga_config_buffer_full(void) |
| 272 | { |
Sieu Mun Tang | 28af165 | 2022-05-09 10:48:53 +0800 | [diff] [blame] | 273 | for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { |
| 274 | if (!fpga_config_buffers[i].write_requested) { |
Hadi Asyrafi | f3a7c14 | 2019-11-12 16:29:03 +0800 | [diff] [blame] | 275 | return false; |
Sieu Mun Tang | 28af165 | 2022-05-09 10:48:53 +0800 | [diff] [blame] | 276 | } |
| 277 | } |
Hadi Asyrafi | f3a7c14 | 2019-11-12 16:29:03 +0800 | [diff] [blame] | 278 | return true; |
| 279 | } |
| 280 | |
Abdul Halim, Muhammad Hadi Asyrafi | 20a07f3 | 2020-05-18 11:16:48 +0800 | [diff] [blame] | 281 | bool is_address_in_ddr_range(uint64_t addr, uint64_t size) |
Hadi Asyrafi | f3a7c14 | 2019-11-12 16:29:03 +0800 | [diff] [blame] | 282 | { |
Abdul Halim, Muhammad Hadi Asyrafi | 461f544 | 2020-07-03 13:22:09 +0800 | [diff] [blame] | 283 | if (!addr && !size) { |
| 284 | return true; |
| 285 | } |
Sieu Mun Tang | 28af165 | 2022-05-09 10:48:53 +0800 | [diff] [blame] | 286 | if (size > (UINT64_MAX - addr)) { |
Abdul Halim, Muhammad Hadi Asyrafi | c39a0e0 | 2020-02-06 19:18:41 +0800 | [diff] [blame] | 287 | return false; |
Sieu Mun Tang | 28af165 | 2022-05-09 10:48:53 +0800 | [diff] [blame] | 288 | } |
| 289 | if (addr < BL31_LIMIT) { |
Abdul Halim, Muhammad Hadi Asyrafi | c39a0e0 | 2020-02-06 19:18:41 +0800 | [diff] [blame] | 290 | return false; |
Sieu Mun Tang | 28af165 | 2022-05-09 10:48:53 +0800 | [diff] [blame] | 291 | } |
| 292 | if (addr + size > DRAM_BASE + DRAM_SIZE) { |
Abdul Halim, Muhammad Hadi Asyrafi | c39a0e0 | 2020-02-06 19:18:41 +0800 | [diff] [blame] | 293 | return false; |
Sieu Mun Tang | 28af165 | 2022-05-09 10:48:53 +0800 | [diff] [blame] | 294 | } |
Hadi Asyrafi | f3a7c14 | 2019-11-12 16:29:03 +0800 | [diff] [blame] | 295 | |
Abdul Halim, Muhammad Hadi Asyrafi | c39a0e0 | 2020-02-06 19:18:41 +0800 | [diff] [blame] | 296 | return true; |
Hadi Asyrafi | f3a7c14 | 2019-11-12 16:29:03 +0800 | [diff] [blame] | 297 | } |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 298 | |
Hadi Asyrafi | cee6aa9 | 2019-12-17 15:25:04 +0800 | [diff] [blame] | 299 | static uint32_t intel_fpga_config_write(uint64_t mem, uint64_t size) |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 300 | { |
Hadi Asyrafi | f3a7c14 | 2019-11-12 16:29:03 +0800 | [diff] [blame] | 301 | int i; |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 302 | |
Hadi Asyrafi | f3a7c14 | 2019-11-12 16:29:03 +0800 | [diff] [blame] | 303 | intel_fpga_sdm_write_all(); |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 304 | |
Abdul Halim, Muhammad Hadi Asyrafi | c39a0e0 | 2020-02-06 19:18:41 +0800 | [diff] [blame] | 305 | if (!is_address_in_ddr_range(mem, size) || |
Abdul Halim, Muhammad Hadi Asyrafi | 351e884 | 2020-11-05 18:00:03 +0800 | [diff] [blame] | 306 | is_fpga_config_buffer_full()) { |
Hadi Asyrafi | f3a7c14 | 2019-11-12 16:29:03 +0800 | [diff] [blame] | 307 | return INTEL_SIP_SMC_STATUS_REJECTED; |
Abdul Halim, Muhammad Hadi Asyrafi | 351e884 | 2020-11-05 18:00:03 +0800 | [diff] [blame] | 308 | } |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 309 | |
| 310 | for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { |
Hadi Asyrafi | f3a7c14 | 2019-11-12 16:29:03 +0800 | [diff] [blame] | 311 | int j = (i + current_buffer) % FPGA_CONFIG_BUFFER_SIZE; |
| 312 | |
| 313 | if (!fpga_config_buffers[j].write_requested) { |
| 314 | fpga_config_buffers[j].addr = mem; |
| 315 | fpga_config_buffers[j].size = size; |
| 316 | fpga_config_buffers[j].size_written = 0; |
| 317 | fpga_config_buffers[j].write_requested = 1; |
| 318 | fpga_config_buffers[j].block_number = |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 319 | blocks_submitted++; |
Hadi Asyrafi | f3a7c14 | 2019-11-12 16:29:03 +0800 | [diff] [blame] | 320 | fpga_config_buffers[j].subblocks_sent = 0; |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 321 | break; |
| 322 | } |
| 323 | } |
| 324 | |
Abdul Halim, Muhammad Hadi Asyrafi | 351e884 | 2020-11-05 18:00:03 +0800 | [diff] [blame] | 325 | if (is_fpga_config_buffer_full()) { |
Hadi Asyrafi | f3a7c14 | 2019-11-12 16:29:03 +0800 | [diff] [blame] | 326 | return INTEL_SIP_SMC_STATUS_BUSY; |
Abdul Halim, Muhammad Hadi Asyrafi | 351e884 | 2020-11-05 18:00:03 +0800 | [diff] [blame] | 327 | } |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 328 | |
Hadi Asyrafi | f3a7c14 | 2019-11-12 16:29:03 +0800 | [diff] [blame] | 329 | return INTEL_SIP_SMC_STATUS_OK; |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 330 | } |
| 331 | |
Hadi Asyrafi | 6794230 | 2019-10-22 13:28:51 +0800 | [diff] [blame] | 332 | static int is_out_of_sec_range(uint64_t reg_addr) |
| 333 | { |
Siew Chin Lim | 869d4f5 | 2021-05-11 21:12:22 +0800 | [diff] [blame] | 334 | #if DEBUG |
| 335 | return 0; |
| 336 | #endif |
| 337 | |
Hadi Asyrafi | 6794230 | 2019-10-22 13:28:51 +0800 | [diff] [blame] | 338 | switch (reg_addr) { |
| 339 | case(0xF8011100): /* ECCCTRL1 */ |
| 340 | case(0xF8011104): /* ECCCTRL2 */ |
| 341 | case(0xF8011110): /* ERRINTEN */ |
| 342 | case(0xF8011114): /* ERRINTENS */ |
| 343 | case(0xF8011118): /* ERRINTENR */ |
| 344 | case(0xF801111C): /* INTMODE */ |
| 345 | case(0xF8011120): /* INTSTAT */ |
| 346 | case(0xF8011124): /* DIAGINTTEST */ |
| 347 | case(0xF801112C): /* DERRADDRA */ |
Sieu Mun Tang | bd8da63 | 2022-09-28 15:58:28 +0800 | [diff] [blame] | 348 | case(0xFA000000): /* SMMU SCR0 */ |
| 349 | case(0xFA000004): /* SMMU SCR1 */ |
| 350 | case(0xFA000400): /* SMMU NSCR0 */ |
| 351 | case(0xFA004000): /* SMMU SSD0_REG */ |
| 352 | case(0xFA000820): /* SMMU SMR8 */ |
| 353 | case(0xFA000c20): /* SMMU SCR8 */ |
| 354 | case(0xFA028000): /* SMMU CB8_SCTRL */ |
| 355 | case(0xFA001020): /* SMMU CBAR8 */ |
| 356 | case(0xFA028030): /* SMMU TCR_LPAE */ |
| 357 | case(0xFA028020): /* SMMU CB8_TTBR0_LOW */ |
| 358 | case(0xFA028024): /* SMMU CB8_PRRR_HIGH */ |
| 359 | case(0xFA028038): /* SMMU CB8_PRRR_MIR0 */ |
| 360 | case(0xFA02803C): /* SMMU CB8_PRRR_MIR1 */ |
| 361 | case(0xFA028010): /* SMMU_CB8)TCR2 */ |
| 362 | case(0xFFD080A4): /* SDM SMMU STREAM ID REG */ |
| 363 | case(0xFA001820): /* SMMU_CBA2R8 */ |
| 364 | case(0xFA000074): /* SMMU_STLBGSTATUS */ |
| 365 | case(0xFA0287F4): /* SMMU_CB8_TLBSTATUS */ |
| 366 | case(0xFA000060): /* SMMU_STLBIALL */ |
| 367 | case(0xFA000070): /* SMMU_STLBGSYNC */ |
| 368 | case(0xFA028618): /* CB8_TLBALL */ |
| 369 | case(0xFA0287F0): /* CB8_TLBSYNC */ |
Hadi Asyrafi | 6794230 | 2019-10-22 13:28:51 +0800 | [diff] [blame] | 370 | case(0xFFD12028): /* SDMMCGRP_CTRL */ |
| 371 | case(0xFFD12044): /* EMAC0 */ |
| 372 | case(0xFFD12048): /* EMAC1 */ |
| 373 | case(0xFFD1204C): /* EMAC2 */ |
| 374 | case(0xFFD12090): /* ECC_INT_MASK_VALUE */ |
| 375 | case(0xFFD12094): /* ECC_INT_MASK_SET */ |
| 376 | case(0xFFD12098): /* ECC_INT_MASK_CLEAR */ |
| 377 | case(0xFFD1209C): /* ECC_INTSTATUS_SERR */ |
| 378 | case(0xFFD120A0): /* ECC_INTSTATUS_DERR */ |
| 379 | case(0xFFD120C0): /* NOC_TIMEOUT */ |
| 380 | case(0xFFD120C4): /* NOC_IDLEREQ_SET */ |
| 381 | case(0xFFD120C8): /* NOC_IDLEREQ_CLR */ |
| 382 | case(0xFFD120D0): /* NOC_IDLEACK */ |
| 383 | case(0xFFD120D4): /* NOC_IDLESTATUS */ |
| 384 | case(0xFFD12200): /* BOOT_SCRATCH_COLD0 */ |
| 385 | case(0xFFD12204): /* BOOT_SCRATCH_COLD1 */ |
| 386 | case(0xFFD12220): /* BOOT_SCRATCH_COLD8 */ |
| 387 | case(0xFFD12224): /* BOOT_SCRATCH_COLD9 */ |
| 388 | return 0; |
| 389 | |
| 390 | default: |
| 391 | break; |
| 392 | } |
| 393 | |
| 394 | return -1; |
| 395 | } |
| 396 | |
| 397 | /* Secure register access */ |
| 398 | uint32_t intel_secure_reg_read(uint64_t reg_addr, uint32_t *retval) |
| 399 | { |
Sieu Mun Tang | 28af165 | 2022-05-09 10:48:53 +0800 | [diff] [blame] | 400 | if (is_out_of_sec_range(reg_addr)) { |
Hadi Asyrafi | 6794230 | 2019-10-22 13:28:51 +0800 | [diff] [blame] | 401 | return INTEL_SIP_SMC_STATUS_ERROR; |
Sieu Mun Tang | 28af165 | 2022-05-09 10:48:53 +0800 | [diff] [blame] | 402 | } |
Hadi Asyrafi | 6794230 | 2019-10-22 13:28:51 +0800 | [diff] [blame] | 403 | |
| 404 | *retval = mmio_read_32(reg_addr); |
| 405 | |
| 406 | return INTEL_SIP_SMC_STATUS_OK; |
| 407 | } |
| 408 | |
| 409 | uint32_t intel_secure_reg_write(uint64_t reg_addr, uint32_t val, |
| 410 | uint32_t *retval) |
| 411 | { |
Sieu Mun Tang | 28af165 | 2022-05-09 10:48:53 +0800 | [diff] [blame] | 412 | if (is_out_of_sec_range(reg_addr)) { |
Hadi Asyrafi | 6794230 | 2019-10-22 13:28:51 +0800 | [diff] [blame] | 413 | return INTEL_SIP_SMC_STATUS_ERROR; |
Sieu Mun Tang | 28af165 | 2022-05-09 10:48:53 +0800 | [diff] [blame] | 414 | } |
Hadi Asyrafi | 6794230 | 2019-10-22 13:28:51 +0800 | [diff] [blame] | 415 | |
| 416 | mmio_write_32(reg_addr, val); |
| 417 | |
| 418 | return intel_secure_reg_read(reg_addr, retval); |
| 419 | } |
| 420 | |
| 421 | uint32_t intel_secure_reg_update(uint64_t reg_addr, uint32_t mask, |
| 422 | uint32_t val, uint32_t *retval) |
| 423 | { |
| 424 | if (!intel_secure_reg_read(reg_addr, retval)) { |
| 425 | *retval &= ~mask; |
Siew Chin Lim | a076315 | 2021-07-10 00:55:35 +0800 | [diff] [blame] | 426 | *retval |= val & mask; |
Hadi Asyrafi | 6794230 | 2019-10-22 13:28:51 +0800 | [diff] [blame] | 427 | return intel_secure_reg_write(reg_addr, *retval, retval); |
| 428 | } |
| 429 | |
| 430 | return INTEL_SIP_SMC_STATUS_ERROR; |
| 431 | } |
| 432 | |
Hadi Asyrafi | 593c4c5 | 2019-12-17 19:22:17 +0800 | [diff] [blame] | 433 | /* Intel Remote System Update (RSU) services */ |
| 434 | uint64_t intel_rsu_update_address; |
| 435 | |
Abdul Halim, Muhammad Hadi Asyrafi | 118ab21 | 2020-10-15 15:27:18 +0800 | [diff] [blame] | 436 | static uint32_t intel_rsu_status(uint64_t *respbuf, unsigned int respbuf_sz) |
Hadi Asyrafi | 593c4c5 | 2019-12-17 19:22:17 +0800 | [diff] [blame] | 437 | { |
Sieu Mun Tang | 28af165 | 2022-05-09 10:48:53 +0800 | [diff] [blame] | 438 | if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) { |
Abdul Halim, Muhammad Hadi Asyrafi | 25f623e | 2020-02-27 10:23:48 +0800 | [diff] [blame] | 439 | return INTEL_SIP_SMC_RSU_ERROR; |
Sieu Mun Tang | 28af165 | 2022-05-09 10:48:53 +0800 | [diff] [blame] | 440 | } |
Hadi Asyrafi | 593c4c5 | 2019-12-17 19:22:17 +0800 | [diff] [blame] | 441 | |
| 442 | return INTEL_SIP_SMC_STATUS_OK; |
| 443 | } |
| 444 | |
| 445 | static uint32_t intel_rsu_update(uint64_t update_address) |
| 446 | { |
| 447 | intel_rsu_update_address = update_address; |
| 448 | return INTEL_SIP_SMC_STATUS_OK; |
| 449 | } |
| 450 | |
Abdul Halim, Muhammad Hadi Asyrafi | d84bfef | 2020-02-25 16:28:10 +0800 | [diff] [blame] | 451 | static uint32_t intel_rsu_notify(uint32_t execution_stage) |
Hadi Asyrafi | 593c4c5 | 2019-12-17 19:22:17 +0800 | [diff] [blame] | 452 | { |
Sieu Mun Tang | 28af165 | 2022-05-09 10:48:53 +0800 | [diff] [blame] | 453 | if (mailbox_hps_stage_notify(execution_stage) < 0) { |
Abdul Halim, Muhammad Hadi Asyrafi | 25f623e | 2020-02-27 10:23:48 +0800 | [diff] [blame] | 454 | return INTEL_SIP_SMC_RSU_ERROR; |
Sieu Mun Tang | 28af165 | 2022-05-09 10:48:53 +0800 | [diff] [blame] | 455 | } |
Hadi Asyrafi | 593c4c5 | 2019-12-17 19:22:17 +0800 | [diff] [blame] | 456 | |
| 457 | return INTEL_SIP_SMC_STATUS_OK; |
| 458 | } |
| 459 | |
| 460 | static uint32_t intel_rsu_retry_counter(uint32_t *respbuf, uint32_t respbuf_sz, |
| 461 | uint32_t *ret_stat) |
| 462 | { |
Sieu Mun Tang | 28af165 | 2022-05-09 10:48:53 +0800 | [diff] [blame] | 463 | if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) { |
Abdul Halim, Muhammad Hadi Asyrafi | 25f623e | 2020-02-27 10:23:48 +0800 | [diff] [blame] | 464 | return INTEL_SIP_SMC_RSU_ERROR; |
Sieu Mun Tang | 28af165 | 2022-05-09 10:48:53 +0800 | [diff] [blame] | 465 | } |
Hadi Asyrafi | 593c4c5 | 2019-12-17 19:22:17 +0800 | [diff] [blame] | 466 | |
| 467 | *ret_stat = respbuf[8]; |
| 468 | return INTEL_SIP_SMC_STATUS_OK; |
| 469 | } |
| 470 | |
Chee Hong Ang | 2cfd8ec | 2020-05-13 11:44:04 +0800 | [diff] [blame] | 471 | static uint32_t intel_rsu_copy_dcmf_version(uint64_t dcmf_ver_1_0, |
| 472 | uint64_t dcmf_ver_3_2) |
| 473 | { |
| 474 | rsu_dcmf_ver[0] = dcmf_ver_1_0; |
| 475 | rsu_dcmf_ver[1] = dcmf_ver_1_0 >> 32; |
| 476 | rsu_dcmf_ver[2] = dcmf_ver_3_2; |
| 477 | rsu_dcmf_ver[3] = dcmf_ver_3_2 >> 32; |
| 478 | |
| 479 | return INTEL_SIP_SMC_STATUS_OK; |
| 480 | } |
| 481 | |
Sieu Mun Tang | e6d5de9 | 2022-04-28 22:21:01 +0800 | [diff] [blame] | 482 | static uint32_t intel_rsu_copy_dcmf_status(uint64_t dcmf_stat) |
| 483 | { |
| 484 | rsu_dcmf_stat[0] = 0xFFFF & (dcmf_stat >> (0 * 16)); |
| 485 | rsu_dcmf_stat[1] = 0xFFFF & (dcmf_stat >> (1 * 16)); |
| 486 | rsu_dcmf_stat[2] = 0xFFFF & (dcmf_stat >> (2 * 16)); |
| 487 | rsu_dcmf_stat[3] = 0xFFFF & (dcmf_stat >> (3 * 16)); |
| 488 | |
| 489 | return INTEL_SIP_SMC_STATUS_OK; |
| 490 | } |
| 491 | |
Kris Chaplin | e768dfa | 2021-06-25 11:31:52 +0100 | [diff] [blame] | 492 | /* Intel HWMON services */ |
| 493 | static uint32_t intel_hwmon_readtemp(uint32_t chan, uint32_t *retval) |
| 494 | { |
Kris Chaplin | e768dfa | 2021-06-25 11:31:52 +0100 | [diff] [blame] | 495 | if (mailbox_hwmon_readtemp(chan, retval) < 0) { |
| 496 | return INTEL_SIP_SMC_STATUS_ERROR; |
| 497 | } |
| 498 | |
| 499 | return INTEL_SIP_SMC_STATUS_OK; |
| 500 | } |
| 501 | |
| 502 | static uint32_t intel_hwmon_readvolt(uint32_t chan, uint32_t *retval) |
| 503 | { |
Kris Chaplin | e768dfa | 2021-06-25 11:31:52 +0100 | [diff] [blame] | 504 | if (mailbox_hwmon_readvolt(chan, retval) < 0) { |
| 505 | return INTEL_SIP_SMC_STATUS_ERROR; |
| 506 | } |
| 507 | |
| 508 | return INTEL_SIP_SMC_STATUS_OK; |
| 509 | } |
| 510 | |
Hadi Asyrafi | a33e810 | 2019-12-17 19:30:41 +0800 | [diff] [blame] | 511 | /* Mailbox services */ |
Abdul Halim, Muhammad Hadi Asyrafi | d9006fc | 2021-02-05 11:50:58 +0800 | [diff] [blame] | 512 | static uint32_t intel_smc_fw_version(uint32_t *fw_version) |
| 513 | { |
Sieu Mun Tang | bfda95a | 2022-04-27 18:54:10 +0800 | [diff] [blame] | 514 | int status; |
| 515 | unsigned int resp_len = CONFIG_STATUS_WORD_SIZE; |
| 516 | uint32_t resp_data[CONFIG_STATUS_WORD_SIZE] = {0U}; |
| 517 | |
| 518 | status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CONFIG_STATUS, NULL, 0U, |
| 519 | CMD_CASUAL, resp_data, &resp_len); |
| 520 | |
| 521 | if (status < 0) { |
| 522 | return INTEL_SIP_SMC_STATUS_ERROR; |
| 523 | } |
| 524 | |
| 525 | if (resp_len <= CONFIG_STATUS_FW_VER_OFFSET) { |
| 526 | return INTEL_SIP_SMC_STATUS_ERROR; |
| 527 | } |
| 528 | |
| 529 | *fw_version = resp_data[CONFIG_STATUS_FW_VER_OFFSET] & CONFIG_STATUS_FW_VER_MASK; |
Abdul Halim, Muhammad Hadi Asyrafi | d9006fc | 2021-02-05 11:50:58 +0800 | [diff] [blame] | 530 | |
| 531 | return INTEL_SIP_SMC_STATUS_OK; |
| 532 | } |
| 533 | |
Sieu Mun Tang | 2468266 | 2022-02-19 21:49:48 +0800 | [diff] [blame] | 534 | static uint32_t intel_mbox_send_cmd(uint32_t cmd, uint32_t *args, |
Sieu Mun Tang | 7420c53 | 2022-05-10 23:17:04 +0800 | [diff] [blame] | 535 | unsigned int len, uint32_t urgent, uint64_t response, |
Sieu Mun Tang | 2468266 | 2022-02-19 21:49:48 +0800 | [diff] [blame] | 536 | unsigned int resp_len, int *mbox_status, |
| 537 | unsigned int *len_in_resp) |
Hadi Asyrafi | a33e810 | 2019-12-17 19:30:41 +0800 | [diff] [blame] | 538 | { |
Abdul Halim, Muhammad Hadi Asyrafi | c39a0e0 | 2020-02-06 19:18:41 +0800 | [diff] [blame] | 539 | *len_in_resp = 0; |
Sieu Mun Tang | 96bbdca | 2022-04-12 15:00:13 +0800 | [diff] [blame] | 540 | *mbox_status = GENERIC_RESPONSE_ERROR; |
Abdul Halim, Muhammad Hadi Asyrafi | c39a0e0 | 2020-02-06 19:18:41 +0800 | [diff] [blame] | 541 | |
Sieu Mun Tang | 28af165 | 2022-05-09 10:48:53 +0800 | [diff] [blame] | 542 | if (!is_address_in_ddr_range((uint64_t)args, sizeof(uint32_t) * len)) { |
Abdul Halim, Muhammad Hadi Asyrafi | c39a0e0 | 2020-02-06 19:18:41 +0800 | [diff] [blame] | 543 | return INTEL_SIP_SMC_STATUS_REJECTED; |
Sieu Mun Tang | 28af165 | 2022-05-09 10:48:53 +0800 | [diff] [blame] | 544 | } |
Abdul Halim, Muhammad Hadi Asyrafi | c39a0e0 | 2020-02-06 19:18:41 +0800 | [diff] [blame] | 545 | |
Hadi Asyrafi | a33e810 | 2019-12-17 19:30:41 +0800 | [diff] [blame] | 546 | int status = mailbox_send_cmd(MBOX_JOB_ID, cmd, args, len, urgent, |
Sieu Mun Tang | 7420c53 | 2022-05-10 23:17:04 +0800 | [diff] [blame] | 547 | (uint32_t *) response, &resp_len); |
Hadi Asyrafi | a33e810 | 2019-12-17 19:30:41 +0800 | [diff] [blame] | 548 | |
| 549 | if (status < 0) { |
Hadi Asyrafi | a33e810 | 2019-12-17 19:30:41 +0800 | [diff] [blame] | 550 | *mbox_status = -status; |
| 551 | return INTEL_SIP_SMC_STATUS_ERROR; |
| 552 | } |
| 553 | |
| 554 | *mbox_status = 0; |
Sieu Mun Tang | 2468266 | 2022-02-19 21:49:48 +0800 | [diff] [blame] | 555 | *len_in_resp = resp_len; |
Sieu Mun Tang | 7420c53 | 2022-05-10 23:17:04 +0800 | [diff] [blame] | 556 | |
| 557 | flush_dcache_range(response, resp_len * MBOX_WORD_BYTE); |
| 558 | |
Hadi Asyrafi | a33e810 | 2019-12-17 19:30:41 +0800 | [diff] [blame] | 559 | return INTEL_SIP_SMC_STATUS_OK; |
| 560 | } |
| 561 | |
Sieu Mun Tang | 2b8e005 | 2022-04-27 18:57:29 +0800 | [diff] [blame] | 562 | static int intel_smc_get_usercode(uint32_t *user_code) |
| 563 | { |
| 564 | int status; |
| 565 | unsigned int resp_len = sizeof(user_code) / MBOX_WORD_BYTE; |
| 566 | |
| 567 | status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_GET_USERCODE, NULL, |
| 568 | 0U, CMD_CASUAL, user_code, &resp_len); |
| 569 | |
| 570 | if (status < 0) { |
| 571 | return INTEL_SIP_SMC_STATUS_ERROR; |
| 572 | } |
| 573 | |
| 574 | return INTEL_SIP_SMC_STATUS_OK; |
| 575 | } |
| 576 | |
Sieu Mun Tang | fd8a8ad | 2022-05-07 00:50:37 +0800 | [diff] [blame] | 577 | uint32_t intel_smc_service_completed(uint64_t addr, uint32_t size, |
| 578 | uint32_t mode, uint32_t *job_id, |
| 579 | uint32_t *ret_size, uint32_t *mbox_error) |
| 580 | { |
| 581 | int status = 0; |
| 582 | uint32_t resp_len = size / MBOX_WORD_BYTE; |
| 583 | |
| 584 | if (resp_len > MBOX_DATA_MAX_LEN) { |
| 585 | return INTEL_SIP_SMC_STATUS_REJECTED; |
| 586 | } |
| 587 | |
| 588 | if (!is_address_in_ddr_range(addr, size)) { |
| 589 | return INTEL_SIP_SMC_STATUS_REJECTED; |
| 590 | } |
| 591 | |
| 592 | if (mode == SERVICE_COMPLETED_MODE_ASYNC) { |
| 593 | status = mailbox_read_response_async(job_id, |
| 594 | NULL, (uint32_t *) addr, &resp_len, 0); |
| 595 | } else { |
| 596 | status = mailbox_read_response(job_id, |
| 597 | (uint32_t *) addr, &resp_len); |
| 598 | |
| 599 | if (status == MBOX_NO_RESPONSE) { |
| 600 | status = MBOX_BUSY; |
| 601 | } |
| 602 | } |
| 603 | |
| 604 | if (status == MBOX_NO_RESPONSE) { |
| 605 | return INTEL_SIP_SMC_STATUS_NO_RESPONSE; |
| 606 | } |
| 607 | |
| 608 | if (status == MBOX_BUSY) { |
| 609 | return INTEL_SIP_SMC_STATUS_BUSY; |
| 610 | } |
| 611 | |
| 612 | *ret_size = resp_len * MBOX_WORD_BYTE; |
| 613 | flush_dcache_range(addr, *ret_size); |
| 614 | |
Sieu Mun Tang | 6c7f0c7 | 2022-12-04 01:43:35 +0800 | [diff] [blame] | 615 | if (status == MBOX_RET_SDOS_DECRYPTION_ERROR_102 || |
| 616 | status == MBOX_RET_SDOS_DECRYPTION_ERROR_103) { |
| 617 | *mbox_error = -status; |
| 618 | } else if (status != MBOX_RET_OK) { |
Sieu Mun Tang | fd8a8ad | 2022-05-07 00:50:37 +0800 | [diff] [blame] | 619 | *mbox_error = -status; |
| 620 | return INTEL_SIP_SMC_STATUS_ERROR; |
| 621 | } |
| 622 | |
| 623 | return INTEL_SIP_SMC_STATUS_OK; |
| 624 | } |
| 625 | |
Sieu Mun Tang | 758a2ad | 2022-05-11 10:23:13 +0800 | [diff] [blame] | 626 | /* Miscellaneous HPS services */ |
| 627 | uint32_t intel_hps_set_bridges(uint64_t enable, uint64_t mask) |
| 628 | { |
| 629 | int status = 0; |
| 630 | |
Sieu Mun Tang | 044ed48 | 2022-05-11 10:45:19 +0800 | [diff] [blame] | 631 | if ((enable & SOCFPGA_BRIDGE_ENABLE) != 0U) { |
| 632 | if ((enable & SOCFPGA_BRIDGE_HAS_MASK) != 0U) { |
Sieu Mun Tang | 758a2ad | 2022-05-11 10:23:13 +0800 | [diff] [blame] | 633 | status = socfpga_bridges_enable((uint32_t)mask); |
| 634 | } else { |
| 635 | status = socfpga_bridges_enable(~0); |
| 636 | } |
| 637 | } else { |
Sieu Mun Tang | 044ed48 | 2022-05-11 10:45:19 +0800 | [diff] [blame] | 638 | if ((enable & SOCFPGA_BRIDGE_HAS_MASK) != 0U) { |
Sieu Mun Tang | 758a2ad | 2022-05-11 10:23:13 +0800 | [diff] [blame] | 639 | status = socfpga_bridges_disable((uint32_t)mask); |
| 640 | } else { |
| 641 | status = socfpga_bridges_disable(~0); |
| 642 | } |
| 643 | } |
| 644 | |
| 645 | if (status < 0) { |
| 646 | return INTEL_SIP_SMC_STATUS_ERROR; |
| 647 | } |
| 648 | |
| 649 | return INTEL_SIP_SMC_STATUS_OK; |
| 650 | } |
| 651 | |
Jit Loon Lim | 2bee173 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 652 | /* SDM SEU Error services */ |
| 653 | static uint32_t intel_sdm_seu_err_read(uint64_t *respbuf, unsigned int respbuf_sz) |
| 654 | { |
| 655 | if (mailbox_seu_err_status((uint32_t *)respbuf, respbuf_sz) < 0) { |
| 656 | return INTEL_SIP_SMC_SEU_ERR_READ_ERROR; |
| 657 | } |
| 658 | |
| 659 | return INTEL_SIP_SMC_STATUS_OK; |
| 660 | } |
| 661 | |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 662 | /* |
| 663 | * This function is responsible for handling all SiP calls from the NS world |
| 664 | */ |
| 665 | |
Sieu Mun Tang | 044ed48 | 2022-05-11 10:45:19 +0800 | [diff] [blame] | 666 | uintptr_t sip_smc_handler_v1(uint32_t smc_fid, |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 667 | u_register_t x1, |
| 668 | u_register_t x2, |
| 669 | u_register_t x3, |
| 670 | u_register_t x4, |
| 671 | void *cookie, |
| 672 | void *handle, |
| 673 | u_register_t flags) |
| 674 | { |
Sieu Mun Tang | 2a820b9 | 2022-05-11 09:59:55 +0800 | [diff] [blame] | 675 | uint32_t retval = 0, completed_addr[3]; |
| 676 | uint32_t retval2 = 0; |
Sieu Mun Tang | a34b881 | 2022-03-17 03:11:55 +0800 | [diff] [blame] | 677 | uint32_t mbox_error = 0; |
Jit Loon Lim | 2bee173 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 678 | uint64_t retval64, rsu_respbuf[9], seu_respbuf[3]; |
Sieu Mun Tang | 9f22cbf | 2022-03-02 11:04:09 +0800 | [diff] [blame] | 679 | int status = INTEL_SIP_SMC_STATUS_OK; |
Sieu Mun Tang | 2468266 | 2022-02-19 21:49:48 +0800 | [diff] [blame] | 680 | int mbox_status; |
| 681 | unsigned int len_in_resp; |
Sieu Mun Tang | 583149a | 2022-05-10 17:27:12 +0800 | [diff] [blame] | 682 | u_register_t x5, x6, x7; |
Abdul Halim, Muhammad Hadi Asyrafi | b45f15e | 2020-05-14 15:32:43 +0800 | [diff] [blame] | 683 | |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 684 | switch (smc_fid) { |
| 685 | case SIP_SVC_UID: |
| 686 | /* Return UID to the caller */ |
| 687 | SMC_UUID_RET(handle, intl_svc_uid); |
Hadi Asyrafi | 6794230 | 2019-10-22 13:28:51 +0800 | [diff] [blame] | 688 | |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 689 | case INTEL_SIP_SMC_FPGA_CONFIG_ISDONE: |
Sieu Mun Tang | c366760 | 2022-05-13 14:55:05 +0800 | [diff] [blame] | 690 | status = intel_mailbox_fpga_config_isdone(); |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 691 | SMC_RET4(handle, status, 0, 0, 0); |
Hadi Asyrafi | 6794230 | 2019-10-22 13:28:51 +0800 | [diff] [blame] | 692 | |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 693 | case INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM: |
| 694 | SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, |
| 695 | INTEL_SIP_SMC_FPGA_CONFIG_ADDR, |
| 696 | INTEL_SIP_SMC_FPGA_CONFIG_SIZE - |
| 697 | INTEL_SIP_SMC_FPGA_CONFIG_ADDR); |
Hadi Asyrafi | 6794230 | 2019-10-22 13:28:51 +0800 | [diff] [blame] | 698 | |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 699 | case INTEL_SIP_SMC_FPGA_CONFIG_START: |
| 700 | status = intel_fpga_config_start(x1); |
| 701 | SMC_RET4(handle, status, 0, 0, 0); |
Hadi Asyrafi | 6794230 | 2019-10-22 13:28:51 +0800 | [diff] [blame] | 702 | |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 703 | case INTEL_SIP_SMC_FPGA_CONFIG_WRITE: |
| 704 | status = intel_fpga_config_write(x1, x2); |
| 705 | SMC_RET4(handle, status, 0, 0, 0); |
Hadi Asyrafi | 6794230 | 2019-10-22 13:28:51 +0800 | [diff] [blame] | 706 | |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 707 | case INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE: |
| 708 | status = intel_fpga_config_completed_write(completed_addr, |
Abdul Halim, Muhammad Hadi Asyrafi | 20a07f3 | 2020-05-18 11:16:48 +0800 | [diff] [blame] | 709 | &retval, &rcv_id); |
| 710 | switch (retval) { |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 711 | case 1: |
| 712 | SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, |
| 713 | completed_addr[0], 0, 0); |
Hadi Asyrafi | 6794230 | 2019-10-22 13:28:51 +0800 | [diff] [blame] | 714 | |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 715 | case 2: |
| 716 | SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, |
| 717 | completed_addr[0], |
| 718 | completed_addr[1], 0); |
Hadi Asyrafi | 6794230 | 2019-10-22 13:28:51 +0800 | [diff] [blame] | 719 | |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 720 | case 3: |
| 721 | SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, |
| 722 | completed_addr[0], |
| 723 | completed_addr[1], |
| 724 | completed_addr[2]); |
Hadi Asyrafi | 6794230 | 2019-10-22 13:28:51 +0800 | [diff] [blame] | 725 | |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 726 | case 0: |
| 727 | SMC_RET4(handle, status, 0, 0, 0); |
Hadi Asyrafi | 6794230 | 2019-10-22 13:28:51 +0800 | [diff] [blame] | 728 | |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 729 | default: |
Tien Hock, Loh | 500b232 | 2019-10-30 14:49:40 +0800 | [diff] [blame] | 730 | mailbox_clear_response(); |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 731 | SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR); |
| 732 | } |
Hadi Asyrafi | 6794230 | 2019-10-22 13:28:51 +0800 | [diff] [blame] | 733 | |
| 734 | case INTEL_SIP_SMC_REG_READ: |
Abdul Halim, Muhammad Hadi Asyrafi | 20a07f3 | 2020-05-18 11:16:48 +0800 | [diff] [blame] | 735 | status = intel_secure_reg_read(x1, &retval); |
| 736 | SMC_RET3(handle, status, retval, x1); |
Hadi Asyrafi | 6794230 | 2019-10-22 13:28:51 +0800 | [diff] [blame] | 737 | |
| 738 | case INTEL_SIP_SMC_REG_WRITE: |
Abdul Halim, Muhammad Hadi Asyrafi | 20a07f3 | 2020-05-18 11:16:48 +0800 | [diff] [blame] | 739 | status = intel_secure_reg_write(x1, (uint32_t)x2, &retval); |
| 740 | SMC_RET3(handle, status, retval, x1); |
Hadi Asyrafi | 6794230 | 2019-10-22 13:28:51 +0800 | [diff] [blame] | 741 | |
| 742 | case INTEL_SIP_SMC_REG_UPDATE: |
| 743 | status = intel_secure_reg_update(x1, (uint32_t)x2, |
Abdul Halim, Muhammad Hadi Asyrafi | 20a07f3 | 2020-05-18 11:16:48 +0800 | [diff] [blame] | 744 | (uint32_t)x3, &retval); |
| 745 | SMC_RET3(handle, status, retval, x1); |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 746 | |
Hadi Asyrafi | 593c4c5 | 2019-12-17 19:22:17 +0800 | [diff] [blame] | 747 | case INTEL_SIP_SMC_RSU_STATUS: |
| 748 | status = intel_rsu_status(rsu_respbuf, |
| 749 | ARRAY_SIZE(rsu_respbuf)); |
| 750 | if (status) { |
| 751 | SMC_RET1(handle, status); |
| 752 | } else { |
| 753 | SMC_RET4(handle, rsu_respbuf[0], rsu_respbuf[1], |
| 754 | rsu_respbuf[2], rsu_respbuf[3]); |
| 755 | } |
| 756 | |
| 757 | case INTEL_SIP_SMC_RSU_UPDATE: |
| 758 | status = intel_rsu_update(x1); |
| 759 | SMC_RET1(handle, status); |
| 760 | |
| 761 | case INTEL_SIP_SMC_RSU_NOTIFY: |
| 762 | status = intel_rsu_notify(x1); |
| 763 | SMC_RET1(handle, status); |
| 764 | |
| 765 | case INTEL_SIP_SMC_RSU_RETRY_COUNTER: |
| 766 | status = intel_rsu_retry_counter((uint32_t *)rsu_respbuf, |
Abdul Halim, Muhammad Hadi Asyrafi | 20a07f3 | 2020-05-18 11:16:48 +0800 | [diff] [blame] | 767 | ARRAY_SIZE(rsu_respbuf), &retval); |
Hadi Asyrafi | 593c4c5 | 2019-12-17 19:22:17 +0800 | [diff] [blame] | 768 | if (status) { |
| 769 | SMC_RET1(handle, status); |
| 770 | } else { |
Abdul Halim, Muhammad Hadi Asyrafi | 20a07f3 | 2020-05-18 11:16:48 +0800 | [diff] [blame] | 771 | SMC_RET2(handle, status, retval); |
Hadi Asyrafi | 593c4c5 | 2019-12-17 19:22:17 +0800 | [diff] [blame] | 772 | } |
| 773 | |
Chee Hong Ang | 2cfd8ec | 2020-05-13 11:44:04 +0800 | [diff] [blame] | 774 | case INTEL_SIP_SMC_RSU_DCMF_VERSION: |
| 775 | SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, |
| 776 | ((uint64_t)rsu_dcmf_ver[1] << 32) | rsu_dcmf_ver[0], |
| 777 | ((uint64_t)rsu_dcmf_ver[3] << 32) | rsu_dcmf_ver[2]); |
| 778 | |
| 779 | case INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION: |
| 780 | status = intel_rsu_copy_dcmf_version(x1, x2); |
| 781 | SMC_RET1(handle, status); |
| 782 | |
Sieu Mun Tang | e6d5de9 | 2022-04-28 22:21:01 +0800 | [diff] [blame] | 783 | case INTEL_SIP_SMC_RSU_DCMF_STATUS: |
| 784 | SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK, |
| 785 | ((uint64_t)rsu_dcmf_stat[3] << 48) | |
| 786 | ((uint64_t)rsu_dcmf_stat[2] << 32) | |
| 787 | ((uint64_t)rsu_dcmf_stat[1] << 16) | |
| 788 | rsu_dcmf_stat[0]); |
| 789 | |
| 790 | case INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS: |
| 791 | status = intel_rsu_copy_dcmf_status(x1); |
| 792 | SMC_RET1(handle, status); |
| 793 | |
Chee Hong Ang | 681631b | 2020-07-01 14:22:25 +0800 | [diff] [blame] | 794 | case INTEL_SIP_SMC_RSU_MAX_RETRY: |
| 795 | SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK, rsu_max_retry); |
| 796 | |
| 797 | case INTEL_SIP_SMC_RSU_COPY_MAX_RETRY: |
| 798 | rsu_max_retry = x1; |
| 799 | SMC_RET1(handle, INTEL_SIP_SMC_STATUS_OK); |
| 800 | |
Sieu Mun Tang | dbcc2cf | 2022-03-07 12:13:04 +0800 | [diff] [blame] | 801 | case INTEL_SIP_SMC_ECC_DBE: |
| 802 | status = intel_ecc_dbe_notification(x1); |
| 803 | SMC_RET1(handle, status); |
| 804 | |
Sieu Mun Tang | 758a2ad | 2022-05-11 10:23:13 +0800 | [diff] [blame] | 805 | case INTEL_SIP_SMC_SERVICE_COMPLETED: |
| 806 | status = intel_smc_service_completed(x1, x2, x3, &rcv_id, |
| 807 | &len_in_resp, &mbox_error); |
| 808 | SMC_RET4(handle, status, mbox_error, x1, len_in_resp); |
| 809 | |
Abdul Halim, Muhammad Hadi Asyrafi | d9006fc | 2021-02-05 11:50:58 +0800 | [diff] [blame] | 810 | case INTEL_SIP_SMC_FIRMWARE_VERSION: |
| 811 | status = intel_smc_fw_version(&retval); |
Sieu Mun Tang | bfda95a | 2022-04-27 18:54:10 +0800 | [diff] [blame] | 812 | SMC_RET2(handle, status, retval); |
Abdul Halim, Muhammad Hadi Asyrafi | d9006fc | 2021-02-05 11:50:58 +0800 | [diff] [blame] | 813 | |
Hadi Asyrafi | a33e810 | 2019-12-17 19:30:41 +0800 | [diff] [blame] | 814 | case INTEL_SIP_SMC_MBOX_SEND_CMD: |
| 815 | x5 = SMC_GET_GP(handle, CTX_GPREG_X5); |
| 816 | x6 = SMC_GET_GP(handle, CTX_GPREG_X6); |
Sieu Mun Tang | 7420c53 | 2022-05-10 23:17:04 +0800 | [diff] [blame] | 817 | status = intel_mbox_send_cmd(x1, (uint32_t *)x2, x3, x4, x5, x6, |
| 818 | &mbox_status, &len_in_resp); |
Sieu Mun Tang | f02f0cb | 2022-02-19 20:36:41 +0800 | [diff] [blame] | 819 | SMC_RET3(handle, status, mbox_status, len_in_resp); |
Hadi Asyrafi | a33e810 | 2019-12-17 19:30:41 +0800 | [diff] [blame] | 820 | |
Sieu Mun Tang | 2b8e005 | 2022-04-27 18:57:29 +0800 | [diff] [blame] | 821 | case INTEL_SIP_SMC_GET_USERCODE: |
| 822 | status = intel_smc_get_usercode(&retval); |
| 823 | SMC_RET2(handle, status, retval); |
| 824 | |
Sieu Mun Tang | 128d2a7 | 2022-05-11 09:49:25 +0800 | [diff] [blame] | 825 | case INTEL_SIP_SMC_FCS_CRYPTION: |
| 826 | x5 = SMC_GET_GP(handle, CTX_GPREG_X5); |
| 827 | |
| 828 | if (x1 == FCS_MODE_DECRYPT) { |
| 829 | status = intel_fcs_decryption(x2, x3, x4, x5, &send_id); |
| 830 | } else if (x1 == FCS_MODE_ENCRYPT) { |
| 831 | status = intel_fcs_encryption(x2, x3, x4, x5, &send_id); |
| 832 | } else { |
| 833 | status = INTEL_SIP_SMC_STATUS_REJECTED; |
| 834 | } |
| 835 | |
| 836 | SMC_RET3(handle, status, x4, x5); |
| 837 | |
Sieu Mun Tang | 22322fb | 2022-05-09 16:05:58 +0800 | [diff] [blame] | 838 | case INTEL_SIP_SMC_FCS_CRYPTION_EXT: |
| 839 | x5 = SMC_GET_GP(handle, CTX_GPREG_X5); |
| 840 | x6 = SMC_GET_GP(handle, CTX_GPREG_X6); |
| 841 | x7 = SMC_GET_GP(handle, CTX_GPREG_X7); |
| 842 | |
| 843 | if (x3 == FCS_MODE_DECRYPT) { |
| 844 | status = intel_fcs_decryption_ext(x1, x2, x4, x5, x6, |
| 845 | (uint32_t *) &x7, &mbox_error); |
| 846 | } else if (x3 == FCS_MODE_ENCRYPT) { |
| 847 | status = intel_fcs_encryption_ext(x1, x2, x4, x5, x6, |
| 848 | (uint32_t *) &x7, &mbox_error); |
| 849 | } else { |
| 850 | status = INTEL_SIP_SMC_STATUS_REJECTED; |
| 851 | } |
| 852 | |
| 853 | SMC_RET4(handle, status, mbox_error, x6, x7); |
| 854 | |
Sieu Mun Tang | fd8a8ad | 2022-05-07 00:50:37 +0800 | [diff] [blame] | 855 | case INTEL_SIP_SMC_FCS_RANDOM_NUMBER: |
| 856 | status = intel_fcs_random_number_gen(x1, &retval64, |
| 857 | &mbox_error); |
| 858 | SMC_RET4(handle, status, mbox_error, x1, retval64); |
| 859 | |
Sieu Mun Tang | e7a037f | 2022-05-10 17:18:19 +0800 | [diff] [blame] | 860 | case INTEL_SIP_SMC_FCS_RANDOM_NUMBER_EXT: |
| 861 | status = intel_fcs_random_number_gen_ext(x1, x2, x3, |
| 862 | &send_id); |
| 863 | SMC_RET1(handle, status); |
| 864 | |
Sieu Mun Tang | fd8a8ad | 2022-05-07 00:50:37 +0800 | [diff] [blame] | 865 | case INTEL_SIP_SMC_FCS_SEND_CERTIFICATE: |
| 866 | status = intel_fcs_send_cert(x1, x2, &send_id); |
| 867 | SMC_RET1(handle, status); |
| 868 | |
| 869 | case INTEL_SIP_SMC_FCS_GET_PROVISION_DATA: |
| 870 | status = intel_fcs_get_provision_data(&send_id); |
| 871 | SMC_RET1(handle, status); |
| 872 | |
Sieu Mun Tang | a068fdf | 2022-05-11 10:01:54 +0800 | [diff] [blame] | 873 | case INTEL_SIP_SMC_FCS_CNTR_SET_PREAUTH: |
| 874 | status = intel_fcs_cntr_set_preauth(x1, x2, x3, |
| 875 | &mbox_error); |
| 876 | SMC_RET2(handle, status, mbox_error); |
| 877 | |
Sieu Mun Tang | 82cf5df | 2022-05-05 17:07:21 +0800 | [diff] [blame] | 878 | case INTEL_SIP_SMC_HPS_SET_BRIDGES: |
| 879 | status = intel_hps_set_bridges(x1, x2); |
| 880 | SMC_RET1(handle, status); |
| 881 | |
Sieu Mun Tang | 044ed48 | 2022-05-11 10:45:19 +0800 | [diff] [blame] | 882 | case INTEL_SIP_SMC_HWMON_READTEMP: |
| 883 | status = intel_hwmon_readtemp(x1, &retval); |
| 884 | SMC_RET2(handle, status, retval); |
| 885 | |
| 886 | case INTEL_SIP_SMC_HWMON_READVOLT: |
| 887 | status = intel_hwmon_readvolt(x1, &retval); |
| 888 | SMC_RET2(handle, status, retval); |
| 889 | |
Sieu Mun Tang | 2a820b9 | 2022-05-11 09:59:55 +0800 | [diff] [blame] | 890 | case INTEL_SIP_SMC_FCS_PSGSIGMA_TEARDOWN: |
| 891 | status = intel_fcs_sigma_teardown(x1, &mbox_error); |
| 892 | SMC_RET2(handle, status, mbox_error); |
| 893 | |
| 894 | case INTEL_SIP_SMC_FCS_CHIP_ID: |
| 895 | status = intel_fcs_chip_id(&retval, &retval2, &mbox_error); |
| 896 | SMC_RET4(handle, status, mbox_error, retval, retval2); |
| 897 | |
| 898 | case INTEL_SIP_SMC_FCS_ATTESTATION_SUBKEY: |
| 899 | status = intel_fcs_attestation_subkey(x1, x2, x3, |
| 900 | (uint32_t *) &x4, &mbox_error); |
| 901 | SMC_RET4(handle, status, mbox_error, x3, x4); |
| 902 | |
| 903 | case INTEL_SIP_SMC_FCS_ATTESTATION_MEASUREMENTS: |
| 904 | status = intel_fcs_get_measurement(x1, x2, x3, |
| 905 | (uint32_t *) &x4, &mbox_error); |
| 906 | SMC_RET4(handle, status, mbox_error, x3, x4); |
| 907 | |
Sieu Mun Tang | 28af165 | 2022-05-09 10:48:53 +0800 | [diff] [blame] | 908 | case INTEL_SIP_SMC_FCS_GET_ATTESTATION_CERT: |
| 909 | status = intel_fcs_get_attestation_cert(x1, x2, |
| 910 | (uint32_t *) &x3, &mbox_error); |
| 911 | SMC_RET4(handle, status, mbox_error, x2, x3); |
| 912 | |
| 913 | case INTEL_SIP_SMC_FCS_CREATE_CERT_ON_RELOAD: |
| 914 | status = intel_fcs_create_cert_on_reload(x1, &mbox_error); |
| 915 | SMC_RET2(handle, status, mbox_error); |
| 916 | |
Sieu Mun Tang | 16754e1 | 2022-05-09 12:08:42 +0800 | [diff] [blame] | 917 | case INTEL_SIP_SMC_FCS_OPEN_CS_SESSION: |
| 918 | status = intel_fcs_open_crypto_service_session(&retval, &mbox_error); |
| 919 | SMC_RET3(handle, status, mbox_error, retval); |
| 920 | |
| 921 | case INTEL_SIP_SMC_FCS_CLOSE_CS_SESSION: |
| 922 | status = intel_fcs_close_crypto_service_session(x1, &mbox_error); |
| 923 | SMC_RET2(handle, status, mbox_error); |
| 924 | |
Sieu Mun Tang | fb1f6e9 | 2022-05-09 14:16:14 +0800 | [diff] [blame] | 925 | case INTEL_SIP_SMC_FCS_IMPORT_CS_KEY: |
| 926 | status = intel_fcs_import_crypto_service_key(x1, x2, &send_id); |
| 927 | SMC_RET1(handle, status); |
| 928 | |
| 929 | case INTEL_SIP_SMC_FCS_EXPORT_CS_KEY: |
| 930 | status = intel_fcs_export_crypto_service_key(x1, x2, x3, |
| 931 | (uint32_t *) &x4, &mbox_error); |
| 932 | SMC_RET4(handle, status, mbox_error, x3, x4); |
| 933 | |
| 934 | case INTEL_SIP_SMC_FCS_REMOVE_CS_KEY: |
| 935 | status = intel_fcs_remove_crypto_service_key(x1, x2, |
| 936 | &mbox_error); |
| 937 | SMC_RET2(handle, status, mbox_error); |
| 938 | |
| 939 | case INTEL_SIP_SMC_FCS_GET_CS_KEY_INFO: |
| 940 | status = intel_fcs_get_crypto_service_key_info(x1, x2, x3, |
| 941 | (uint32_t *) &x4, &mbox_error); |
| 942 | SMC_RET4(handle, status, mbox_error, x3, x4); |
| 943 | |
Sieu Mun Tang | d907cc3 | 2022-05-10 17:24:05 +0800 | [diff] [blame] | 944 | case INTEL_SIP_SMC_FCS_GET_DIGEST_INIT: |
| 945 | x5 = SMC_GET_GP(handle, CTX_GPREG_X5); |
| 946 | status = intel_fcs_get_digest_init(x1, x2, x3, |
| 947 | x4, x5, &mbox_error); |
| 948 | SMC_RET2(handle, status, mbox_error); |
| 949 | |
Sieu Mun Tang | 527df9f | 2022-04-28 16:28:48 +0800 | [diff] [blame] | 950 | case INTEL_SIP_SMC_FCS_GET_DIGEST_UPDATE: |
| 951 | x5 = SMC_GET_GP(handle, CTX_GPREG_X5); |
| 952 | x6 = SMC_GET_GP(handle, CTX_GPREG_X6); |
| 953 | status = intel_fcs_get_digest_update_finalize(x1, x2, x3, |
| 954 | x4, x5, (uint32_t *) &x6, false, |
| 955 | &mbox_error); |
| 956 | SMC_RET4(handle, status, mbox_error, x5, x6); |
| 957 | |
Sieu Mun Tang | d907cc3 | 2022-05-10 17:24:05 +0800 | [diff] [blame] | 958 | case INTEL_SIP_SMC_FCS_GET_DIGEST_FINALIZE: |
| 959 | x5 = SMC_GET_GP(handle, CTX_GPREG_X5); |
| 960 | x6 = SMC_GET_GP(handle, CTX_GPREG_X6); |
Sieu Mun Tang | 527df9f | 2022-04-28 16:28:48 +0800 | [diff] [blame] | 961 | status = intel_fcs_get_digest_update_finalize(x1, x2, x3, |
| 962 | x4, x5, (uint32_t *) &x6, true, |
| 963 | &mbox_error); |
Sieu Mun Tang | d907cc3 | 2022-05-10 17:24:05 +0800 | [diff] [blame] | 964 | SMC_RET4(handle, status, mbox_error, x5, x6); |
| 965 | |
Sieu Mun Tang | bd8da63 | 2022-09-28 15:58:28 +0800 | [diff] [blame] | 966 | case INTEL_SIP_SMC_FCS_GET_DIGEST_SMMU_UPDATE: |
| 967 | x5 = SMC_GET_GP(handle, CTX_GPREG_X5); |
| 968 | x6 = SMC_GET_GP(handle, CTX_GPREG_X6); |
| 969 | status = intel_fcs_get_digest_smmu_update_finalize(x1, x2, x3, |
| 970 | x4, x5, (uint32_t *) &x6, false, |
| 971 | &mbox_error, &send_id); |
| 972 | SMC_RET4(handle, status, mbox_error, x5, x6); |
| 973 | |
| 974 | case INTEL_SIP_SMC_FCS_GET_DIGEST_SMMU_FINALIZE: |
| 975 | x5 = SMC_GET_GP(handle, CTX_GPREG_X5); |
| 976 | x6 = SMC_GET_GP(handle, CTX_GPREG_X6); |
| 977 | status = intel_fcs_get_digest_smmu_update_finalize(x1, x2, x3, |
| 978 | x4, x5, (uint32_t *) &x6, true, |
| 979 | &mbox_error, &send_id); |
| 980 | SMC_RET4(handle, status, mbox_error, x5, x6); |
| 981 | |
Sieu Mun Tang | 583149a | 2022-05-10 17:27:12 +0800 | [diff] [blame] | 982 | case INTEL_SIP_SMC_FCS_MAC_VERIFY_INIT: |
| 983 | x5 = SMC_GET_GP(handle, CTX_GPREG_X5); |
| 984 | status = intel_fcs_mac_verify_init(x1, x2, x3, |
| 985 | x4, x5, &mbox_error); |
| 986 | SMC_RET2(handle, status, mbox_error); |
| 987 | |
Sieu Mun Tang | 527df9f | 2022-04-28 16:28:48 +0800 | [diff] [blame] | 988 | case INTEL_SIP_SMC_FCS_MAC_VERIFY_UPDATE: |
| 989 | x5 = SMC_GET_GP(handle, CTX_GPREG_X5); |
| 990 | x6 = SMC_GET_GP(handle, CTX_GPREG_X6); |
| 991 | x7 = SMC_GET_GP(handle, CTX_GPREG_X7); |
| 992 | status = intel_fcs_mac_verify_update_finalize(x1, x2, x3, |
| 993 | x4, x5, (uint32_t *) &x6, x7, |
| 994 | false, &mbox_error); |
| 995 | SMC_RET4(handle, status, mbox_error, x5, x6); |
| 996 | |
Sieu Mun Tang | 583149a | 2022-05-10 17:27:12 +0800 | [diff] [blame] | 997 | case INTEL_SIP_SMC_FCS_MAC_VERIFY_FINALIZE: |
| 998 | x5 = SMC_GET_GP(handle, CTX_GPREG_X5); |
| 999 | x6 = SMC_GET_GP(handle, CTX_GPREG_X6); |
| 1000 | x7 = SMC_GET_GP(handle, CTX_GPREG_X7); |
Sieu Mun Tang | 527df9f | 2022-04-28 16:28:48 +0800 | [diff] [blame] | 1001 | status = intel_fcs_mac_verify_update_finalize(x1, x2, x3, |
| 1002 | x4, x5, (uint32_t *) &x6, x7, |
| 1003 | true, &mbox_error); |
Sieu Mun Tang | 583149a | 2022-05-10 17:27:12 +0800 | [diff] [blame] | 1004 | SMC_RET4(handle, status, mbox_error, x5, x6); |
| 1005 | |
Sieu Mun Tang | bd8da63 | 2022-09-28 15:58:28 +0800 | [diff] [blame] | 1006 | case INTEL_SIP_SMC_FCS_MAC_VERIFY_SMMU_UPDATE: |
| 1007 | x5 = SMC_GET_GP(handle, CTX_GPREG_X5); |
| 1008 | x6 = SMC_GET_GP(handle, CTX_GPREG_X6); |
| 1009 | x7 = SMC_GET_GP(handle, CTX_GPREG_X7); |
| 1010 | status = intel_fcs_mac_verify_smmu_update_finalize(x1, x2, x3, |
| 1011 | x4, x5, (uint32_t *) &x6, x7, |
| 1012 | false, &mbox_error, &send_id); |
| 1013 | SMC_RET4(handle, status, mbox_error, x5, x6); |
| 1014 | |
| 1015 | case INTEL_SIP_SMC_FCS_MAC_VERIFY_SMMU_FINALIZE: |
| 1016 | x5 = SMC_GET_GP(handle, CTX_GPREG_X5); |
| 1017 | x6 = SMC_GET_GP(handle, CTX_GPREG_X6); |
| 1018 | x7 = SMC_GET_GP(handle, CTX_GPREG_X7); |
| 1019 | status = intel_fcs_mac_verify_smmu_update_finalize(x1, x2, x3, |
| 1020 | x4, x5, (uint32_t *) &x6, x7, |
| 1021 | true, &mbox_error, &send_id); |
| 1022 | SMC_RET4(handle, status, mbox_error, x5, x6); |
| 1023 | |
Sieu Mun Tang | 153ecfb | 2022-05-10 17:39:26 +0800 | [diff] [blame] | 1024 | case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_INIT: |
| 1025 | x5 = SMC_GET_GP(handle, CTX_GPREG_X5); |
| 1026 | status = intel_fcs_ecdsa_sha2_data_sign_init(x1, x2, x3, |
| 1027 | x4, x5, &mbox_error); |
| 1028 | SMC_RET2(handle, status, mbox_error); |
| 1029 | |
Sieu Mun Tang | e77d37d | 2022-04-28 16:23:20 +0800 | [diff] [blame] | 1030 | case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_UPDATE: |
| 1031 | x5 = SMC_GET_GP(handle, CTX_GPREG_X5); |
| 1032 | x6 = SMC_GET_GP(handle, CTX_GPREG_X6); |
| 1033 | status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(x1, x2, |
| 1034 | x3, x4, x5, (uint32_t *) &x6, false, |
| 1035 | &mbox_error); |
| 1036 | SMC_RET4(handle, status, mbox_error, x5, x6); |
| 1037 | |
Sieu Mun Tang | 153ecfb | 2022-05-10 17:39:26 +0800 | [diff] [blame] | 1038 | case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE: |
| 1039 | x5 = SMC_GET_GP(handle, CTX_GPREG_X5); |
| 1040 | x6 = SMC_GET_GP(handle, CTX_GPREG_X6); |
Sieu Mun Tang | e77d37d | 2022-04-28 16:23:20 +0800 | [diff] [blame] | 1041 | status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(x1, x2, |
| 1042 | x3, x4, x5, (uint32_t *) &x6, true, |
| 1043 | &mbox_error); |
Sieu Mun Tang | 153ecfb | 2022-05-10 17:39:26 +0800 | [diff] [blame] | 1044 | SMC_RET4(handle, status, mbox_error, x5, x6); |
| 1045 | |
Sieu Mun Tang | bd8da63 | 2022-09-28 15:58:28 +0800 | [diff] [blame] | 1046 | case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_UPDATE: |
| 1047 | x5 = SMC_GET_GP(handle, CTX_GPREG_X5); |
| 1048 | x6 = SMC_GET_GP(handle, CTX_GPREG_X6); |
| 1049 | status = intel_fcs_ecdsa_sha2_data_sign_smmu_update_finalize(x1, |
| 1050 | x2, x3, x4, x5, (uint32_t *) &x6, false, |
| 1051 | &mbox_error, &send_id); |
| 1052 | SMC_RET4(handle, status, mbox_error, x5, x6); |
| 1053 | |
| 1054 | case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_FINALIZE: |
| 1055 | x5 = SMC_GET_GP(handle, CTX_GPREG_X5); |
| 1056 | x6 = SMC_GET_GP(handle, CTX_GPREG_X6); |
| 1057 | status = intel_fcs_ecdsa_sha2_data_sign_smmu_update_finalize(x1, |
| 1058 | x2, x3, x4, x5, (uint32_t *) &x6, true, |
| 1059 | &mbox_error, &send_id); |
| 1060 | SMC_RET4(handle, status, mbox_error, x5, x6); |
| 1061 | |
Sieu Mun Tang | 8aa05ad | 2022-05-10 17:50:30 +0800 | [diff] [blame] | 1062 | case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_INIT: |
| 1063 | x5 = SMC_GET_GP(handle, CTX_GPREG_X5); |
| 1064 | status = intel_fcs_ecdsa_hash_sign_init(x1, x2, x3, |
| 1065 | x4, x5, &mbox_error); |
| 1066 | SMC_RET2(handle, status, mbox_error); |
| 1067 | |
| 1068 | case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_FINALIZE: |
| 1069 | x5 = SMC_GET_GP(handle, CTX_GPREG_X5); |
| 1070 | x6 = SMC_GET_GP(handle, CTX_GPREG_X6); |
| 1071 | status = intel_fcs_ecdsa_hash_sign_finalize(x1, x2, x3, |
| 1072 | x4, x5, (uint32_t *) &x6, &mbox_error); |
| 1073 | SMC_RET4(handle, status, mbox_error, x5, x6); |
| 1074 | |
Sieu Mun Tang | 59357e8 | 2022-05-10 17:53:32 +0800 | [diff] [blame] | 1075 | case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_INIT: |
| 1076 | x5 = SMC_GET_GP(handle, CTX_GPREG_X5); |
| 1077 | status = intel_fcs_ecdsa_hash_sig_verify_init(x1, x2, x3, |
| 1078 | x4, x5, &mbox_error); |
| 1079 | SMC_RET2(handle, status, mbox_error); |
| 1080 | |
| 1081 | case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_FINALIZE: |
| 1082 | x5 = SMC_GET_GP(handle, CTX_GPREG_X5); |
| 1083 | x6 = SMC_GET_GP(handle, CTX_GPREG_X6); |
| 1084 | status = intel_fcs_ecdsa_hash_sig_verify_finalize(x1, x2, x3, |
| 1085 | x4, x5, (uint32_t *) &x6, &mbox_error); |
| 1086 | SMC_RET4(handle, status, mbox_error, x5, x6); |
| 1087 | |
Sieu Mun Tang | dcaab77 | 2022-05-11 10:16:40 +0800 | [diff] [blame] | 1088 | case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_INIT: |
| 1089 | x5 = SMC_GET_GP(handle, CTX_GPREG_X5); |
| 1090 | status = intel_fcs_ecdsa_sha2_data_sig_verify_init(x1, x2, x3, |
| 1091 | x4, x5, &mbox_error); |
| 1092 | SMC_RET2(handle, status, mbox_error); |
| 1093 | |
Sieu Mun Tang | e77d37d | 2022-04-28 16:23:20 +0800 | [diff] [blame] | 1094 | case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_UPDATE: |
| 1095 | x5 = SMC_GET_GP(handle, CTX_GPREG_X5); |
| 1096 | x6 = SMC_GET_GP(handle, CTX_GPREG_X6); |
| 1097 | x7 = SMC_GET_GP(handle, CTX_GPREG_X7); |
| 1098 | status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize( |
| 1099 | x1, x2, x3, x4, x5, (uint32_t *) &x6, |
| 1100 | x7, false, &mbox_error); |
| 1101 | SMC_RET4(handle, status, mbox_error, x5, x6); |
| 1102 | |
Sieu Mun Tang | bd8da63 | 2022-09-28 15:58:28 +0800 | [diff] [blame] | 1103 | case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_UPDATE: |
| 1104 | x5 = SMC_GET_GP(handle, CTX_GPREG_X5); |
| 1105 | x6 = SMC_GET_GP(handle, CTX_GPREG_X6); |
| 1106 | x7 = SMC_GET_GP(handle, CTX_GPREG_X7); |
| 1107 | status = intel_fcs_ecdsa_sha2_data_sig_verify_smmu_update_finalize( |
| 1108 | x1, x2, x3, x4, x5, (uint32_t *) &x6, |
| 1109 | x7, false, &mbox_error, &send_id); |
| 1110 | SMC_RET4(handle, status, mbox_error, x5, x6); |
| 1111 | |
| 1112 | case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_FINALIZE: |
| 1113 | x5 = SMC_GET_GP(handle, CTX_GPREG_X5); |
| 1114 | x6 = SMC_GET_GP(handle, CTX_GPREG_X6); |
| 1115 | x7 = SMC_GET_GP(handle, CTX_GPREG_X7); |
| 1116 | status = intel_fcs_ecdsa_sha2_data_sig_verify_smmu_update_finalize( |
| 1117 | x1, x2, x3, x4, x5, (uint32_t *) &x6, |
| 1118 | x7, true, &mbox_error, &send_id); |
| 1119 | SMC_RET4(handle, status, mbox_error, x5, x6); |
| 1120 | |
Sieu Mun Tang | dcaab77 | 2022-05-11 10:16:40 +0800 | [diff] [blame] | 1121 | case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE: |
| 1122 | x5 = SMC_GET_GP(handle, CTX_GPREG_X5); |
| 1123 | x6 = SMC_GET_GP(handle, CTX_GPREG_X6); |
| 1124 | x7 = SMC_GET_GP(handle, CTX_GPREG_X7); |
Sieu Mun Tang | e77d37d | 2022-04-28 16:23:20 +0800 | [diff] [blame] | 1125 | status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize( |
| 1126 | x1, x2, x3, x4, x5, (uint32_t *) &x6, |
| 1127 | x7, true, &mbox_error); |
Sieu Mun Tang | dcaab77 | 2022-05-11 10:16:40 +0800 | [diff] [blame] | 1128 | SMC_RET4(handle, status, mbox_error, x5, x6); |
Sieu Mun Tang | 153ecfb | 2022-05-10 17:39:26 +0800 | [diff] [blame] | 1129 | |
Sieu Mun Tang | e2f3ede | 2022-05-10 17:36:32 +0800 | [diff] [blame] | 1130 | case INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_INIT: |
| 1131 | x5 = SMC_GET_GP(handle, CTX_GPREG_X5); |
| 1132 | status = intel_fcs_ecdsa_get_pubkey_init(x1, x2, x3, |
| 1133 | x4, x5, &mbox_error); |
| 1134 | SMC_RET2(handle, status, mbox_error); |
| 1135 | |
| 1136 | case INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_FINALIZE: |
| 1137 | status = intel_fcs_ecdsa_get_pubkey_finalize(x1, x2, x3, |
| 1138 | (uint32_t *) &x4, &mbox_error); |
| 1139 | SMC_RET4(handle, status, mbox_error, x3, x4); |
| 1140 | |
Sieu Mun Tang | 0675c22 | 2022-05-10 17:48:11 +0800 | [diff] [blame] | 1141 | case INTEL_SIP_SMC_FCS_ECDH_REQUEST_INIT: |
| 1142 | x5 = SMC_GET_GP(handle, CTX_GPREG_X5); |
| 1143 | status = intel_fcs_ecdh_request_init(x1, x2, x3, |
| 1144 | x4, x5, &mbox_error); |
| 1145 | SMC_RET2(handle, status, mbox_error); |
| 1146 | |
| 1147 | case INTEL_SIP_SMC_FCS_ECDH_REQUEST_FINALIZE: |
| 1148 | x5 = SMC_GET_GP(handle, CTX_GPREG_X5); |
| 1149 | x6 = SMC_GET_GP(handle, CTX_GPREG_X6); |
| 1150 | status = intel_fcs_ecdh_request_finalize(x1, x2, x3, |
| 1151 | x4, x5, (uint32_t *) &x6, &mbox_error); |
| 1152 | SMC_RET4(handle, status, mbox_error, x5, x6); |
| 1153 | |
Sieu Mun Tang | b0c1d11 | 2022-05-10 17:30:00 +0800 | [diff] [blame] | 1154 | case INTEL_SIP_SMC_FCS_AES_CRYPT_INIT: |
| 1155 | x5 = SMC_GET_GP(handle, CTX_GPREG_X5); |
| 1156 | status = intel_fcs_aes_crypt_init(x1, x2, x3, x4, x5, |
| 1157 | &mbox_error); |
| 1158 | SMC_RET2(handle, status, mbox_error); |
| 1159 | |
Sieu Mun Tang | 9bea815 | 2022-04-28 16:15:54 +0800 | [diff] [blame] | 1160 | case INTEL_SIP_SMC_FCS_AES_CRYPT_UPDATE: |
| 1161 | x5 = SMC_GET_GP(handle, CTX_GPREG_X5); |
| 1162 | x6 = SMC_GET_GP(handle, CTX_GPREG_X6); |
| 1163 | status = intel_fcs_aes_crypt_update_finalize(x1, x2, x3, x4, |
| 1164 | x5, x6, false, &send_id); |
| 1165 | SMC_RET1(handle, status); |
| 1166 | |
Sieu Mun Tang | b0c1d11 | 2022-05-10 17:30:00 +0800 | [diff] [blame] | 1167 | case INTEL_SIP_SMC_FCS_AES_CRYPT_FINALIZE: |
| 1168 | x5 = SMC_GET_GP(handle, CTX_GPREG_X5); |
| 1169 | x6 = SMC_GET_GP(handle, CTX_GPREG_X6); |
Sieu Mun Tang | 9bea815 | 2022-04-28 16:15:54 +0800 | [diff] [blame] | 1170 | status = intel_fcs_aes_crypt_update_finalize(x1, x2, x3, x4, |
| 1171 | x5, x6, true, &send_id); |
Sieu Mun Tang | b0c1d11 | 2022-05-10 17:30:00 +0800 | [diff] [blame] | 1172 | SMC_RET1(handle, status); |
| 1173 | |
Sieu Mun Tang | a34b881 | 2022-03-17 03:11:55 +0800 | [diff] [blame] | 1174 | case INTEL_SIP_SMC_GET_ROM_PATCH_SHA384: |
| 1175 | status = intel_fcs_get_rom_patch_sha384(x1, &retval64, |
| 1176 | &mbox_error); |
| 1177 | SMC_RET4(handle, status, mbox_error, x1, retval64); |
| 1178 | |
Sieu Mun Tang | f9cb657 | 2022-04-27 18:24:06 +0800 | [diff] [blame] | 1179 | case INTEL_SIP_SMC_SVC_VERSION: |
| 1180 | SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, |
| 1181 | SIP_SVC_VERSION_MAJOR, |
| 1182 | SIP_SVC_VERSION_MINOR); |
| 1183 | |
Jit Loon Lim | 2bee173 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 1184 | case INTEL_SIP_SMC_SEU_ERR_STATUS: |
| 1185 | status = intel_sdm_seu_err_read(seu_respbuf, |
| 1186 | ARRAY_SIZE(seu_respbuf)); |
| 1187 | if (status) { |
| 1188 | SMC_RET1(handle, status); |
| 1189 | } else { |
| 1190 | SMC_RET3(handle, seu_respbuf[0], seu_respbuf[1], seu_respbuf[2]); |
| 1191 | } |
| 1192 | |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 1193 | default: |
| 1194 | return socfpga_sip_handler(smc_fid, x1, x2, x3, x4, |
| 1195 | cookie, handle, flags); |
| 1196 | } |
| 1197 | } |
| 1198 | |
Sieu Mun Tang | 044ed48 | 2022-05-11 10:45:19 +0800 | [diff] [blame] | 1199 | uintptr_t sip_smc_handler(uint32_t smc_fid, |
| 1200 | u_register_t x1, |
| 1201 | u_register_t x2, |
| 1202 | u_register_t x3, |
| 1203 | u_register_t x4, |
| 1204 | void *cookie, |
| 1205 | void *handle, |
| 1206 | u_register_t flags) |
| 1207 | { |
| 1208 | uint32_t cmd = smc_fid & INTEL_SIP_SMC_CMD_MASK; |
| 1209 | |
| 1210 | if (cmd >= INTEL_SIP_SMC_CMD_V2_RANGE_BEGIN && |
| 1211 | cmd <= INTEL_SIP_SMC_CMD_V2_RANGE_END) { |
| 1212 | return sip_smc_handler_v2(smc_fid, x1, x2, x3, x4, |
| 1213 | cookie, handle, flags); |
| 1214 | } else { |
| 1215 | return sip_smc_handler_v1(smc_fid, x1, x2, x3, x4, |
| 1216 | cookie, handle, flags); |
| 1217 | } |
| 1218 | } |
| 1219 | |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 1220 | DECLARE_RT_SVC( |
Hadi Asyrafi | 4d9f395 | 2019-10-23 17:35:32 +0800 | [diff] [blame] | 1221 | socfpga_sip_svc, |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 1222 | OEN_SIP_START, |
| 1223 | OEN_SIP_END, |
| 1224 | SMC_TYPE_FAST, |
| 1225 | NULL, |
| 1226 | sip_smc_handler |
| 1227 | ); |
| 1228 | |
| 1229 | DECLARE_RT_SVC( |
Hadi Asyrafi | 4d9f395 | 2019-10-23 17:35:32 +0800 | [diff] [blame] | 1230 | socfpga_sip_svc_std, |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 1231 | OEN_SIP_START, |
| 1232 | OEN_SIP_END, |
| 1233 | SMC_TYPE_YIELD, |
| 1234 | NULL, |
| 1235 | sip_smc_handler |
| 1236 | ); |