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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Antonio Nino Diaz47a90642019-01-31 11:01:26 +00002 * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00007#include <platform_def.h>
8
Sandrine Bailleuxc10bd2c2013-11-12 16:41:16 +00009#include <arch.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010#include <common/bl_common.h>
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +010011#include <el3_common_macros.S>
Bence Szépkúti78dc10c2019-11-07 12:09:24 +010012#include <lib/pmf/aarch64/pmf_asm_macros.S>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000013#include <lib/runtime_instr.h>
14#include <lib/xlat_tables/xlat_mmu_helpers.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010015
16 .globl bl31_entrypoint
Soby Mathewd0194872016-04-29 19:01:30 +010017 .globl bl31_warm_entrypoint
Achin Gupta4f6ad662013-10-25 09:08:21 +010018
Achin Gupta4f6ad662013-10-25 09:08:21 +010019 /* -----------------------------------------------------
20 * bl31_entrypoint() is the cold boot entrypoint,
21 * executed only by the primary cpu.
22 * -----------------------------------------------------
23 */
24
Andrew Thoelke38bde412014-03-18 13:46:55 +000025func bl31_entrypoint
Vikram Kanigirida567432014-04-15 18:08:08 +010026 /* ---------------------------------------------------------------
Soby Mathew73308d02018-01-09 14:36:14 +000027 * Stash the previous bootloader arguments x0 - x3 for later use.
Vikram Kanigirida567432014-04-15 18:08:08 +010028 * ---------------------------------------------------------------
Sandrine Bailleuxc10bd2c2013-11-12 16:41:16 +000029 */
Vikram Kanigiria3a5e4a2014-05-15 18:27:15 +010030 mov x20, x0
31 mov x21, x1
Soby Mathew73308d02018-01-09 14:36:14 +000032 mov x22, x2
33 mov x23, x3
Sandrine Bailleuxc10bd2c2013-11-12 16:41:16 +000034
Louis Mayencourt81de7ab2019-03-22 16:33:23 +000035#if !RESET_TO_BL31
Harry Liebel4f603682014-01-14 18:11:48 +000036 /* ---------------------------------------------------------------------
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +010037 * For !RESET_TO_BL31 systems, only the primary CPU ever reaches
38 * bl31_entrypoint() during the cold boot flow, so the cold/warm boot
39 * and primary/secondary CPU logic should not be executed in this case.
Harry Liebel4f603682014-01-14 18:11:48 +000040 *
David Cunadofee86532017-04-13 22:38:29 +010041 * Also, assume that the previous bootloader has already initialised the
42 * SCTLR_EL3, including the endianness, and has initialised the memory.
Harry Liebel4f603682014-01-14 18:11:48 +000043 * ---------------------------------------------------------------------
44 */
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +010045 el3_entrypoint_common \
David Cunadofee86532017-04-13 22:38:29 +010046 _init_sctlr=0 \
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +010047 _warm_boot_mailbox=0 \
48 _secondary_cold_boot=0 \
49 _init_memory=0 \
50 _init_c_runtime=1 \
Manish Pandeyc8257682019-11-26 11:34:17 +000051 _exception_vectors=runtime_exceptions \
52 _pie_fixup_size=BL31_LIMIT - BL31_BASE
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +010053#else
Louis Mayencourt81de7ab2019-03-22 16:33:23 +000054
Sandrine Bailleux449dbd52015-06-02 17:19:43 +010055 /* ---------------------------------------------------------------------
56 * For RESET_TO_BL31 systems which have a programmable reset address,
57 * bl31_entrypoint() is executed only on the cold boot path so we can
58 * skip the warm boot mailbox mechanism.
59 * ---------------------------------------------------------------------
60 */
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +010061 el3_entrypoint_common \
David Cunadofee86532017-04-13 22:38:29 +010062 _init_sctlr=1 \
Sandrine Bailleux449dbd52015-06-02 17:19:43 +010063 _warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \
Sandrine Bailleuxb21b02f2015-10-30 15:05:17 +000064 _secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +010065 _init_memory=1 \
66 _init_c_runtime=1 \
Manish Pandeyc8257682019-11-26 11:34:17 +000067 _exception_vectors=runtime_exceptions \
68 _pie_fixup_size=BL31_LIMIT - BL31_BASE
Jeenu Viswambharancaa84932014-02-06 10:36:15 +000069
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +010070 /* ---------------------------------------------------------------------
Juan Castillo7d199412015-12-14 09:35:25 +000071 * For RESET_TO_BL31 systems, BL31 is the first bootloader to run so
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +010072 * there's no argument to relay from a previous bootloader. Zero the
73 * arguments passed to the platform layer to reflect that.
74 * ---------------------------------------------------------------------
Achin Gupta4f6ad662013-10-25 09:08:21 +010075 */
Soby Mathew73308d02018-01-09 14:36:14 +000076 mov x20, 0
77 mov x21, 0
78 mov x22, 0
79 mov x23, 0
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +010080#endif /* RESET_TO_BL31 */
Soby Mathew4e28c202018-10-14 08:09:22 +010081
82 /* --------------------------------------------------------------------
Antonio Nino Diaz47a90642019-01-31 11:01:26 +000083 * Perform BL31 setup
84 * --------------------------------------------------------------------
Achin Gupta4f6ad662013-10-25 09:08:21 +010085 */
Soby Mathew73308d02018-01-09 14:36:14 +000086 mov x0, x20
87 mov x1, x21
88 mov x2, x22
89 mov x3, x23
Antonio Nino Diaz47a90642019-01-31 11:01:26 +000090 bl bl31_setup
91
Antonio Nino Diaz47a90642019-01-31 11:01:26 +000092#if ENABLE_PAUTH
Alexei Fedorov90f2e882019-05-24 12:17:09 +010093 /* --------------------------------------------------------------------
Alexei Fedorovf41355c2019-09-13 14:11:59 +010094 * Program APIAKey_EL1 and enable pointer authentication
Alexei Fedorov90f2e882019-05-24 12:17:09 +010095 * --------------------------------------------------------------------
96 */
Alexei Fedorovf41355c2019-09-13 14:11:59 +010097 bl pauth_init_enable_el3
Antonio Nino Diaz47a90642019-01-31 11:01:26 +000098#endif /* ENABLE_PAUTH */
Achin Gupta4f6ad662013-10-25 09:08:21 +010099
Antonio Nino Diaz47a90642019-01-31 11:01:26 +0000100 /* --------------------------------------------------------------------
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100101 * Jump to main function
Antonio Nino Diaz47a90642019-01-31 11:01:26 +0000102 * --------------------------------------------------------------------
Achin Guptab739f222014-01-18 16:50:09 +0000103 */
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000104 bl bl31_main
Achin Guptab739f222014-01-18 16:50:09 +0000105
Antonio Nino Diaz47a90642019-01-31 11:01:26 +0000106 /* --------------------------------------------------------------------
Achin Guptae9c4a642015-09-11 16:03:13 +0100107 * Clean the .data & .bss sections to main memory. This ensures
108 * that any global data which was initialised by the primary CPU
109 * is visible to secondary CPUs before they enable their data
110 * caches and participate in coherency.
Antonio Nino Diaz47a90642019-01-31 11:01:26 +0000111 * --------------------------------------------------------------------
Achin Guptae9c4a642015-09-11 16:03:13 +0100112 */
113 adr x0, __DATA_START__
114 adr x1, __DATA_END__
115 sub x1, x1, x0
116 bl clean_dcache_range
117
118 adr x0, __BSS_START__
119 adr x1, __BSS_END__
120 sub x1, x1, x0
121 bl clean_dcache_range
122
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000123 b el3_exit
Kévin Petita877c252015-03-24 14:03:57 +0000124endfunc bl31_entrypoint
Soby Mathewd0194872016-04-29 19:01:30 +0100125
126 /* --------------------------------------------------------------------
127 * This CPU has been physically powered up. It is either resuming from
128 * suspend or has simply been turned on. In both cases, call the BL31
129 * warmboot entrypoint
130 * --------------------------------------------------------------------
131 */
132func bl31_warm_entrypoint
dp-arm3cac7862016-09-19 11:18:44 +0100133#if ENABLE_RUNTIME_INSTRUMENTATION
134
135 /*
136 * This timestamp update happens with cache off. The next
137 * timestamp collection will need to do cache maintenance prior
138 * to timestamp update.
139 */
Antonio Nino Diazf0b14cf2018-10-04 09:55:23 +0100140 pmf_calc_timestamp_addr rt_instr_svc, RT_INSTR_EXIT_HW_LOW_PWR
dp-arm3cac7862016-09-19 11:18:44 +0100141 mrs x1, cntpct_el0
142 str x1, [x0]
143#endif
144
Soby Mathewd0194872016-04-29 19:01:30 +0100145 /*
146 * On the warm boot path, most of the EL3 initialisations performed by
147 * 'el3_entrypoint_common' must be skipped:
148 *
149 * - Only when the platform bypasses the BL1/BL31 entrypoint by
David Cunadofee86532017-04-13 22:38:29 +0100150 * programming the reset address do we need to initialise SCTLR_EL3.
Soby Mathewd0194872016-04-29 19:01:30 +0100151 * In other cases, we assume this has been taken care by the
152 * entrypoint code.
153 *
154 * - No need to determine the type of boot, we know it is a warm boot.
155 *
156 * - Do not try to distinguish between primary and secondary CPUs, this
157 * notion only exists for a cold boot.
158 *
159 * - No need to initialise the memory or the C runtime environment,
160 * it has been done once and for all on the cold boot path.
161 */
162 el3_entrypoint_common \
David Cunadofee86532017-04-13 22:38:29 +0100163 _init_sctlr=PROGRAMMABLE_RESET_ADDRESS \
Soby Mathewd0194872016-04-29 19:01:30 +0100164 _warm_boot_mailbox=0 \
165 _secondary_cold_boot=0 \
166 _init_memory=0 \
167 _init_c_runtime=0 \
Manish Pandeyc8257682019-11-26 11:34:17 +0000168 _exception_vectors=runtime_exceptions \
169 _pie_fixup_size=0
Soby Mathewd0194872016-04-29 19:01:30 +0100170
Jeenu Viswambharan46144962017-01-05 10:37:21 +0000171 /*
172 * We're about to enable MMU and participate in PSCI state coordination.
173 *
174 * The PSCI implementation invokes platform routines that enable CPUs to
175 * participate in coherency. On a system where CPUs are not
Soby Mathew043fe9c2017-04-10 22:35:42 +0100176 * cache-coherent without appropriate platform specific programming,
177 * having caches enabled until such time might lead to coherency issues
178 * (resulting from stale data getting speculatively fetched, among
179 * others). Therefore we keep data caches disabled even after enabling
180 * the MMU for such platforms.
Jeenu Viswambharan46144962017-01-05 10:37:21 +0000181 *
Soby Mathew043fe9c2017-04-10 22:35:42 +0100182 * On systems with hardware-assisted coherency, or on single cluster
183 * platforms, such platform specific programming is not required to
184 * enter coherency (as CPUs already are); and there's no reason to have
185 * caches disabled either.
Soby Mathewd0194872016-04-29 19:01:30 +0100186 */
Soby Mathew043fe9c2017-04-10 22:35:42 +0100187#if HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY
Jeenu Viswambharane834ee12018-04-27 15:17:03 +0100188 mov x0, xzr
189#else
190 mov x0, #DISABLE_DCACHE
Soby Mathew043fe9c2017-04-10 22:35:42 +0100191#endif
Jeenu Viswambharane834ee12018-04-27 15:17:03 +0100192 bl bl31_plat_enable_mmu
Soby Mathew043fe9c2017-04-10 22:35:42 +0100193
Alexei Fedorove71d26c2019-03-06 11:15:51 +0000194#if ENABLE_PAUTH
Alexei Fedorov90f2e882019-05-24 12:17:09 +0100195 /* --------------------------------------------------------------------
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100196 * Program APIAKey_EL1 and enable pointer authentication
Alexei Fedorov90f2e882019-05-24 12:17:09 +0100197 * --------------------------------------------------------------------
198 */
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100199 bl pauth_init_enable_el3
Alexei Fedorove71d26c2019-03-06 11:15:51 +0000200#endif /* ENABLE_PAUTH */
201
Soby Mathewd0194872016-04-29 19:01:30 +0100202 bl psci_warmboot_entrypoint
203
dp-arm3cac7862016-09-19 11:18:44 +0100204#if ENABLE_RUNTIME_INSTRUMENTATION
Antonio Nino Diazf0b14cf2018-10-04 09:55:23 +0100205 pmf_calc_timestamp_addr rt_instr_svc, RT_INSTR_EXIT_PSCI
dp-arm3cac7862016-09-19 11:18:44 +0100206 mov x19, x0
207
208 /*
209 * Invalidate before updating timestamp to ensure previous timestamp
210 * updates on the same cache line with caches disabled are properly
211 * seen by the same core. Without the cache invalidate, the core might
212 * write into a stale cache line.
213 */
214 mov x1, #PMF_TS_SIZE
215 mov x20, x30
216 bl inv_dcache_range
217 mov x30, x20
218
219 mrs x0, cntpct_el0
220 str x0, [x19]
221#endif
Soby Mathewd0194872016-04-29 19:01:30 +0100222 b el3_exit
223endfunc bl31_warm_entrypoint