Rationalize reset handling code
The attempt to run the CPU reset code as soon as possible after reset
results in highly complex conditional code relating to the
RESET_TO_BL31 option.
This patch relaxes this requirement a little. In the BL1, BL3-1 and
PSCI entrypoints code, the sequence of operations is now as follows:
1) Detect whether it is a cold or warm boot;
2) For cold boot, detect whether it is the primary or a secondary
CPU. This is needed to handle multiple CPUs entering cold reset
simultaneously;
3) Run the CPU init code.
This patch also abstracts the EL3 registers initialisation done by
the BL1, BL3-1 and PSCI entrypoints into common code.
This improves code re-use and consolidates the code flows for
different types of systems.
NOTE: THE FUNCTION plat_secondary_cold_boot() IS NOW EXPECTED TO
NEVER RETURN. THIS PATCH FORCES PLATFORM PORTS THAT RELIED ON THE
FORMER RETRY LOOP AT THE CALL SITE TO MODIFY THEIR IMPLEMENTATION.
OTHERWISE, SECONDARY CPUS WILL PANIC.
Change-Id: If5ecd74d75bee700b1bd718d23d7556b8f863546
diff --git a/bl31/aarch64/bl31_entrypoint.S b/bl31/aarch64/bl31_entrypoint.S
index 1777d26..5350f68 100644
--- a/bl31/aarch64/bl31_entrypoint.S
+++ b/bl31/aarch64/bl31_entrypoint.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -29,8 +29,8 @@
*/
#include <arch.h>
-#include <asm_macros.S>
#include <bl_common.h>
+#include <el3_common_macros.S>
.globl bl31_entrypoint
@@ -42,154 +42,62 @@
*/
func bl31_entrypoint
+#if !RESET_TO_BL31
/* ---------------------------------------------------------------
* Preceding bootloader has populated x0 with a pointer to a
* 'bl31_params' structure & x1 with a pointer to platform
* specific structure
* ---------------------------------------------------------------
*/
-#if !RESET_TO_BL31
mov x20, x0
mov x21, x1
-#else
- /* ---------------------------------------------
- * Set the CPU endianness before doing anything
- * that might involve memory reads or writes.
- * ---------------------------------------------
- */
- mrs x0, sctlr_el3
- bic x0, x0, #SCTLR_EE_BIT
- msr sctlr_el3, x0
- isb
-#endif
-
- /* ---------------------------------------------
- * When RESET_TO_BL31 is true, perform any
- * processor specific actions upon reset e.g.
- * cache, tlb invalidations, errata workarounds
- * etc.
- * When RESET_TO_BL31 is false, perform any
- * processor specific actions which undo or are
- * in addition to the actions performed by the
- * reset handler in the Boot ROM (BL1).
- * ---------------------------------------------
- */
- bl reset_handler
-
- /* ---------------------------------------------
- * Enable the instruction cache, stack pointer
- * and data access alignment checks
- * ---------------------------------------------
- */
- mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
- mrs x0, sctlr_el3
- orr x0, x0, x1
- msr sctlr_el3, x0
- isb
-
- /* ---------------------------------------------
- * Initialise cpu_data early to enable crash
- * reporting to have access to crash stack.
- * Since crash reporting depends on cpu_data to
- * report the unhandled exception, not
- * doing so can lead to recursive exceptions due
- * to a NULL TPIDR_EL3
- * ---------------------------------------------
- */
- bl init_cpu_data_ptr
-
- /* ---------------------------------------------
- * Set the exception vector.
- * ---------------------------------------------
- */
- adr x1, runtime_exceptions
- msr vbar_el3, x1
- isb
-
- /* ---------------------------------------------
- * Enable the SError interrupt now that the
- * exception vectors have been setup.
- * ---------------------------------------------
- */
- msr daifclr, #DAIF_ABT_BIT
/* ---------------------------------------------------------------------
- * The initial state of the Architectural feature trap register
- * (CPTR_EL3) is unknown and it must be set to a known state. All
- * feature traps are disabled. Some bits in this register are marked as
- * Reserved and should not be modified.
+ * For !RESET_TO_BL31 systems, only the primary CPU ever reaches
+ * bl31_entrypoint() during the cold boot flow, so the cold/warm boot
+ * and primary/secondary CPU logic should not be executed in this case.
*
- * CPTR_EL3.TCPAC: This causes a direct access to the CPACR_EL1 from EL1
- * or the CPTR_EL2 from EL2 to trap to EL3 unless it is trapped at EL2.
- * CPTR_EL3.TTA: This causes access to the Trace functionality to trap
- * to EL3 when executed from EL0, EL1, EL2, or EL3. If system register
- * access to trace functionality is not supported, this bit is RES0.
- * CPTR_EL3.TFP: This causes instructions that access the registers
- * associated with Floating Point and Advanced SIMD execution to trap
- * to EL3 when executed from any exception level, unless trapped to EL1
- * or EL2.
+ * Also, assume that the previous bootloader has already set up the CPU
+ * endianness and has initialised the memory.
* ---------------------------------------------------------------------
*/
- mrs x1, cptr_el3
- bic w1, w1, #TCPAC_BIT
- bic w1, w1, #TTA_BIT
- bic w1, w1, #TFP_BIT
- msr cptr_el3, x1
-
-#if RESET_TO_BL31
- /* -------------------------------------------------------
- * Will not return from this macro if it is a warm boot.
- * -------------------------------------------------------
- */
- wait_for_entrypoint
- bl platform_mem_init
-#endif
-
- /* ---------------------------------------------
- * Zero out NOBITS sections. There are 2 of them:
- * - the .bss section;
- * - the coherent memory section.
- * ---------------------------------------------
- */
- ldr x0, =__BSS_START__
- ldr x1, =__BSS_SIZE__
- bl zeromem16
+ el3_entrypoint_common \
+ _set_endian=0 \
+ _warm_boot_mailbox=0 \
+ _secondary_cold_boot=0 \
+ _init_memory=0 \
+ _init_c_runtime=1 \
+ _exception_vectors=runtime_exceptions
-#if USE_COHERENT_MEM
- ldr x0, =__COHERENT_RAM_START__
- ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__
- bl zeromem16
-#endif
-
- /* ---------------------------------------------
- * Use SP_EL0 for the C runtime stack.
- * ---------------------------------------------
+ /* ---------------------------------------------------------------------
+ * Relay the previous bootloader's arguments to the platform layer
+ * ---------------------------------------------------------------------
*/
- msr spsel, #0
+ mov x0, x20
+ mov x1, x21
+#else
+ el3_entrypoint_common \
+ _set_endian=1 \
+ _warm_boot_mailbox=1 \
+ _secondary_cold_boot=1 \
+ _init_memory=1 \
+ _init_c_runtime=1 \
+ _exception_vectors=runtime_exceptions
- /* --------------------------------------------
- * Allocate a stack whose memory will be marked
- * as Normal-IS-WBWA when the MMU is enabled.
- * There is no risk of reading stale stack
- * memory after enabling the MMU as only the
- * primary cpu is running at the moment.
- * --------------------------------------------
+ /* ---------------------------------------------------------------------
+ * For RESET_TO_BL31 systems, BL3-1 is the first bootloader to run so
+ * there's no argument to relay from a previous bootloader. Zero the
+ * arguments passed to the platform layer to reflect that.
+ * ---------------------------------------------------------------------
*/
- mrs x0, mpidr_el1
- bl platform_set_stack
+ mov x0, 0
+ mov x1, 0
+#endif /* RESET_TO_BL31 */
/* ---------------------------------------------
* Perform platform specific early arch. setup
* ---------------------------------------------
*/
-#if RESET_TO_BL31
- mov x0, 0
- mov x1, 0
-#else
- mov x0, x20
- mov x1, x21
-#endif
-
bl bl31_early_platform_setup
bl bl31_plat_arch_setup