blob: 636b1d287c6f5f63cf6ba369470dd14056f8440d [file] [log] [blame]
Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +01002 * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
Sandrine Bailleuxc10bd2c2013-11-12 16:41:16 +000031#include <arch.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010032#include <bl_common.h>
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +010033#include <el3_common_macros.S>
Achin Gupta4f6ad662013-10-25 09:08:21 +010034
35 .globl bl31_entrypoint
36
37
Achin Gupta4f6ad662013-10-25 09:08:21 +010038 /* -----------------------------------------------------
39 * bl31_entrypoint() is the cold boot entrypoint,
40 * executed only by the primary cpu.
41 * -----------------------------------------------------
42 */
43
Andrew Thoelke38bde412014-03-18 13:46:55 +000044func bl31_entrypoint
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +010045#if !RESET_TO_BL31
Vikram Kanigirida567432014-04-15 18:08:08 +010046 /* ---------------------------------------------------------------
47 * Preceding bootloader has populated x0 with a pointer to a
48 * 'bl31_params' structure & x1 with a pointer to platform
49 * specific structure
50 * ---------------------------------------------------------------
Sandrine Bailleuxc10bd2c2013-11-12 16:41:16 +000051 */
Vikram Kanigiria3a5e4a2014-05-15 18:27:15 +010052 mov x20, x0
53 mov x21, x1
Sandrine Bailleuxc10bd2c2013-11-12 16:41:16 +000054
Harry Liebel4f603682014-01-14 18:11:48 +000055 /* ---------------------------------------------------------------------
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +010056 * For !RESET_TO_BL31 systems, only the primary CPU ever reaches
57 * bl31_entrypoint() during the cold boot flow, so the cold/warm boot
58 * and primary/secondary CPU logic should not be executed in this case.
Harry Liebel4f603682014-01-14 18:11:48 +000059 *
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +010060 * Also, assume that the previous bootloader has already set up the CPU
61 * endianness and has initialised the memory.
Harry Liebel4f603682014-01-14 18:11:48 +000062 * ---------------------------------------------------------------------
63 */
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +010064 el3_entrypoint_common \
65 _set_endian=0 \
66 _warm_boot_mailbox=0 \
67 _secondary_cold_boot=0 \
68 _init_memory=0 \
69 _init_c_runtime=1 \
70 _exception_vectors=runtime_exceptions
Sandrine Bailleux65f546a2013-11-28 09:43:06 +000071
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +010072 /* ---------------------------------------------------------------------
73 * Relay the previous bootloader's arguments to the platform layer
74 * ---------------------------------------------------------------------
Jeenu Viswambharancaa84932014-02-06 10:36:15 +000075 */
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +010076 mov x0, x20
77 mov x1, x21
78#else
Sandrine Bailleux449dbd52015-06-02 17:19:43 +010079 /* ---------------------------------------------------------------------
80 * For RESET_TO_BL31 systems which have a programmable reset address,
81 * bl31_entrypoint() is executed only on the cold boot path so we can
82 * skip the warm boot mailbox mechanism.
83 * ---------------------------------------------------------------------
84 */
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +010085 el3_entrypoint_common \
86 _set_endian=1 \
Sandrine Bailleux449dbd52015-06-02 17:19:43 +010087 _warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +010088 _secondary_cold_boot=1 \
89 _init_memory=1 \
90 _init_c_runtime=1 \
91 _exception_vectors=runtime_exceptions
Jeenu Viswambharancaa84932014-02-06 10:36:15 +000092
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +010093 /* ---------------------------------------------------------------------
94 * For RESET_TO_BL31 systems, BL3-1 is the first bootloader to run so
95 * there's no argument to relay from a previous bootloader. Zero the
96 * arguments passed to the platform layer to reflect that.
97 * ---------------------------------------------------------------------
Achin Gupta4f6ad662013-10-25 09:08:21 +010098 */
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +010099 mov x0, 0
100 mov x1, 0
101#endif /* RESET_TO_BL31 */
Achin Gupta4f6ad662013-10-25 09:08:21 +0100102
103 /* ---------------------------------------------
104 * Perform platform specific early arch. setup
105 * ---------------------------------------------
106 */
Achin Gupta4f6ad662013-10-25 09:08:21 +0100107 bl bl31_early_platform_setup
108 bl bl31_plat_arch_setup
109
110 /* ---------------------------------------------
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000111 * Jump to main function.
Achin Guptab739f222014-01-18 16:50:09 +0000112 * ---------------------------------------------
113 */
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000114 bl bl31_main
Achin Guptab739f222014-01-18 16:50:09 +0000115
Achin Guptae9c4a642015-09-11 16:03:13 +0100116 /* -------------------------------------------------------------
117 * Clean the .data & .bss sections to main memory. This ensures
118 * that any global data which was initialised by the primary CPU
119 * is visible to secondary CPUs before they enable their data
120 * caches and participate in coherency.
121 * -------------------------------------------------------------
122 */
123 adr x0, __DATA_START__
124 adr x1, __DATA_END__
125 sub x1, x1, x0
126 bl clean_dcache_range
127
128 adr x0, __BSS_START__
129 adr x1, __BSS_END__
130 sub x1, x1, x0
131 bl clean_dcache_range
132
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000133 b el3_exit
Kévin Petita877c252015-03-24 14:03:57 +0000134endfunc bl31_entrypoint