blob: ff050e4da80b95b70fdf6998120dcd3f8ee20c74 [file] [log] [blame]
Hadi Asyrafi616da772019-06-27 11:34:03 +08001/*
Jit Loon Lim86f6fb32023-05-17 12:26:11 +08002 * Copyright (c) 2019-2023, ARM Limited and Contributors. All rights reserved.
Hadi Asyrafi616da772019-06-27 11:34:03 +08003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <assert.h>
8#include <common/debug.h>
9#include <common/runtime_svc.h>
Hadi Asyrafi67942302019-10-22 13:28:51 +080010#include <lib/mmio.h>
Hadi Asyrafi616da772019-06-27 11:34:03 +080011#include <tools_share/uuid.h>
12
Sieu Mun Tang9f22cbf2022-03-02 11:04:09 +080013#include "socfpga_fcs.h"
Hadi Asyrafi6f8a2b22019-10-23 18:34:14 +080014#include "socfpga_mailbox.h"
Jit Loon Lim86f6fb32023-05-17 12:26:11 +080015#include "socfpga_plat_def.h"
Hadi Asyrafi36a9f302019-12-24 10:42:52 +080016#include "socfpga_reset_manager.h"
Hadi Asyrafiab1132f2019-10-22 10:31:45 +080017#include "socfpga_sip_svc.h"
Jit Loon Lim86f6fb32023-05-17 12:26:11 +080018#include "socfpga_system_manager.h"
Hadi Asyrafi616da772019-06-27 11:34:03 +080019
20/* Total buffer the driver can hold */
21#define FPGA_CONFIG_BUFFER_SIZE 4
22
Sieu Mun Tangc3667602022-05-13 14:55:05 +080023static config_type request_type = NO_REQUEST;
Abdul Halim, Muhammad Hadi Asyrafi20a07f32020-05-18 11:16:48 +080024static int current_block, current_buffer;
Abdul Halim, Muhammad Hadi Asyrafib251c332020-05-29 12:13:17 +080025static int read_block, max_blocks;
Abdul Halim, Muhammad Hadi Asyrafi20a07f32020-05-18 11:16:48 +080026static uint32_t send_id, rcv_id;
27static uint32_t bytes_per_block, blocks_submitted;
Sieu Mun Tang54064982022-04-28 22:40:58 +080028static bool bridge_disable;
Hadi Asyrafi616da772019-06-27 11:34:03 +080029
Sieu Mun Tange6d5de92022-04-28 22:21:01 +080030/* RSU static variables */
Chee Hong Ang2cfd8ec2020-05-13 11:44:04 +080031static uint32_t rsu_dcmf_ver[4] = {0};
Sieu Mun Tange6d5de92022-04-28 22:21:01 +080032static uint16_t rsu_dcmf_stat[4] = {0};
Sieu Mun Tangc3667602022-05-13 14:55:05 +080033static uint32_t rsu_max_retry;
Hadi Asyrafi616da772019-06-27 11:34:03 +080034
35/* SiP Service UUID */
36DEFINE_SVC_UUID2(intl_svc_uid,
37 0xa85273b0, 0xe85a, 0x4862, 0xa6, 0x2a,
38 0xfa, 0x88, 0x88, 0x17, 0x68, 0x81);
39
Hadi Asyraficee6aa92019-12-17 15:25:04 +080040static uint64_t socfpga_sip_handler(uint32_t smc_fid,
Hadi Asyrafi616da772019-06-27 11:34:03 +080041 uint64_t x1,
42 uint64_t x2,
43 uint64_t x3,
44 uint64_t x4,
45 void *cookie,
46 void *handle,
47 uint64_t flags)
48{
49 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
50 SMC_RET1(handle, SMC_UNK);
51}
52
53struct fpga_config_info fpga_config_buffers[FPGA_CONFIG_BUFFER_SIZE];
54
Hadi Asyrafif3a7c142019-11-12 16:29:03 +080055static int intel_fpga_sdm_write_buffer(struct fpga_config_info *buffer)
Hadi Asyrafi616da772019-06-27 11:34:03 +080056{
Abdul Halim, Muhammad Hadi Asyrafid84bfef2020-02-25 16:28:10 +080057 uint32_t args[3];
Hadi Asyrafi616da772019-06-27 11:34:03 +080058
59 while (max_blocks > 0 && buffer->size > buffer->size_written) {
Hadi Asyrafif3a7c142019-11-12 16:29:03 +080060 args[0] = (1<<8);
61 args[1] = buffer->addr + buffer->size_written;
62 if (buffer->size - buffer->size_written <= bytes_per_block) {
Hadi Asyrafi616da772019-06-27 11:34:03 +080063 args[2] = buffer->size - buffer->size_written;
Hadi Asyrafi616da772019-06-27 11:34:03 +080064 current_buffer++;
65 current_buffer %= FPGA_CONFIG_BUFFER_SIZE;
Sieu Mun Tang28af1652022-05-09 10:48:53 +080066 } else {
Hadi Asyrafi616da772019-06-27 11:34:03 +080067 args[2] = bytes_per_block;
Sieu Mun Tang28af1652022-05-09 10:48:53 +080068 }
Hadi Asyrafif3a7c142019-11-12 16:29:03 +080069
70 buffer->size_written += args[2];
Abdul Halim, Muhammad Hadi Asyrafi20a07f32020-05-18 11:16:48 +080071 mailbox_send_cmd_async(&send_id, MBOX_RECONFIG_DATA, args,
Abdul Halim, Muhammad Hadi Asyrafi118ab212020-10-15 15:27:18 +080072 3U, CMD_INDIRECT);
Hadi Asyrafif3a7c142019-11-12 16:29:03 +080073
74 buffer->subblocks_sent++;
Hadi Asyrafi616da772019-06-27 11:34:03 +080075 max_blocks--;
76 }
Hadi Asyrafif3a7c142019-11-12 16:29:03 +080077
78 return !max_blocks;
Hadi Asyrafi616da772019-06-27 11:34:03 +080079}
80
81static int intel_fpga_sdm_write_all(void)
82{
Sieu Mun Tang28af1652022-05-09 10:48:53 +080083 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
Hadi Asyrafif3a7c142019-11-12 16:29:03 +080084 if (intel_fpga_sdm_write_buffer(
Sieu Mun Tang28af1652022-05-09 10:48:53 +080085 &fpga_config_buffers[current_buffer])) {
Hadi Asyrafif3a7c142019-11-12 16:29:03 +080086 break;
Sieu Mun Tang28af1652022-05-09 10:48:53 +080087 }
88 }
Hadi Asyrafi616da772019-06-27 11:34:03 +080089 return 0;
90}
91
Sieu Mun Tangc3667602022-05-13 14:55:05 +080092static uint32_t intel_mailbox_fpga_config_isdone(void)
Hadi Asyrafi616da772019-06-27 11:34:03 +080093{
Hadi Asyrafi0c6dae22019-12-17 23:33:39 +080094 uint32_t ret;
95
Sieu Mun Tangc3667602022-05-13 14:55:05 +080096 switch (request_type) {
97 case RECONFIGURATION:
98 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS,
99 true);
100 break;
101 case BITSTREAM_AUTH:
102 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS,
103 false);
104 break;
105 default:
106 ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS,
107 false);
108 break;
Kris Chapline768dfa2021-06-25 11:31:52 +0100109 }
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800110
Abdul Halim, Muhammad Hadi Asyrafi959143d2020-12-29 16:49:23 +0800111 if (ret != 0U) {
Kris Chapline768dfa2021-06-25 11:31:52 +0100112 if (ret == MBOX_CFGSTAT_STATE_CONFIG) {
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800113 return INTEL_SIP_SMC_STATUS_BUSY;
Kris Chapline768dfa2021-06-25 11:31:52 +0100114 } else {
Sieu Mun Tangc3667602022-05-13 14:55:05 +0800115 request_type = NO_REQUEST;
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800116 return INTEL_SIP_SMC_STATUS_ERROR;
Kris Chapline768dfa2021-06-25 11:31:52 +0100117 }
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800118 }
119
Sieu Mun Tangc3667602022-05-13 14:55:05 +0800120 if (bridge_disable != 0U) {
Sieu Mun Tang82cf5df2022-05-05 17:07:21 +0800121 socfpga_bridges_enable(~0); /* Enable bridge */
Sieu Mun Tang54064982022-04-28 22:40:58 +0800122 bridge_disable = false;
Hadi Asyrafi36a9f302019-12-24 10:42:52 +0800123 }
Sieu Mun Tangc3667602022-05-13 14:55:05 +0800124 request_type = NO_REQUEST;
Hadi Asyrafi36a9f302019-12-24 10:42:52 +0800125
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800126 return INTEL_SIP_SMC_STATUS_OK;
Hadi Asyrafi616da772019-06-27 11:34:03 +0800127}
128
129static int mark_last_buffer_xfer_completed(uint32_t *buffer_addr_completed)
130{
131 int i;
132
133 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
134 if (fpga_config_buffers[i].block_number == current_block) {
135 fpga_config_buffers[i].subblocks_sent--;
136 if (fpga_config_buffers[i].subblocks_sent == 0
137 && fpga_config_buffers[i].size <=
138 fpga_config_buffers[i].size_written) {
139 fpga_config_buffers[i].write_requested = 0;
140 current_block++;
141 *buffer_addr_completed =
142 fpga_config_buffers[i].addr;
143 return 0;
144 }
145 }
146 }
147
148 return -1;
149}
150
Hadi Asyraficee6aa92019-12-17 15:25:04 +0800151static int intel_fpga_config_completed_write(uint32_t *completed_addr,
Abdul Halim, Muhammad Hadi Asyrafi20a07f32020-05-18 11:16:48 +0800152 uint32_t *count, uint32_t *job_id)
Hadi Asyrafi616da772019-06-27 11:34:03 +0800153{
Hadi Asyrafi616da772019-06-27 11:34:03 +0800154 uint32_t resp[5];
Sieu Mun Tang24682662022-02-19 21:49:48 +0800155 unsigned int resp_len = ARRAY_SIZE(resp);
156 int status = INTEL_SIP_SMC_STATUS_OK;
Hadi Asyrafi616da772019-06-27 11:34:03 +0800157 int all_completed = 1;
Sieu Mun Tang24682662022-02-19 21:49:48 +0800158 *count = 0;
Hadi Asyrafi616da772019-06-27 11:34:03 +0800159
Tien Hock, Loh500b2322019-10-30 14:49:40 +0800160 while (*count < 3) {
Hadi Asyrafi616da772019-06-27 11:34:03 +0800161
Sieu Mun Tang24682662022-02-19 21:49:48 +0800162 status = mailbox_read_response(job_id,
163 resp, &resp_len);
Hadi Asyrafi616da772019-06-27 11:34:03 +0800164
Sieu Mun Tang9f22cbf2022-03-02 11:04:09 +0800165 if (status < 0) {
Tien Hock, Loh500b2322019-10-30 14:49:40 +0800166 break;
Sieu Mun Tang9f22cbf2022-03-02 11:04:09 +0800167 }
Hadi Asyrafi616da772019-06-27 11:34:03 +0800168
Hadi Asyrafi616da772019-06-27 11:34:03 +0800169 max_blocks++;
Tien Hock, Loh500b2322019-10-30 14:49:40 +0800170
Hadi Asyrafi616da772019-06-27 11:34:03 +0800171 if (mark_last_buffer_xfer_completed(
Sieu Mun Tang9f22cbf2022-03-02 11:04:09 +0800172 &completed_addr[*count]) == 0) {
Hadi Asyrafi616da772019-06-27 11:34:03 +0800173 *count = *count + 1;
Sieu Mun Tang9f22cbf2022-03-02 11:04:09 +0800174 } else {
Hadi Asyrafi616da772019-06-27 11:34:03 +0800175 break;
Sieu Mun Tang9f22cbf2022-03-02 11:04:09 +0800176 }
Hadi Asyrafi616da772019-06-27 11:34:03 +0800177 }
178
179 if (*count <= 0) {
Sieu Mun Tang9f22cbf2022-03-02 11:04:09 +0800180 if (status != MBOX_NO_RESPONSE &&
181 status != MBOX_TIMEOUT && resp_len != 0) {
Tien Hock, Loh500b2322019-10-30 14:49:40 +0800182 mailbox_clear_response();
Sieu Mun Tangc3667602022-05-13 14:55:05 +0800183 request_type = NO_REQUEST;
Hadi Asyrafi616da772019-06-27 11:34:03 +0800184 return INTEL_SIP_SMC_STATUS_ERROR;
185 }
186
187 *count = 0;
188 }
189
190 intel_fpga_sdm_write_all();
191
Sieu Mun Tang28af1652022-05-09 10:48:53 +0800192 if (*count > 0) {
Hadi Asyrafi616da772019-06-27 11:34:03 +0800193 status = INTEL_SIP_SMC_STATUS_OK;
Sieu Mun Tang28af1652022-05-09 10:48:53 +0800194 } else if (*count == 0) {
Hadi Asyrafi616da772019-06-27 11:34:03 +0800195 status = INTEL_SIP_SMC_STATUS_BUSY;
Sieu Mun Tang28af1652022-05-09 10:48:53 +0800196 }
Hadi Asyrafi616da772019-06-27 11:34:03 +0800197
198 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
199 if (fpga_config_buffers[i].write_requested != 0) {
200 all_completed = 0;
201 break;
202 }
203 }
204
Sieu Mun Tang28af1652022-05-09 10:48:53 +0800205 if (all_completed == 1) {
Hadi Asyrafi616da772019-06-27 11:34:03 +0800206 return INTEL_SIP_SMC_STATUS_OK;
Sieu Mun Tang28af1652022-05-09 10:48:53 +0800207 }
Hadi Asyrafi616da772019-06-27 11:34:03 +0800208
209 return status;
210}
211
Sieu Mun Tang54064982022-04-28 22:40:58 +0800212static int intel_fpga_config_start(uint32_t flag)
Hadi Asyrafi616da772019-06-27 11:34:03 +0800213{
Sieu Mun Tang24682662022-02-19 21:49:48 +0800214 uint32_t argument = 0x1;
Hadi Asyrafi616da772019-06-27 11:34:03 +0800215 uint32_t response[3];
216 int status = 0;
Sieu Mun Tang24682662022-02-19 21:49:48 +0800217 unsigned int size = 0;
218 unsigned int resp_len = ARRAY_SIZE(response);
Hadi Asyrafi616da772019-06-27 11:34:03 +0800219
Sieu Mun Tangc3667602022-05-13 14:55:05 +0800220 request_type = RECONFIGURATION;
221
Sieu Mun Tang54064982022-04-28 22:40:58 +0800222 if (!CONFIG_TEST_FLAG(flag, PARTIAL_CONFIG)) {
223 bridge_disable = true;
Abdul Halim, Muhammad Hadi Asyrafib251c332020-05-29 12:13:17 +0800224 }
Hadi Asyrafi36a9f302019-12-24 10:42:52 +0800225
Sieu Mun Tang54064982022-04-28 22:40:58 +0800226 if (CONFIG_TEST_FLAG(flag, AUTHENTICATION)) {
227 size = 1;
228 bridge_disable = false;
Sieu Mun Tangc3667602022-05-13 14:55:05 +0800229 request_type = BITSTREAM_AUTH;
Sieu Mun Tang54064982022-04-28 22:40:58 +0800230 }
231
Tien Hock, Loh500b2322019-10-30 14:49:40 +0800232 mailbox_clear_response();
233
Sieu Mun Tang24682662022-02-19 21:49:48 +0800234 mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_CANCEL, NULL, 0U,
235 CMD_CASUAL, NULL, NULL);
Tien Hock, Loh500b2322019-10-30 14:49:40 +0800236
Sieu Mun Tang24682662022-02-19 21:49:48 +0800237 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_RECONFIG, &argument, size,
238 CMD_CASUAL, response, &resp_len);
Hadi Asyrafi616da772019-06-27 11:34:03 +0800239
Abdul Halim, Muhammad Hadi Asyrafifbc39132020-11-20 11:06:00 +0800240 if (status < 0) {
Sieu Mun Tang54064982022-04-28 22:40:58 +0800241 bridge_disable = false;
Sieu Mun Tangc3667602022-05-13 14:55:05 +0800242 request_type = NO_REQUEST;
Abdul Halim, Muhammad Hadi Asyrafifbc39132020-11-20 11:06:00 +0800243 return INTEL_SIP_SMC_STATUS_ERROR;
244 }
Hadi Asyrafi616da772019-06-27 11:34:03 +0800245
246 max_blocks = response[0];
247 bytes_per_block = response[1];
248
249 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
250 fpga_config_buffers[i].size = 0;
251 fpga_config_buffers[i].size_written = 0;
252 fpga_config_buffers[i].addr = 0;
253 fpga_config_buffers[i].write_requested = 0;
254 fpga_config_buffers[i].block_number = 0;
255 fpga_config_buffers[i].subblocks_sent = 0;
256 }
257
258 blocks_submitted = 0;
259 current_block = 0;
Tien Hock, Loh500b2322019-10-30 14:49:40 +0800260 read_block = 0;
Hadi Asyrafi616da772019-06-27 11:34:03 +0800261 current_buffer = 0;
262
Sieu Mun Tang54064982022-04-28 22:40:58 +0800263 /* Disable bridge on full reconfiguration */
264 if (bridge_disable) {
Sieu Mun Tang82cf5df2022-05-05 17:07:21 +0800265 socfpga_bridges_disable(~0);
Hadi Asyrafi36a9f302019-12-24 10:42:52 +0800266 }
267
Abdul Halim, Muhammad Hadi Asyrafifbc39132020-11-20 11:06:00 +0800268 return INTEL_SIP_SMC_STATUS_OK;
Hadi Asyrafi616da772019-06-27 11:34:03 +0800269}
270
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800271static bool is_fpga_config_buffer_full(void)
272{
Sieu Mun Tang28af1652022-05-09 10:48:53 +0800273 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
274 if (!fpga_config_buffers[i].write_requested) {
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800275 return false;
Sieu Mun Tang28af1652022-05-09 10:48:53 +0800276 }
277 }
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800278 return true;
279}
280
Abdul Halim, Muhammad Hadi Asyrafi20a07f32020-05-18 11:16:48 +0800281bool is_address_in_ddr_range(uint64_t addr, uint64_t size)
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800282{
Abdul Halim, Muhammad Hadi Asyrafi461f5442020-07-03 13:22:09 +0800283 if (!addr && !size) {
284 return true;
285 }
Sieu Mun Tang28af1652022-05-09 10:48:53 +0800286 if (size > (UINT64_MAX - addr)) {
Abdul Halim, Muhammad Hadi Asyrafic39a0e02020-02-06 19:18:41 +0800287 return false;
Sieu Mun Tang28af1652022-05-09 10:48:53 +0800288 }
289 if (addr < BL31_LIMIT) {
Abdul Halim, Muhammad Hadi Asyrafic39a0e02020-02-06 19:18:41 +0800290 return false;
Sieu Mun Tang28af1652022-05-09 10:48:53 +0800291 }
292 if (addr + size > DRAM_BASE + DRAM_SIZE) {
Abdul Halim, Muhammad Hadi Asyrafic39a0e02020-02-06 19:18:41 +0800293 return false;
Sieu Mun Tang28af1652022-05-09 10:48:53 +0800294 }
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800295
Abdul Halim, Muhammad Hadi Asyrafic39a0e02020-02-06 19:18:41 +0800296 return true;
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800297}
Hadi Asyrafi616da772019-06-27 11:34:03 +0800298
Hadi Asyraficee6aa92019-12-17 15:25:04 +0800299static uint32_t intel_fpga_config_write(uint64_t mem, uint64_t size)
Hadi Asyrafi616da772019-06-27 11:34:03 +0800300{
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800301 int i;
Hadi Asyrafi616da772019-06-27 11:34:03 +0800302
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800303 intel_fpga_sdm_write_all();
Hadi Asyrafi616da772019-06-27 11:34:03 +0800304
Abdul Halim, Muhammad Hadi Asyrafic39a0e02020-02-06 19:18:41 +0800305 if (!is_address_in_ddr_range(mem, size) ||
Abdul Halim, Muhammad Hadi Asyrafi351e8842020-11-05 18:00:03 +0800306 is_fpga_config_buffer_full()) {
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800307 return INTEL_SIP_SMC_STATUS_REJECTED;
Abdul Halim, Muhammad Hadi Asyrafi351e8842020-11-05 18:00:03 +0800308 }
Hadi Asyrafi616da772019-06-27 11:34:03 +0800309
310 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800311 int j = (i + current_buffer) % FPGA_CONFIG_BUFFER_SIZE;
312
313 if (!fpga_config_buffers[j].write_requested) {
314 fpga_config_buffers[j].addr = mem;
315 fpga_config_buffers[j].size = size;
316 fpga_config_buffers[j].size_written = 0;
317 fpga_config_buffers[j].write_requested = 1;
318 fpga_config_buffers[j].block_number =
Hadi Asyrafi616da772019-06-27 11:34:03 +0800319 blocks_submitted++;
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800320 fpga_config_buffers[j].subblocks_sent = 0;
Hadi Asyrafi616da772019-06-27 11:34:03 +0800321 break;
322 }
323 }
324
Abdul Halim, Muhammad Hadi Asyrafi351e8842020-11-05 18:00:03 +0800325 if (is_fpga_config_buffer_full()) {
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800326 return INTEL_SIP_SMC_STATUS_BUSY;
Abdul Halim, Muhammad Hadi Asyrafi351e8842020-11-05 18:00:03 +0800327 }
Hadi Asyrafi616da772019-06-27 11:34:03 +0800328
Hadi Asyrafif3a7c142019-11-12 16:29:03 +0800329 return INTEL_SIP_SMC_STATUS_OK;
Hadi Asyrafi616da772019-06-27 11:34:03 +0800330}
331
Hadi Asyrafi67942302019-10-22 13:28:51 +0800332static int is_out_of_sec_range(uint64_t reg_addr)
333{
Siew Chin Lim869d4f52021-05-11 21:12:22 +0800334#if DEBUG
335 return 0;
336#endif
337
Hadi Asyrafi67942302019-10-22 13:28:51 +0800338 switch (reg_addr) {
339 case(0xF8011100): /* ECCCTRL1 */
340 case(0xF8011104): /* ECCCTRL2 */
341 case(0xF8011110): /* ERRINTEN */
342 case(0xF8011114): /* ERRINTENS */
343 case(0xF8011118): /* ERRINTENR */
344 case(0xF801111C): /* INTMODE */
345 case(0xF8011120): /* INTSTAT */
346 case(0xF8011124): /* DIAGINTTEST */
347 case(0xF801112C): /* DERRADDRA */
Sieu Mun Tangbd8da632022-09-28 15:58:28 +0800348 case(0xFA000000): /* SMMU SCR0 */
349 case(0xFA000004): /* SMMU SCR1 */
350 case(0xFA000400): /* SMMU NSCR0 */
351 case(0xFA004000): /* SMMU SSD0_REG */
352 case(0xFA000820): /* SMMU SMR8 */
353 case(0xFA000c20): /* SMMU SCR8 */
354 case(0xFA028000): /* SMMU CB8_SCTRL */
355 case(0xFA001020): /* SMMU CBAR8 */
356 case(0xFA028030): /* SMMU TCR_LPAE */
357 case(0xFA028020): /* SMMU CB8_TTBR0_LOW */
358 case(0xFA028024): /* SMMU CB8_PRRR_HIGH */
359 case(0xFA028038): /* SMMU CB8_PRRR_MIR0 */
360 case(0xFA02803C): /* SMMU CB8_PRRR_MIR1 */
361 case(0xFA028010): /* SMMU_CB8)TCR2 */
362 case(0xFFD080A4): /* SDM SMMU STREAM ID REG */
363 case(0xFA001820): /* SMMU_CBA2R8 */
364 case(0xFA000074): /* SMMU_STLBGSTATUS */
365 case(0xFA0287F4): /* SMMU_CB8_TLBSTATUS */
366 case(0xFA000060): /* SMMU_STLBIALL */
367 case(0xFA000070): /* SMMU_STLBGSYNC */
368 case(0xFA028618): /* CB8_TLBALL */
369 case(0xFA0287F0): /* CB8_TLBSYNC */
Hadi Asyrafi67942302019-10-22 13:28:51 +0800370 case(0xFFD12028): /* SDMMCGRP_CTRL */
371 case(0xFFD12044): /* EMAC0 */
372 case(0xFFD12048): /* EMAC1 */
373 case(0xFFD1204C): /* EMAC2 */
374 case(0xFFD12090): /* ECC_INT_MASK_VALUE */
375 case(0xFFD12094): /* ECC_INT_MASK_SET */
376 case(0xFFD12098): /* ECC_INT_MASK_CLEAR */
377 case(0xFFD1209C): /* ECC_INTSTATUS_SERR */
378 case(0xFFD120A0): /* ECC_INTSTATUS_DERR */
379 case(0xFFD120C0): /* NOC_TIMEOUT */
380 case(0xFFD120C4): /* NOC_IDLEREQ_SET */
381 case(0xFFD120C8): /* NOC_IDLEREQ_CLR */
382 case(0xFFD120D0): /* NOC_IDLEACK */
383 case(0xFFD120D4): /* NOC_IDLESTATUS */
384 case(0xFFD12200): /* BOOT_SCRATCH_COLD0 */
385 case(0xFFD12204): /* BOOT_SCRATCH_COLD1 */
386 case(0xFFD12220): /* BOOT_SCRATCH_COLD8 */
387 case(0xFFD12224): /* BOOT_SCRATCH_COLD9 */
388 return 0;
389
390 default:
391 break;
392 }
393
394 return -1;
395}
396
397/* Secure register access */
398uint32_t intel_secure_reg_read(uint64_t reg_addr, uint32_t *retval)
399{
Sieu Mun Tang28af1652022-05-09 10:48:53 +0800400 if (is_out_of_sec_range(reg_addr)) {
Hadi Asyrafi67942302019-10-22 13:28:51 +0800401 return INTEL_SIP_SMC_STATUS_ERROR;
Sieu Mun Tang28af1652022-05-09 10:48:53 +0800402 }
Hadi Asyrafi67942302019-10-22 13:28:51 +0800403
404 *retval = mmio_read_32(reg_addr);
405
406 return INTEL_SIP_SMC_STATUS_OK;
407}
408
409uint32_t intel_secure_reg_write(uint64_t reg_addr, uint32_t val,
410 uint32_t *retval)
411{
Sieu Mun Tang28af1652022-05-09 10:48:53 +0800412 if (is_out_of_sec_range(reg_addr)) {
Hadi Asyrafi67942302019-10-22 13:28:51 +0800413 return INTEL_SIP_SMC_STATUS_ERROR;
Sieu Mun Tang28af1652022-05-09 10:48:53 +0800414 }
Hadi Asyrafi67942302019-10-22 13:28:51 +0800415
416 mmio_write_32(reg_addr, val);
417
418 return intel_secure_reg_read(reg_addr, retval);
419}
420
421uint32_t intel_secure_reg_update(uint64_t reg_addr, uint32_t mask,
422 uint32_t val, uint32_t *retval)
423{
424 if (!intel_secure_reg_read(reg_addr, retval)) {
425 *retval &= ~mask;
Siew Chin Lima0763152021-07-10 00:55:35 +0800426 *retval |= val & mask;
Hadi Asyrafi67942302019-10-22 13:28:51 +0800427 return intel_secure_reg_write(reg_addr, *retval, retval);
428 }
429
430 return INTEL_SIP_SMC_STATUS_ERROR;
431}
432
Hadi Asyrafi593c4c52019-12-17 19:22:17 +0800433/* Intel Remote System Update (RSU) services */
434uint64_t intel_rsu_update_address;
435
Abdul Halim, Muhammad Hadi Asyrafi118ab212020-10-15 15:27:18 +0800436static uint32_t intel_rsu_status(uint64_t *respbuf, unsigned int respbuf_sz)
Hadi Asyrafi593c4c52019-12-17 19:22:17 +0800437{
Sieu Mun Tang28af1652022-05-09 10:48:53 +0800438 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) {
Abdul Halim, Muhammad Hadi Asyrafi25f623e2020-02-27 10:23:48 +0800439 return INTEL_SIP_SMC_RSU_ERROR;
Sieu Mun Tang28af1652022-05-09 10:48:53 +0800440 }
Hadi Asyrafi593c4c52019-12-17 19:22:17 +0800441
442 return INTEL_SIP_SMC_STATUS_OK;
443}
444
445static uint32_t intel_rsu_update(uint64_t update_address)
446{
Jit Loon Lim581ad472023-05-17 12:26:11 +0800447 if (update_address > SIZE_MAX) {
448 return INTEL_SIP_SMC_STATUS_REJECTED;
449 }
450
Hadi Asyrafi593c4c52019-12-17 19:22:17 +0800451 intel_rsu_update_address = update_address;
452 return INTEL_SIP_SMC_STATUS_OK;
453}
454
Abdul Halim, Muhammad Hadi Asyrafid84bfef2020-02-25 16:28:10 +0800455static uint32_t intel_rsu_notify(uint32_t execution_stage)
Hadi Asyrafi593c4c52019-12-17 19:22:17 +0800456{
Sieu Mun Tang28af1652022-05-09 10:48:53 +0800457 if (mailbox_hps_stage_notify(execution_stage) < 0) {
Abdul Halim, Muhammad Hadi Asyrafi25f623e2020-02-27 10:23:48 +0800458 return INTEL_SIP_SMC_RSU_ERROR;
Sieu Mun Tang28af1652022-05-09 10:48:53 +0800459 }
Hadi Asyrafi593c4c52019-12-17 19:22:17 +0800460
461 return INTEL_SIP_SMC_STATUS_OK;
462}
463
464static uint32_t intel_rsu_retry_counter(uint32_t *respbuf, uint32_t respbuf_sz,
465 uint32_t *ret_stat)
466{
Sieu Mun Tang28af1652022-05-09 10:48:53 +0800467 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) {
Abdul Halim, Muhammad Hadi Asyrafi25f623e2020-02-27 10:23:48 +0800468 return INTEL_SIP_SMC_RSU_ERROR;
Sieu Mun Tang28af1652022-05-09 10:48:53 +0800469 }
Hadi Asyrafi593c4c52019-12-17 19:22:17 +0800470
471 *ret_stat = respbuf[8];
472 return INTEL_SIP_SMC_STATUS_OK;
473}
474
Chee Hong Ang2cfd8ec2020-05-13 11:44:04 +0800475static uint32_t intel_rsu_copy_dcmf_version(uint64_t dcmf_ver_1_0,
476 uint64_t dcmf_ver_3_2)
477{
478 rsu_dcmf_ver[0] = dcmf_ver_1_0;
479 rsu_dcmf_ver[1] = dcmf_ver_1_0 >> 32;
480 rsu_dcmf_ver[2] = dcmf_ver_3_2;
481 rsu_dcmf_ver[3] = dcmf_ver_3_2 >> 32;
482
483 return INTEL_SIP_SMC_STATUS_OK;
484}
485
Sieu Mun Tange6d5de92022-04-28 22:21:01 +0800486static uint32_t intel_rsu_copy_dcmf_status(uint64_t dcmf_stat)
487{
488 rsu_dcmf_stat[0] = 0xFFFF & (dcmf_stat >> (0 * 16));
489 rsu_dcmf_stat[1] = 0xFFFF & (dcmf_stat >> (1 * 16));
490 rsu_dcmf_stat[2] = 0xFFFF & (dcmf_stat >> (2 * 16));
491 rsu_dcmf_stat[3] = 0xFFFF & (dcmf_stat >> (3 * 16));
492
493 return INTEL_SIP_SMC_STATUS_OK;
494}
495
Kris Chapline768dfa2021-06-25 11:31:52 +0100496/* Intel HWMON services */
497static uint32_t intel_hwmon_readtemp(uint32_t chan, uint32_t *retval)
498{
Kris Chapline768dfa2021-06-25 11:31:52 +0100499 if (mailbox_hwmon_readtemp(chan, retval) < 0) {
500 return INTEL_SIP_SMC_STATUS_ERROR;
501 }
502
503 return INTEL_SIP_SMC_STATUS_OK;
504}
505
506static uint32_t intel_hwmon_readvolt(uint32_t chan, uint32_t *retval)
507{
Kris Chapline768dfa2021-06-25 11:31:52 +0100508 if (mailbox_hwmon_readvolt(chan, retval) < 0) {
509 return INTEL_SIP_SMC_STATUS_ERROR;
510 }
511
512 return INTEL_SIP_SMC_STATUS_OK;
513}
514
Hadi Asyrafia33e8102019-12-17 19:30:41 +0800515/* Mailbox services */
Abdul Halim, Muhammad Hadi Asyrafid9006fc2021-02-05 11:50:58 +0800516static uint32_t intel_smc_fw_version(uint32_t *fw_version)
517{
Sieu Mun Tangbfda95a2022-04-27 18:54:10 +0800518 int status;
519 unsigned int resp_len = CONFIG_STATUS_WORD_SIZE;
520 uint32_t resp_data[CONFIG_STATUS_WORD_SIZE] = {0U};
521
522 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CONFIG_STATUS, NULL, 0U,
523 CMD_CASUAL, resp_data, &resp_len);
524
525 if (status < 0) {
526 return INTEL_SIP_SMC_STATUS_ERROR;
527 }
528
529 if (resp_len <= CONFIG_STATUS_FW_VER_OFFSET) {
530 return INTEL_SIP_SMC_STATUS_ERROR;
531 }
532
533 *fw_version = resp_data[CONFIG_STATUS_FW_VER_OFFSET] & CONFIG_STATUS_FW_VER_MASK;
Abdul Halim, Muhammad Hadi Asyrafid9006fc2021-02-05 11:50:58 +0800534
535 return INTEL_SIP_SMC_STATUS_OK;
536}
537
Sieu Mun Tang24682662022-02-19 21:49:48 +0800538static uint32_t intel_mbox_send_cmd(uint32_t cmd, uint32_t *args,
Sieu Mun Tang7420c532022-05-10 23:17:04 +0800539 unsigned int len, uint32_t urgent, uint64_t response,
Sieu Mun Tang24682662022-02-19 21:49:48 +0800540 unsigned int resp_len, int *mbox_status,
541 unsigned int *len_in_resp)
Hadi Asyrafia33e8102019-12-17 19:30:41 +0800542{
Abdul Halim, Muhammad Hadi Asyrafic39a0e02020-02-06 19:18:41 +0800543 *len_in_resp = 0;
Sieu Mun Tang96bbdca2022-04-12 15:00:13 +0800544 *mbox_status = GENERIC_RESPONSE_ERROR;
Abdul Halim, Muhammad Hadi Asyrafic39a0e02020-02-06 19:18:41 +0800545
Sieu Mun Tang28af1652022-05-09 10:48:53 +0800546 if (!is_address_in_ddr_range((uint64_t)args, sizeof(uint32_t) * len)) {
Abdul Halim, Muhammad Hadi Asyrafic39a0e02020-02-06 19:18:41 +0800547 return INTEL_SIP_SMC_STATUS_REJECTED;
Sieu Mun Tang28af1652022-05-09 10:48:53 +0800548 }
Abdul Halim, Muhammad Hadi Asyrafic39a0e02020-02-06 19:18:41 +0800549
Hadi Asyrafia33e8102019-12-17 19:30:41 +0800550 int status = mailbox_send_cmd(MBOX_JOB_ID, cmd, args, len, urgent,
Sieu Mun Tang7420c532022-05-10 23:17:04 +0800551 (uint32_t *) response, &resp_len);
Hadi Asyrafia33e8102019-12-17 19:30:41 +0800552
553 if (status < 0) {
Hadi Asyrafia33e8102019-12-17 19:30:41 +0800554 *mbox_status = -status;
555 return INTEL_SIP_SMC_STATUS_ERROR;
556 }
557
558 *mbox_status = 0;
Sieu Mun Tang24682662022-02-19 21:49:48 +0800559 *len_in_resp = resp_len;
Sieu Mun Tang7420c532022-05-10 23:17:04 +0800560
561 flush_dcache_range(response, resp_len * MBOX_WORD_BYTE);
562
Hadi Asyrafia33e8102019-12-17 19:30:41 +0800563 return INTEL_SIP_SMC_STATUS_OK;
564}
565
Sieu Mun Tang2b8e0052022-04-27 18:57:29 +0800566static int intel_smc_get_usercode(uint32_t *user_code)
567{
568 int status;
569 unsigned int resp_len = sizeof(user_code) / MBOX_WORD_BYTE;
570
571 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_GET_USERCODE, NULL,
572 0U, CMD_CASUAL, user_code, &resp_len);
573
574 if (status < 0) {
575 return INTEL_SIP_SMC_STATUS_ERROR;
576 }
577
578 return INTEL_SIP_SMC_STATUS_OK;
579}
580
Sieu Mun Tangfd8a8ad2022-05-07 00:50:37 +0800581uint32_t intel_smc_service_completed(uint64_t addr, uint32_t size,
582 uint32_t mode, uint32_t *job_id,
583 uint32_t *ret_size, uint32_t *mbox_error)
584{
585 int status = 0;
586 uint32_t resp_len = size / MBOX_WORD_BYTE;
587
588 if (resp_len > MBOX_DATA_MAX_LEN) {
589 return INTEL_SIP_SMC_STATUS_REJECTED;
590 }
591
592 if (!is_address_in_ddr_range(addr, size)) {
593 return INTEL_SIP_SMC_STATUS_REJECTED;
594 }
595
596 if (mode == SERVICE_COMPLETED_MODE_ASYNC) {
597 status = mailbox_read_response_async(job_id,
598 NULL, (uint32_t *) addr, &resp_len, 0);
599 } else {
600 status = mailbox_read_response(job_id,
601 (uint32_t *) addr, &resp_len);
602
603 if (status == MBOX_NO_RESPONSE) {
604 status = MBOX_BUSY;
605 }
606 }
607
608 if (status == MBOX_NO_RESPONSE) {
609 return INTEL_SIP_SMC_STATUS_NO_RESPONSE;
610 }
611
612 if (status == MBOX_BUSY) {
613 return INTEL_SIP_SMC_STATUS_BUSY;
614 }
615
616 *ret_size = resp_len * MBOX_WORD_BYTE;
617 flush_dcache_range(addr, *ret_size);
618
Sieu Mun Tang6c7f0c72022-12-04 01:43:35 +0800619 if (status == MBOX_RET_SDOS_DECRYPTION_ERROR_102 ||
620 status == MBOX_RET_SDOS_DECRYPTION_ERROR_103) {
621 *mbox_error = -status;
622 } else if (status != MBOX_RET_OK) {
Sieu Mun Tangfd8a8ad2022-05-07 00:50:37 +0800623 *mbox_error = -status;
624 return INTEL_SIP_SMC_STATUS_ERROR;
625 }
626
627 return INTEL_SIP_SMC_STATUS_OK;
628}
629
Sieu Mun Tang758a2ad2022-05-11 10:23:13 +0800630/* Miscellaneous HPS services */
631uint32_t intel_hps_set_bridges(uint64_t enable, uint64_t mask)
632{
633 int status = 0;
634
Sieu Mun Tang044ed482022-05-11 10:45:19 +0800635 if ((enable & SOCFPGA_BRIDGE_ENABLE) != 0U) {
636 if ((enable & SOCFPGA_BRIDGE_HAS_MASK) != 0U) {
Sieu Mun Tang758a2ad2022-05-11 10:23:13 +0800637 status = socfpga_bridges_enable((uint32_t)mask);
638 } else {
639 status = socfpga_bridges_enable(~0);
640 }
641 } else {
Sieu Mun Tang044ed482022-05-11 10:45:19 +0800642 if ((enable & SOCFPGA_BRIDGE_HAS_MASK) != 0U) {
Sieu Mun Tang758a2ad2022-05-11 10:23:13 +0800643 status = socfpga_bridges_disable((uint32_t)mask);
644 } else {
645 status = socfpga_bridges_disable(~0);
646 }
647 }
648
649 if (status < 0) {
650 return INTEL_SIP_SMC_STATUS_ERROR;
651 }
652
653 return INTEL_SIP_SMC_STATUS_OK;
654}
655
Jit Loon Lim2bee1732023-05-17 12:26:11 +0800656/* SDM SEU Error services */
657static uint32_t intel_sdm_seu_err_read(uint64_t *respbuf, unsigned int respbuf_sz)
658{
659 if (mailbox_seu_err_status((uint32_t *)respbuf, respbuf_sz) < 0) {
660 return INTEL_SIP_SMC_SEU_ERR_READ_ERROR;
661 }
662
663 return INTEL_SIP_SMC_STATUS_OK;
664}
665
Hadi Asyrafi616da772019-06-27 11:34:03 +0800666/*
667 * This function is responsible for handling all SiP calls from the NS world
668 */
669
Sieu Mun Tang044ed482022-05-11 10:45:19 +0800670uintptr_t sip_smc_handler_v1(uint32_t smc_fid,
Hadi Asyrafi616da772019-06-27 11:34:03 +0800671 u_register_t x1,
672 u_register_t x2,
673 u_register_t x3,
674 u_register_t x4,
675 void *cookie,
676 void *handle,
677 u_register_t flags)
678{
Sieu Mun Tang2a820b92022-05-11 09:59:55 +0800679 uint32_t retval = 0, completed_addr[3];
680 uint32_t retval2 = 0;
Sieu Mun Tanga34b8812022-03-17 03:11:55 +0800681 uint32_t mbox_error = 0;
Jit Loon Lim2bee1732023-05-17 12:26:11 +0800682 uint64_t retval64, rsu_respbuf[9], seu_respbuf[3];
Sieu Mun Tang9f22cbf2022-03-02 11:04:09 +0800683 int status = INTEL_SIP_SMC_STATUS_OK;
Sieu Mun Tang24682662022-02-19 21:49:48 +0800684 int mbox_status;
685 unsigned int len_in_resp;
Sieu Mun Tang583149a2022-05-10 17:27:12 +0800686 u_register_t x5, x6, x7;
Abdul Halim, Muhammad Hadi Asyrafib45f15e2020-05-14 15:32:43 +0800687
Hadi Asyrafi616da772019-06-27 11:34:03 +0800688 switch (smc_fid) {
689 case SIP_SVC_UID:
690 /* Return UID to the caller */
691 SMC_UUID_RET(handle, intl_svc_uid);
Hadi Asyrafi67942302019-10-22 13:28:51 +0800692
Hadi Asyrafi616da772019-06-27 11:34:03 +0800693 case INTEL_SIP_SMC_FPGA_CONFIG_ISDONE:
Sieu Mun Tangc3667602022-05-13 14:55:05 +0800694 status = intel_mailbox_fpga_config_isdone();
Hadi Asyrafi616da772019-06-27 11:34:03 +0800695 SMC_RET4(handle, status, 0, 0, 0);
Hadi Asyrafi67942302019-10-22 13:28:51 +0800696
Hadi Asyrafi616da772019-06-27 11:34:03 +0800697 case INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM:
698 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK,
699 INTEL_SIP_SMC_FPGA_CONFIG_ADDR,
700 INTEL_SIP_SMC_FPGA_CONFIG_SIZE -
701 INTEL_SIP_SMC_FPGA_CONFIG_ADDR);
Hadi Asyrafi67942302019-10-22 13:28:51 +0800702
Hadi Asyrafi616da772019-06-27 11:34:03 +0800703 case INTEL_SIP_SMC_FPGA_CONFIG_START:
704 status = intel_fpga_config_start(x1);
705 SMC_RET4(handle, status, 0, 0, 0);
Hadi Asyrafi67942302019-10-22 13:28:51 +0800706
Hadi Asyrafi616da772019-06-27 11:34:03 +0800707 case INTEL_SIP_SMC_FPGA_CONFIG_WRITE:
708 status = intel_fpga_config_write(x1, x2);
709 SMC_RET4(handle, status, 0, 0, 0);
Hadi Asyrafi67942302019-10-22 13:28:51 +0800710
Hadi Asyrafi616da772019-06-27 11:34:03 +0800711 case INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE:
712 status = intel_fpga_config_completed_write(completed_addr,
Abdul Halim, Muhammad Hadi Asyrafi20a07f32020-05-18 11:16:48 +0800713 &retval, &rcv_id);
714 switch (retval) {
Hadi Asyrafi616da772019-06-27 11:34:03 +0800715 case 1:
716 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK,
717 completed_addr[0], 0, 0);
Hadi Asyrafi67942302019-10-22 13:28:51 +0800718
Hadi Asyrafi616da772019-06-27 11:34:03 +0800719 case 2:
720 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK,
721 completed_addr[0],
722 completed_addr[1], 0);
Hadi Asyrafi67942302019-10-22 13:28:51 +0800723
Hadi Asyrafi616da772019-06-27 11:34:03 +0800724 case 3:
725 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK,
726 completed_addr[0],
727 completed_addr[1],
728 completed_addr[2]);
Hadi Asyrafi67942302019-10-22 13:28:51 +0800729
Hadi Asyrafi616da772019-06-27 11:34:03 +0800730 case 0:
731 SMC_RET4(handle, status, 0, 0, 0);
Hadi Asyrafi67942302019-10-22 13:28:51 +0800732
Hadi Asyrafi616da772019-06-27 11:34:03 +0800733 default:
Tien Hock, Loh500b2322019-10-30 14:49:40 +0800734 mailbox_clear_response();
Hadi Asyrafi616da772019-06-27 11:34:03 +0800735 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR);
736 }
Hadi Asyrafi67942302019-10-22 13:28:51 +0800737
738 case INTEL_SIP_SMC_REG_READ:
Abdul Halim, Muhammad Hadi Asyrafi20a07f32020-05-18 11:16:48 +0800739 status = intel_secure_reg_read(x1, &retval);
740 SMC_RET3(handle, status, retval, x1);
Hadi Asyrafi67942302019-10-22 13:28:51 +0800741
742 case INTEL_SIP_SMC_REG_WRITE:
Abdul Halim, Muhammad Hadi Asyrafi20a07f32020-05-18 11:16:48 +0800743 status = intel_secure_reg_write(x1, (uint32_t)x2, &retval);
744 SMC_RET3(handle, status, retval, x1);
Hadi Asyrafi67942302019-10-22 13:28:51 +0800745
746 case INTEL_SIP_SMC_REG_UPDATE:
747 status = intel_secure_reg_update(x1, (uint32_t)x2,
Abdul Halim, Muhammad Hadi Asyrafi20a07f32020-05-18 11:16:48 +0800748 (uint32_t)x3, &retval);
749 SMC_RET3(handle, status, retval, x1);
Hadi Asyrafi616da772019-06-27 11:34:03 +0800750
Hadi Asyrafi593c4c52019-12-17 19:22:17 +0800751 case INTEL_SIP_SMC_RSU_STATUS:
752 status = intel_rsu_status(rsu_respbuf,
753 ARRAY_SIZE(rsu_respbuf));
754 if (status) {
755 SMC_RET1(handle, status);
756 } else {
757 SMC_RET4(handle, rsu_respbuf[0], rsu_respbuf[1],
758 rsu_respbuf[2], rsu_respbuf[3]);
759 }
760
761 case INTEL_SIP_SMC_RSU_UPDATE:
762 status = intel_rsu_update(x1);
763 SMC_RET1(handle, status);
764
765 case INTEL_SIP_SMC_RSU_NOTIFY:
766 status = intel_rsu_notify(x1);
767 SMC_RET1(handle, status);
768
769 case INTEL_SIP_SMC_RSU_RETRY_COUNTER:
770 status = intel_rsu_retry_counter((uint32_t *)rsu_respbuf,
Abdul Halim, Muhammad Hadi Asyrafi20a07f32020-05-18 11:16:48 +0800771 ARRAY_SIZE(rsu_respbuf), &retval);
Hadi Asyrafi593c4c52019-12-17 19:22:17 +0800772 if (status) {
773 SMC_RET1(handle, status);
774 } else {
Abdul Halim, Muhammad Hadi Asyrafi20a07f32020-05-18 11:16:48 +0800775 SMC_RET2(handle, status, retval);
Hadi Asyrafi593c4c52019-12-17 19:22:17 +0800776 }
777
Chee Hong Ang2cfd8ec2020-05-13 11:44:04 +0800778 case INTEL_SIP_SMC_RSU_DCMF_VERSION:
779 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK,
780 ((uint64_t)rsu_dcmf_ver[1] << 32) | rsu_dcmf_ver[0],
781 ((uint64_t)rsu_dcmf_ver[3] << 32) | rsu_dcmf_ver[2]);
782
783 case INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION:
784 status = intel_rsu_copy_dcmf_version(x1, x2);
785 SMC_RET1(handle, status);
786
Sieu Mun Tange6d5de92022-04-28 22:21:01 +0800787 case INTEL_SIP_SMC_RSU_DCMF_STATUS:
788 SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK,
789 ((uint64_t)rsu_dcmf_stat[3] << 48) |
790 ((uint64_t)rsu_dcmf_stat[2] << 32) |
791 ((uint64_t)rsu_dcmf_stat[1] << 16) |
792 rsu_dcmf_stat[0]);
793
794 case INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS:
795 status = intel_rsu_copy_dcmf_status(x1);
796 SMC_RET1(handle, status);
797
Chee Hong Ang681631b2020-07-01 14:22:25 +0800798 case INTEL_SIP_SMC_RSU_MAX_RETRY:
799 SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK, rsu_max_retry);
800
801 case INTEL_SIP_SMC_RSU_COPY_MAX_RETRY:
802 rsu_max_retry = x1;
803 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_OK);
804
Sieu Mun Tangdbcc2cf2022-03-07 12:13:04 +0800805 case INTEL_SIP_SMC_ECC_DBE:
806 status = intel_ecc_dbe_notification(x1);
807 SMC_RET1(handle, status);
808
Sieu Mun Tang758a2ad2022-05-11 10:23:13 +0800809 case INTEL_SIP_SMC_SERVICE_COMPLETED:
810 status = intel_smc_service_completed(x1, x2, x3, &rcv_id,
811 &len_in_resp, &mbox_error);
812 SMC_RET4(handle, status, mbox_error, x1, len_in_resp);
813
Abdul Halim, Muhammad Hadi Asyrafid9006fc2021-02-05 11:50:58 +0800814 case INTEL_SIP_SMC_FIRMWARE_VERSION:
815 status = intel_smc_fw_version(&retval);
Sieu Mun Tangbfda95a2022-04-27 18:54:10 +0800816 SMC_RET2(handle, status, retval);
Abdul Halim, Muhammad Hadi Asyrafid9006fc2021-02-05 11:50:58 +0800817
Hadi Asyrafia33e8102019-12-17 19:30:41 +0800818 case INTEL_SIP_SMC_MBOX_SEND_CMD:
819 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
820 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
Sieu Mun Tang7420c532022-05-10 23:17:04 +0800821 status = intel_mbox_send_cmd(x1, (uint32_t *)x2, x3, x4, x5, x6,
822 &mbox_status, &len_in_resp);
Sieu Mun Tangf02f0cb2022-02-19 20:36:41 +0800823 SMC_RET3(handle, status, mbox_status, len_in_resp);
Hadi Asyrafia33e8102019-12-17 19:30:41 +0800824
Sieu Mun Tang2b8e0052022-04-27 18:57:29 +0800825 case INTEL_SIP_SMC_GET_USERCODE:
826 status = intel_smc_get_usercode(&retval);
827 SMC_RET2(handle, status, retval);
828
Sieu Mun Tang128d2a72022-05-11 09:49:25 +0800829 case INTEL_SIP_SMC_FCS_CRYPTION:
830 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
831
832 if (x1 == FCS_MODE_DECRYPT) {
833 status = intel_fcs_decryption(x2, x3, x4, x5, &send_id);
834 } else if (x1 == FCS_MODE_ENCRYPT) {
835 status = intel_fcs_encryption(x2, x3, x4, x5, &send_id);
836 } else {
837 status = INTEL_SIP_SMC_STATUS_REJECTED;
838 }
839
840 SMC_RET3(handle, status, x4, x5);
841
Sieu Mun Tang22322fb2022-05-09 16:05:58 +0800842 case INTEL_SIP_SMC_FCS_CRYPTION_EXT:
843 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
844 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
845 x7 = SMC_GET_GP(handle, CTX_GPREG_X7);
846
847 if (x3 == FCS_MODE_DECRYPT) {
848 status = intel_fcs_decryption_ext(x1, x2, x4, x5, x6,
849 (uint32_t *) &x7, &mbox_error);
850 } else if (x3 == FCS_MODE_ENCRYPT) {
851 status = intel_fcs_encryption_ext(x1, x2, x4, x5, x6,
852 (uint32_t *) &x7, &mbox_error);
853 } else {
854 status = INTEL_SIP_SMC_STATUS_REJECTED;
855 }
856
857 SMC_RET4(handle, status, mbox_error, x6, x7);
858
Sieu Mun Tangfd8a8ad2022-05-07 00:50:37 +0800859 case INTEL_SIP_SMC_FCS_RANDOM_NUMBER:
860 status = intel_fcs_random_number_gen(x1, &retval64,
861 &mbox_error);
862 SMC_RET4(handle, status, mbox_error, x1, retval64);
863
Sieu Mun Tange7a037f2022-05-10 17:18:19 +0800864 case INTEL_SIP_SMC_FCS_RANDOM_NUMBER_EXT:
865 status = intel_fcs_random_number_gen_ext(x1, x2, x3,
866 &send_id);
867 SMC_RET1(handle, status);
868
Sieu Mun Tangfd8a8ad2022-05-07 00:50:37 +0800869 case INTEL_SIP_SMC_FCS_SEND_CERTIFICATE:
870 status = intel_fcs_send_cert(x1, x2, &send_id);
871 SMC_RET1(handle, status);
872
873 case INTEL_SIP_SMC_FCS_GET_PROVISION_DATA:
874 status = intel_fcs_get_provision_data(&send_id);
875 SMC_RET1(handle, status);
876
Sieu Mun Tanga068fdf2022-05-11 10:01:54 +0800877 case INTEL_SIP_SMC_FCS_CNTR_SET_PREAUTH:
878 status = intel_fcs_cntr_set_preauth(x1, x2, x3,
879 &mbox_error);
880 SMC_RET2(handle, status, mbox_error);
881
Sieu Mun Tang82cf5df2022-05-05 17:07:21 +0800882 case INTEL_SIP_SMC_HPS_SET_BRIDGES:
883 status = intel_hps_set_bridges(x1, x2);
884 SMC_RET1(handle, status);
885
Sieu Mun Tang044ed482022-05-11 10:45:19 +0800886 case INTEL_SIP_SMC_HWMON_READTEMP:
887 status = intel_hwmon_readtemp(x1, &retval);
888 SMC_RET2(handle, status, retval);
889
890 case INTEL_SIP_SMC_HWMON_READVOLT:
891 status = intel_hwmon_readvolt(x1, &retval);
892 SMC_RET2(handle, status, retval);
893
Sieu Mun Tang2a820b92022-05-11 09:59:55 +0800894 case INTEL_SIP_SMC_FCS_PSGSIGMA_TEARDOWN:
895 status = intel_fcs_sigma_teardown(x1, &mbox_error);
896 SMC_RET2(handle, status, mbox_error);
897
898 case INTEL_SIP_SMC_FCS_CHIP_ID:
899 status = intel_fcs_chip_id(&retval, &retval2, &mbox_error);
900 SMC_RET4(handle, status, mbox_error, retval, retval2);
901
902 case INTEL_SIP_SMC_FCS_ATTESTATION_SUBKEY:
903 status = intel_fcs_attestation_subkey(x1, x2, x3,
904 (uint32_t *) &x4, &mbox_error);
905 SMC_RET4(handle, status, mbox_error, x3, x4);
906
907 case INTEL_SIP_SMC_FCS_ATTESTATION_MEASUREMENTS:
908 status = intel_fcs_get_measurement(x1, x2, x3,
909 (uint32_t *) &x4, &mbox_error);
910 SMC_RET4(handle, status, mbox_error, x3, x4);
911
Sieu Mun Tang28af1652022-05-09 10:48:53 +0800912 case INTEL_SIP_SMC_FCS_GET_ATTESTATION_CERT:
913 status = intel_fcs_get_attestation_cert(x1, x2,
914 (uint32_t *) &x3, &mbox_error);
915 SMC_RET4(handle, status, mbox_error, x2, x3);
916
917 case INTEL_SIP_SMC_FCS_CREATE_CERT_ON_RELOAD:
918 status = intel_fcs_create_cert_on_reload(x1, &mbox_error);
919 SMC_RET2(handle, status, mbox_error);
920
Sieu Mun Tang16754e12022-05-09 12:08:42 +0800921 case INTEL_SIP_SMC_FCS_OPEN_CS_SESSION:
922 status = intel_fcs_open_crypto_service_session(&retval, &mbox_error);
923 SMC_RET3(handle, status, mbox_error, retval);
924
925 case INTEL_SIP_SMC_FCS_CLOSE_CS_SESSION:
926 status = intel_fcs_close_crypto_service_session(x1, &mbox_error);
927 SMC_RET2(handle, status, mbox_error);
928
Sieu Mun Tangfb1f6e92022-05-09 14:16:14 +0800929 case INTEL_SIP_SMC_FCS_IMPORT_CS_KEY:
930 status = intel_fcs_import_crypto_service_key(x1, x2, &send_id);
931 SMC_RET1(handle, status);
932
933 case INTEL_SIP_SMC_FCS_EXPORT_CS_KEY:
934 status = intel_fcs_export_crypto_service_key(x1, x2, x3,
935 (uint32_t *) &x4, &mbox_error);
936 SMC_RET4(handle, status, mbox_error, x3, x4);
937
938 case INTEL_SIP_SMC_FCS_REMOVE_CS_KEY:
939 status = intel_fcs_remove_crypto_service_key(x1, x2,
940 &mbox_error);
941 SMC_RET2(handle, status, mbox_error);
942
943 case INTEL_SIP_SMC_FCS_GET_CS_KEY_INFO:
944 status = intel_fcs_get_crypto_service_key_info(x1, x2, x3,
945 (uint32_t *) &x4, &mbox_error);
946 SMC_RET4(handle, status, mbox_error, x3, x4);
947
Sieu Mun Tangd907cc32022-05-10 17:24:05 +0800948 case INTEL_SIP_SMC_FCS_GET_DIGEST_INIT:
949 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
950 status = intel_fcs_get_digest_init(x1, x2, x3,
951 x4, x5, &mbox_error);
952 SMC_RET2(handle, status, mbox_error);
953
Sieu Mun Tang527df9f2022-04-28 16:28:48 +0800954 case INTEL_SIP_SMC_FCS_GET_DIGEST_UPDATE:
955 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
956 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
957 status = intel_fcs_get_digest_update_finalize(x1, x2, x3,
958 x4, x5, (uint32_t *) &x6, false,
959 &mbox_error);
960 SMC_RET4(handle, status, mbox_error, x5, x6);
961
Sieu Mun Tangd907cc32022-05-10 17:24:05 +0800962 case INTEL_SIP_SMC_FCS_GET_DIGEST_FINALIZE:
963 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
964 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
Sieu Mun Tang527df9f2022-04-28 16:28:48 +0800965 status = intel_fcs_get_digest_update_finalize(x1, x2, x3,
966 x4, x5, (uint32_t *) &x6, true,
967 &mbox_error);
Sieu Mun Tangd907cc32022-05-10 17:24:05 +0800968 SMC_RET4(handle, status, mbox_error, x5, x6);
969
Sieu Mun Tangbd8da632022-09-28 15:58:28 +0800970 case INTEL_SIP_SMC_FCS_GET_DIGEST_SMMU_UPDATE:
971 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
972 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
973 status = intel_fcs_get_digest_smmu_update_finalize(x1, x2, x3,
974 x4, x5, (uint32_t *) &x6, false,
975 &mbox_error, &send_id);
976 SMC_RET4(handle, status, mbox_error, x5, x6);
977
978 case INTEL_SIP_SMC_FCS_GET_DIGEST_SMMU_FINALIZE:
979 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
980 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
981 status = intel_fcs_get_digest_smmu_update_finalize(x1, x2, x3,
982 x4, x5, (uint32_t *) &x6, true,
983 &mbox_error, &send_id);
984 SMC_RET4(handle, status, mbox_error, x5, x6);
985
Sieu Mun Tang583149a2022-05-10 17:27:12 +0800986 case INTEL_SIP_SMC_FCS_MAC_VERIFY_INIT:
987 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
988 status = intel_fcs_mac_verify_init(x1, x2, x3,
989 x4, x5, &mbox_error);
990 SMC_RET2(handle, status, mbox_error);
991
Sieu Mun Tang527df9f2022-04-28 16:28:48 +0800992 case INTEL_SIP_SMC_FCS_MAC_VERIFY_UPDATE:
993 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
994 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
995 x7 = SMC_GET_GP(handle, CTX_GPREG_X7);
996 status = intel_fcs_mac_verify_update_finalize(x1, x2, x3,
997 x4, x5, (uint32_t *) &x6, x7,
998 false, &mbox_error);
999 SMC_RET4(handle, status, mbox_error, x5, x6);
1000
Sieu Mun Tang583149a2022-05-10 17:27:12 +08001001 case INTEL_SIP_SMC_FCS_MAC_VERIFY_FINALIZE:
1002 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1003 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1004 x7 = SMC_GET_GP(handle, CTX_GPREG_X7);
Sieu Mun Tang527df9f2022-04-28 16:28:48 +08001005 status = intel_fcs_mac_verify_update_finalize(x1, x2, x3,
1006 x4, x5, (uint32_t *) &x6, x7,
1007 true, &mbox_error);
Sieu Mun Tang583149a2022-05-10 17:27:12 +08001008 SMC_RET4(handle, status, mbox_error, x5, x6);
1009
Sieu Mun Tangbd8da632022-09-28 15:58:28 +08001010 case INTEL_SIP_SMC_FCS_MAC_VERIFY_SMMU_UPDATE:
1011 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1012 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1013 x7 = SMC_GET_GP(handle, CTX_GPREG_X7);
1014 status = intel_fcs_mac_verify_smmu_update_finalize(x1, x2, x3,
1015 x4, x5, (uint32_t *) &x6, x7,
1016 false, &mbox_error, &send_id);
1017 SMC_RET4(handle, status, mbox_error, x5, x6);
1018
1019 case INTEL_SIP_SMC_FCS_MAC_VERIFY_SMMU_FINALIZE:
1020 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1021 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1022 x7 = SMC_GET_GP(handle, CTX_GPREG_X7);
1023 status = intel_fcs_mac_verify_smmu_update_finalize(x1, x2, x3,
1024 x4, x5, (uint32_t *) &x6, x7,
1025 true, &mbox_error, &send_id);
1026 SMC_RET4(handle, status, mbox_error, x5, x6);
1027
Sieu Mun Tang153ecfb2022-05-10 17:39:26 +08001028 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_INIT:
1029 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1030 status = intel_fcs_ecdsa_sha2_data_sign_init(x1, x2, x3,
1031 x4, x5, &mbox_error);
1032 SMC_RET2(handle, status, mbox_error);
1033
Sieu Mun Tange77d37d2022-04-28 16:23:20 +08001034 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_UPDATE:
1035 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1036 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1037 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(x1, x2,
1038 x3, x4, x5, (uint32_t *) &x6, false,
1039 &mbox_error);
1040 SMC_RET4(handle, status, mbox_error, x5, x6);
1041
Sieu Mun Tang153ecfb2022-05-10 17:39:26 +08001042 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE:
1043 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1044 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
Sieu Mun Tange77d37d2022-04-28 16:23:20 +08001045 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(x1, x2,
1046 x3, x4, x5, (uint32_t *) &x6, true,
1047 &mbox_error);
Sieu Mun Tang153ecfb2022-05-10 17:39:26 +08001048 SMC_RET4(handle, status, mbox_error, x5, x6);
1049
Sieu Mun Tangbd8da632022-09-28 15:58:28 +08001050 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_UPDATE:
1051 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1052 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1053 status = intel_fcs_ecdsa_sha2_data_sign_smmu_update_finalize(x1,
1054 x2, x3, x4, x5, (uint32_t *) &x6, false,
1055 &mbox_error, &send_id);
1056 SMC_RET4(handle, status, mbox_error, x5, x6);
1057
1058 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_FINALIZE:
1059 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1060 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1061 status = intel_fcs_ecdsa_sha2_data_sign_smmu_update_finalize(x1,
1062 x2, x3, x4, x5, (uint32_t *) &x6, true,
1063 &mbox_error, &send_id);
1064 SMC_RET4(handle, status, mbox_error, x5, x6);
1065
Sieu Mun Tang8aa05ad2022-05-10 17:50:30 +08001066 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_INIT:
1067 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1068 status = intel_fcs_ecdsa_hash_sign_init(x1, x2, x3,
1069 x4, x5, &mbox_error);
1070 SMC_RET2(handle, status, mbox_error);
1071
1072 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_FINALIZE:
1073 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1074 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1075 status = intel_fcs_ecdsa_hash_sign_finalize(x1, x2, x3,
1076 x4, x5, (uint32_t *) &x6, &mbox_error);
1077 SMC_RET4(handle, status, mbox_error, x5, x6);
1078
Sieu Mun Tang59357e82022-05-10 17:53:32 +08001079 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_INIT:
1080 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1081 status = intel_fcs_ecdsa_hash_sig_verify_init(x1, x2, x3,
1082 x4, x5, &mbox_error);
1083 SMC_RET2(handle, status, mbox_error);
1084
1085 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_FINALIZE:
1086 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1087 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1088 status = intel_fcs_ecdsa_hash_sig_verify_finalize(x1, x2, x3,
1089 x4, x5, (uint32_t *) &x6, &mbox_error);
1090 SMC_RET4(handle, status, mbox_error, x5, x6);
1091
Sieu Mun Tangdcaab772022-05-11 10:16:40 +08001092 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_INIT:
1093 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1094 status = intel_fcs_ecdsa_sha2_data_sig_verify_init(x1, x2, x3,
1095 x4, x5, &mbox_error);
1096 SMC_RET2(handle, status, mbox_error);
1097
Sieu Mun Tange77d37d2022-04-28 16:23:20 +08001098 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_UPDATE:
1099 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1100 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1101 x7 = SMC_GET_GP(handle, CTX_GPREG_X7);
1102 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize(
1103 x1, x2, x3, x4, x5, (uint32_t *) &x6,
1104 x7, false, &mbox_error);
1105 SMC_RET4(handle, status, mbox_error, x5, x6);
1106
Sieu Mun Tangbd8da632022-09-28 15:58:28 +08001107 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_UPDATE:
1108 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1109 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1110 x7 = SMC_GET_GP(handle, CTX_GPREG_X7);
1111 status = intel_fcs_ecdsa_sha2_data_sig_verify_smmu_update_finalize(
1112 x1, x2, x3, x4, x5, (uint32_t *) &x6,
1113 x7, false, &mbox_error, &send_id);
1114 SMC_RET4(handle, status, mbox_error, x5, x6);
1115
1116 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_FINALIZE:
1117 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1118 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1119 x7 = SMC_GET_GP(handle, CTX_GPREG_X7);
1120 status = intel_fcs_ecdsa_sha2_data_sig_verify_smmu_update_finalize(
1121 x1, x2, x3, x4, x5, (uint32_t *) &x6,
1122 x7, true, &mbox_error, &send_id);
1123 SMC_RET4(handle, status, mbox_error, x5, x6);
1124
Sieu Mun Tangdcaab772022-05-11 10:16:40 +08001125 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE:
1126 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1127 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1128 x7 = SMC_GET_GP(handle, CTX_GPREG_X7);
Sieu Mun Tange77d37d2022-04-28 16:23:20 +08001129 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize(
1130 x1, x2, x3, x4, x5, (uint32_t *) &x6,
1131 x7, true, &mbox_error);
Sieu Mun Tangdcaab772022-05-11 10:16:40 +08001132 SMC_RET4(handle, status, mbox_error, x5, x6);
Sieu Mun Tang153ecfb2022-05-10 17:39:26 +08001133
Sieu Mun Tange2f3ede2022-05-10 17:36:32 +08001134 case INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_INIT:
1135 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1136 status = intel_fcs_ecdsa_get_pubkey_init(x1, x2, x3,
1137 x4, x5, &mbox_error);
1138 SMC_RET2(handle, status, mbox_error);
1139
1140 case INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_FINALIZE:
1141 status = intel_fcs_ecdsa_get_pubkey_finalize(x1, x2, x3,
1142 (uint32_t *) &x4, &mbox_error);
1143 SMC_RET4(handle, status, mbox_error, x3, x4);
1144
Sieu Mun Tang0675c222022-05-10 17:48:11 +08001145 case INTEL_SIP_SMC_FCS_ECDH_REQUEST_INIT:
1146 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1147 status = intel_fcs_ecdh_request_init(x1, x2, x3,
1148 x4, x5, &mbox_error);
1149 SMC_RET2(handle, status, mbox_error);
1150
1151 case INTEL_SIP_SMC_FCS_ECDH_REQUEST_FINALIZE:
1152 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1153 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1154 status = intel_fcs_ecdh_request_finalize(x1, x2, x3,
1155 x4, x5, (uint32_t *) &x6, &mbox_error);
1156 SMC_RET4(handle, status, mbox_error, x5, x6);
1157
Sieu Mun Tangb0c1d112022-05-10 17:30:00 +08001158 case INTEL_SIP_SMC_FCS_AES_CRYPT_INIT:
1159 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1160 status = intel_fcs_aes_crypt_init(x1, x2, x3, x4, x5,
1161 &mbox_error);
1162 SMC_RET2(handle, status, mbox_error);
1163
Sieu Mun Tang9bea8152022-04-28 16:15:54 +08001164 case INTEL_SIP_SMC_FCS_AES_CRYPT_UPDATE:
1165 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1166 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1167 status = intel_fcs_aes_crypt_update_finalize(x1, x2, x3, x4,
1168 x5, x6, false, &send_id);
1169 SMC_RET1(handle, status);
1170
Sieu Mun Tangb0c1d112022-05-10 17:30:00 +08001171 case INTEL_SIP_SMC_FCS_AES_CRYPT_FINALIZE:
1172 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1173 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
Sieu Mun Tang9bea8152022-04-28 16:15:54 +08001174 status = intel_fcs_aes_crypt_update_finalize(x1, x2, x3, x4,
1175 x5, x6, true, &send_id);
Sieu Mun Tangb0c1d112022-05-10 17:30:00 +08001176 SMC_RET1(handle, status);
1177
Sieu Mun Tanga34b8812022-03-17 03:11:55 +08001178 case INTEL_SIP_SMC_GET_ROM_PATCH_SHA384:
1179 status = intel_fcs_get_rom_patch_sha384(x1, &retval64,
1180 &mbox_error);
1181 SMC_RET4(handle, status, mbox_error, x1, retval64);
1182
Sieu Mun Tangf9cb6572022-04-27 18:24:06 +08001183 case INTEL_SIP_SMC_SVC_VERSION:
1184 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK,
1185 SIP_SVC_VERSION_MAJOR,
1186 SIP_SVC_VERSION_MINOR);
1187
Jit Loon Lim2bee1732023-05-17 12:26:11 +08001188 case INTEL_SIP_SMC_SEU_ERR_STATUS:
1189 status = intel_sdm_seu_err_read(seu_respbuf,
1190 ARRAY_SIZE(seu_respbuf));
1191 if (status) {
1192 SMC_RET1(handle, status);
1193 } else {
1194 SMC_RET3(handle, seu_respbuf[0], seu_respbuf[1], seu_respbuf[2]);
1195 }
1196
Hadi Asyrafi616da772019-06-27 11:34:03 +08001197 default:
1198 return socfpga_sip_handler(smc_fid, x1, x2, x3, x4,
1199 cookie, handle, flags);
1200 }
1201}
1202
Sieu Mun Tang044ed482022-05-11 10:45:19 +08001203uintptr_t sip_smc_handler(uint32_t smc_fid,
1204 u_register_t x1,
1205 u_register_t x2,
1206 u_register_t x3,
1207 u_register_t x4,
1208 void *cookie,
1209 void *handle,
1210 u_register_t flags)
1211{
1212 uint32_t cmd = smc_fid & INTEL_SIP_SMC_CMD_MASK;
1213
1214 if (cmd >= INTEL_SIP_SMC_CMD_V2_RANGE_BEGIN &&
1215 cmd <= INTEL_SIP_SMC_CMD_V2_RANGE_END) {
1216 return sip_smc_handler_v2(smc_fid, x1, x2, x3, x4,
1217 cookie, handle, flags);
1218 } else {
1219 return sip_smc_handler_v1(smc_fid, x1, x2, x3, x4,
1220 cookie, handle, flags);
1221 }
1222}
1223
Hadi Asyrafi616da772019-06-27 11:34:03 +08001224DECLARE_RT_SVC(
Hadi Asyrafi4d9f3952019-10-23 17:35:32 +08001225 socfpga_sip_svc,
Hadi Asyrafi616da772019-06-27 11:34:03 +08001226 OEN_SIP_START,
1227 OEN_SIP_END,
1228 SMC_TYPE_FAST,
1229 NULL,
1230 sip_smc_handler
1231);
1232
1233DECLARE_RT_SVC(
Hadi Asyrafi4d9f3952019-10-23 17:35:32 +08001234 socfpga_sip_svc_std,
Hadi Asyrafi616da772019-06-27 11:34:03 +08001235 OEN_SIP_START,
1236 OEN_SIP_END,
1237 SMC_TYPE_YIELD,
1238 NULL,
1239 sip_smc_handler
1240);