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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Dan Handleye83b0ca2014-01-14 18:17:09 +00002 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
Sandrine Bailleux3fa98472014-03-31 11:25:18 +010031#include <arch.h>
Vikram Kanigiri96377452014-04-24 11:02:16 +010032#include <arch_helpers.h>
Dan Handleyfb42b122014-06-20 09:43:15 +010033#include <arm_gic.h>
Vikram Kanigirida567432014-04-15 18:08:08 +010034#include <assert.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010035#include <bl_common.h>
36#include <bl31.h>
Vikram Kanigiri3ff77de2014-03-25 17:35:26 +000037#include <console.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010038#include <mmio.h>
39#include <platform.h>
40#include <stddef.h>
Dan Handley4d2e49d2014-04-11 11:52:12 +010041#include "drivers/pwrc/fvp_pwrc.h"
Dan Handleyed6ff952014-05-14 17:44:19 +010042#include "fvp_def.h"
43#include "fvp_private.h"
Achin Gupta4f6ad662013-10-25 09:08:21 +010044
45/*******************************************************************************
46 * Declarations of linker defined symbols which will help us find the layout
47 * of trusted SRAM
48 ******************************************************************************/
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000049extern unsigned long __RO_START__;
50extern unsigned long __RO_END__;
Achin Gupta4f6ad662013-10-25 09:08:21 +010051
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000052extern unsigned long __COHERENT_RAM_START__;
53extern unsigned long __COHERENT_RAM_END__;
Achin Gupta4f6ad662013-10-25 09:08:21 +010054
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000055/*
56 * The next 2 constants identify the extents of the code & RO data region.
57 * These addresses are used by the MMU setup code and therefore they must be
58 * page-aligned. It is the responsibility of the linker script to ensure that
59 * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses.
60 */
61#define BL31_RO_BASE (unsigned long)(&__RO_START__)
62#define BL31_RO_LIMIT (unsigned long)(&__RO_END__)
63
64/*
65 * The next 2 constants identify the extents of the coherent memory region.
66 * These addresses are used by the MMU setup code and therefore they must be
67 * page-aligned. It is the responsibility of the linker script to ensure that
68 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols
69 * refer to page-aligned addresses.
70 */
71#define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
72#define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
Achin Gupta4f6ad662013-10-25 09:08:21 +010073
Vikram Kanigiri96377452014-04-24 11:02:16 +010074
75#if RESET_TO_BL31
Vikram Kanigiri9d70f0f2014-07-15 16:46:43 +010076static entry_point_info_t bl32_image_ep_info;
77static entry_point_info_t bl33_image_ep_info;
Vikram Kanigiri96377452014-04-24 11:02:16 +010078#else
Achin Gupta4f6ad662013-10-25 09:08:21 +010079/*******************************************************************************
Achin Guptae4d084e2014-02-19 17:18:23 +000080 * Reference to structure which holds the arguments that have been passed to
81 * BL31 from BL2.
Achin Gupta4f6ad662013-10-25 09:08:21 +010082 ******************************************************************************/
Vikram Kanigirida567432014-04-15 18:08:08 +010083static bl31_params_t *bl2_to_bl31_params;
Vikram Kanigiri96377452014-04-24 11:02:16 +010084#endif
Achin Gupta35ca3512014-02-19 17:58:33 +000085
Achin Gupta4f6ad662013-10-25 09:08:21 +010086/*******************************************************************************
Vikram Kanigirida567432014-04-15 18:08:08 +010087 * Return a pointer to the 'entry_point_info' structure of the next image for the
Achin Gupta35ca3512014-02-19 17:58:33 +000088 * security state specified. BL33 corresponds to the non-secure image type
89 * while BL32 corresponds to the secure image type. A NULL pointer is returned
90 * if the image does not exist.
Achin Gupta4f6ad662013-10-25 09:08:21 +010091 ******************************************************************************/
Dan Handley701fea72014-05-27 16:17:21 +010092entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
Achin Gupta4f6ad662013-10-25 09:08:21 +010093{
Vikram Kanigiri96377452014-04-24 11:02:16 +010094#if RESET_TO_BL31
Juan Castillof558cac2014-06-05 09:45:36 +010095 assert(sec_state_is_valid(type));
Vikram Kanigiricf79bf52014-06-02 14:59:00 +010096
Vikram Kanigiri9d70f0f2014-07-15 16:46:43 +010097 if (type == NON_SECURE)
98 return &bl33_image_ep_info;
99 else
100 return &bl32_image_ep_info;
Vikram Kanigiri96377452014-04-24 11:02:16 +0100101#else
Vikram Kanigiricf79bf52014-06-02 14:59:00 +0100102 entry_point_info_t *next_image_info;
103
Juan Castillof558cac2014-06-05 09:45:36 +0100104 assert(sec_state_is_valid(type));
105
Vikram Kanigiri96377452014-04-24 11:02:16 +0100106 next_image_info = (type == NON_SECURE) ?
Vikram Kanigirida567432014-04-15 18:08:08 +0100107 bl2_to_bl31_params->bl33_ep_info :
108 bl2_to_bl31_params->bl32_ep_info;
Achin Gupta35ca3512014-02-19 17:58:33 +0000109
110 /* None of the images on this platform can have 0x0 as the entrypoint */
Vikram Kanigirida567432014-04-15 18:08:08 +0100111 if (next_image_info->pc)
Achin Gupta35ca3512014-02-19 17:58:33 +0000112 return next_image_info;
113 else
114 return NULL;
Vikram Kanigiricf79bf52014-06-02 14:59:00 +0100115#endif
Achin Gupta4f6ad662013-10-25 09:08:21 +0100116}
117
118/*******************************************************************************
Achin Guptae4d084e2014-02-19 17:18:23 +0000119 * Perform any BL31 specific platform actions. Here is an opportunity to copy
120 * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they
121 * are lost (potentially). This needs to be done before the MMU is initialized
122 * so that the memory layout can be used while creating page tables. On the FVP
123 * we know that BL2 has populated the parameters in secure DRAM. So we just use
124 * the reference passed in 'from_bl2' instead of copying. The 'data' parameter
125 * is not used since all the information is contained in 'from_bl2'. Also, BL2
126 * has flushed this information to memory, so we are guaranteed to pick up good
127 * data
Achin Gupta4f6ad662013-10-25 09:08:21 +0100128 ******************************************************************************/
Vikram Kanigirida567432014-04-15 18:08:08 +0100129void bl31_early_platform_setup(bl31_params_t *from_bl2,
Vikram Kanigirid8c9d262014-05-16 18:48:12 +0100130 void *plat_params_from_bl2)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100131{
Vikram Kanigiri3684abf2014-03-27 14:33:15 +0000132 /* Initialize the console to provide early debug support */
Soby Mathew69817f72014-07-14 15:43:21 +0100133 console_init(PL011_UART0_BASE, PL011_UART0_CLK_IN_HZ, PL011_BAUDRATE);
Vikram Kanigiri3684abf2014-03-27 14:33:15 +0000134
Achin Gupta4f6ad662013-10-25 09:08:21 +0100135 /* Initialize the platform config for future decision making */
Dan Handleyea451572014-05-15 14:53:30 +0100136 fvp_config_setup();
Vikram Kanigiri96377452014-04-24 11:02:16 +0100137
138#if RESET_TO_BL31
139 /* There are no parameters from BL2 if BL31 is a reset vector */
140 assert(from_bl2 == NULL);
141 assert(plat_params_from_bl2 == NULL);
142
Vikram Kanigiri96377452014-04-24 11:02:16 +0100143 /*
144 * Do initial security configuration to allow DRAM/device access. On
145 * Base FVP only DRAM security is programmable (via TrustZone), but
146 * other platforms might have more programmable security devices
147 * present.
148 */
Dan Handleyea451572014-05-15 14:53:30 +0100149 fvp_security_setup();
Vikram Kanigiri9d70f0f2014-07-15 16:46:43 +0100150
151 /* Populate entry point information for BL3-2 and BL3-3 */
152 SET_PARAM_HEAD(&bl32_image_ep_info,
153 PARAM_EP,
154 VERSION_1,
155 0);
156 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
157 bl32_image_ep_info.pc = BL32_BASE;
158 bl32_image_ep_info.spsr = fvp_get_spsr_for_bl32_entry();
159
160 SET_PARAM_HEAD(&bl33_image_ep_info,
161 PARAM_EP,
162 VERSION_1,
163 0);
164 /*
165 * Tell BL31 where the non-trusted software image
166 * is located and the entry state information
167 */
168 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
169 bl33_image_ep_info.spsr = fvp_get_spsr_for_bl33_entry();
170 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
171
Vikram Kanigiri96377452014-04-24 11:02:16 +0100172#else
173 /* Check params passed from BL2 should not be NULL,
174 * We are not checking plat_params_from_bl2 as NULL as we are not
175 * using it on FVP
176 */
177 assert(from_bl2 != NULL);
178 assert(from_bl2->h.type == PARAM_BL31);
179 assert(from_bl2->h.version >= VERSION_1);
180
181 bl2_to_bl31_params = from_bl2;
Andrew Thoelkea55566d2014-05-28 22:22:55 +0100182 assert(((unsigned long)plat_params_from_bl2) == FVP_BL31_PLAT_PARAM_VAL);
Vikram Kanigiri96377452014-04-24 11:02:16 +0100183#endif
Achin Gupta4f6ad662013-10-25 09:08:21 +0100184}
185
186/*******************************************************************************
187 * Initialize the gic, configure the CLCD and zero out variables needed by the
188 * secondaries to boot up correctly.
189 ******************************************************************************/
Juan Castillo2d552402014-06-13 17:05:10 +0100190void bl31_platform_setup(void)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100191{
192 unsigned int reg_val;
193
Ian Spray84687392014-01-02 16:57:12 +0000194 /* Initialize the gic cpu and distributor interfaces */
Dan Handleyfb42b122014-06-20 09:43:15 +0100195 fvp_gic_init();
196 arm_gic_setup();
Achin Gupta4f6ad662013-10-25 09:08:21 +0100197
198 /*
199 * TODO: Configure the CLCD before handing control to
200 * linux. Need to see if a separate driver is needed
201 * instead.
202 */
203 mmio_write_32(VE_SYSREGS_BASE + V2M_SYS_CFGDATA, 0);
204 mmio_write_32(VE_SYSREGS_BASE + V2M_SYS_CFGCTRL,
205 (1ull << 31) | (1 << 30) | (7 << 20) | (0 << 16));
206
Sandrine Bailleux3fa98472014-03-31 11:25:18 +0100207 /* Enable and initialize the System level generic timer */
208 mmio_write_32(SYS_CNTCTL_BASE + CNTCR_OFF, CNTCR_FCREQ(0) | CNTCR_EN);
209
Achin Gupta4f6ad662013-10-25 09:08:21 +0100210 /* Allow access to the System counter timer module */
211 reg_val = (1 << CNTACR_RPCT_SHIFT) | (1 << CNTACR_RVCT_SHIFT);
212 reg_val |= (1 << CNTACR_RFRQ_SHIFT) | (1 << CNTACR_RVOFF_SHIFT);
213 reg_val |= (1 << CNTACR_RWVT_SHIFT) | (1 << CNTACR_RWPT_SHIFT);
214 mmio_write_32(SYS_TIMCTL_BASE + CNTACR_BASE(0), reg_val);
215 mmio_write_32(SYS_TIMCTL_BASE + CNTACR_BASE(1), reg_val);
216
217 reg_val = (1 << CNTNSAR_NS_SHIFT(0)) | (1 << CNTNSAR_NS_SHIFT(1));
218 mmio_write_32(SYS_TIMCTL_BASE + CNTNSAR, reg_val);
219
220 /* Intialize the power controller */
221 fvp_pwrc_setup();
222
Ian Spray84687392014-01-02 16:57:12 +0000223 /* Topologies are best known to the platform. */
Dan Handleyea451572014-05-15 14:53:30 +0100224 fvp_setup_topology();
Achin Gupta4f6ad662013-10-25 09:08:21 +0100225}
226
227/*******************************************************************************
228 * Perform the very early platform specific architectural setup here. At the
229 * moment this is only intializes the mmu in a quick and dirty way.
230 ******************************************************************************/
Juan Castillo2d552402014-06-13 17:05:10 +0100231void bl31_plat_arch_setup(void)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100232{
Dan Handleybe234f92014-08-04 16:11:15 +0100233 fvp_cci_init();
Vikram Kanigiri96377452014-04-24 11:02:16 +0100234#if RESET_TO_BL31
Dan Handleybe234f92014-08-04 16:11:15 +0100235 fvp_cci_enable();
Dan Handleyea451572014-05-15 14:53:30 +0100236#endif
237 fvp_configure_mmu_el3(BL31_RO_BASE,
238 (BL31_COHERENT_RAM_LIMIT - BL31_RO_BASE),
239 BL31_RO_BASE,
240 BL31_RO_LIMIT,
241 BL31_COHERENT_RAM_BASE,
242 BL31_COHERENT_RAM_LIMIT);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100243}