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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Dan Handleye83b0ca2014-01-14 18:17:09 +00002 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
Sandrine Bailleux3fa98472014-03-31 11:25:18 +010031#include <arch.h>
Vikram Kanigiri96377452014-04-24 11:02:16 +010032#include <arch_helpers.h>
Vikram Kanigirida567432014-04-15 18:08:08 +010033#include <assert.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010034#include <bl_common.h>
35#include <bl31.h>
Vikram Kanigiri3ff77de2014-03-25 17:35:26 +000036#include <console.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010037#include <mmio.h>
38#include <platform.h>
39#include <stddef.h>
Dan Handley4d2e49d2014-04-11 11:52:12 +010040#include "drivers/pwrc/fvp_pwrc.h"
Dan Handleyed6ff952014-05-14 17:44:19 +010041#include "fvp_def.h"
42#include "fvp_private.h"
Achin Gupta4f6ad662013-10-25 09:08:21 +010043
44/*******************************************************************************
45 * Declarations of linker defined symbols which will help us find the layout
46 * of trusted SRAM
47 ******************************************************************************/
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000048extern unsigned long __RO_START__;
49extern unsigned long __RO_END__;
Achin Gupta4f6ad662013-10-25 09:08:21 +010050
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000051extern unsigned long __COHERENT_RAM_START__;
52extern unsigned long __COHERENT_RAM_END__;
Achin Gupta4f6ad662013-10-25 09:08:21 +010053
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000054/*
55 * The next 2 constants identify the extents of the code & RO data region.
56 * These addresses are used by the MMU setup code and therefore they must be
57 * page-aligned. It is the responsibility of the linker script to ensure that
58 * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses.
59 */
60#define BL31_RO_BASE (unsigned long)(&__RO_START__)
61#define BL31_RO_LIMIT (unsigned long)(&__RO_END__)
62
63/*
64 * The next 2 constants identify the extents of the coherent memory region.
65 * These addresses are used by the MMU setup code and therefore they must be
66 * page-aligned. It is the responsibility of the linker script to ensure that
67 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols
68 * refer to page-aligned addresses.
69 */
70#define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
71#define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
Achin Gupta4f6ad662013-10-25 09:08:21 +010072
Vikram Kanigiri96377452014-04-24 11:02:16 +010073
74#if RESET_TO_BL31
75static entry_point_info_t bl32_entrypoint_info;
76static entry_point_info_t bl33_entrypoint_info;
77#else
Achin Gupta4f6ad662013-10-25 09:08:21 +010078/*******************************************************************************
Achin Guptae4d084e2014-02-19 17:18:23 +000079 * Reference to structure which holds the arguments that have been passed to
80 * BL31 from BL2.
Achin Gupta4f6ad662013-10-25 09:08:21 +010081 ******************************************************************************/
Vikram Kanigirida567432014-04-15 18:08:08 +010082static bl31_params_t *bl2_to_bl31_params;
Vikram Kanigiri96377452014-04-24 11:02:16 +010083#endif
Achin Gupta35ca3512014-02-19 17:58:33 +000084
Achin Gupta4f6ad662013-10-25 09:08:21 +010085/*******************************************************************************
Vikram Kanigirida567432014-04-15 18:08:08 +010086 * Return a pointer to the 'entry_point_info' structure of the next image for the
Achin Gupta35ca3512014-02-19 17:58:33 +000087 * security state specified. BL33 corresponds to the non-secure image type
88 * while BL32 corresponds to the secure image type. A NULL pointer is returned
89 * if the image does not exist.
Achin Gupta4f6ad662013-10-25 09:08:21 +010090 ******************************************************************************/
Dan Handley701fea72014-05-27 16:17:21 +010091entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
Achin Gupta4f6ad662013-10-25 09:08:21 +010092{
Vikram Kanigirida567432014-04-15 18:08:08 +010093 entry_point_info_t *next_image_info;
Achin Gupta35ca3512014-02-19 17:58:33 +000094
Vikram Kanigiri96377452014-04-24 11:02:16 +010095#if RESET_TO_BL31
96
97 if (type == NON_SECURE)
Dan Handleyea451572014-05-15 14:53:30 +010098 fvp_get_entry_point_info(NON_SECURE, &bl33_entrypoint_info);
Vikram Kanigiri96377452014-04-24 11:02:16 +010099 else
Dan Handleyea451572014-05-15 14:53:30 +0100100 fvp_get_entry_point_info(SECURE, &bl32_entrypoint_info);
Vikram Kanigiri96377452014-04-24 11:02:16 +0100101
Achin Gupta35ca3512014-02-19 17:58:33 +0000102 next_image_info = (type == NON_SECURE) ?
Vikram Kanigiri96377452014-04-24 11:02:16 +0100103 &bl33_entrypoint_info :
104 &bl32_entrypoint_info;
105#else
106 next_image_info = (type == NON_SECURE) ?
Vikram Kanigirida567432014-04-15 18:08:08 +0100107 bl2_to_bl31_params->bl33_ep_info :
108 bl2_to_bl31_params->bl32_ep_info;
Vikram Kanigiri96377452014-04-24 11:02:16 +0100109#endif
110
Achin Gupta35ca3512014-02-19 17:58:33 +0000111
112 /* None of the images on this platform can have 0x0 as the entrypoint */
Vikram Kanigirida567432014-04-15 18:08:08 +0100113 if (next_image_info->pc)
Achin Gupta35ca3512014-02-19 17:58:33 +0000114 return next_image_info;
115 else
116 return NULL;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100117}
118
119/*******************************************************************************
Achin Guptae4d084e2014-02-19 17:18:23 +0000120 * Perform any BL31 specific platform actions. Here is an opportunity to copy
121 * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they
122 * are lost (potentially). This needs to be done before the MMU is initialized
123 * so that the memory layout can be used while creating page tables. On the FVP
124 * we know that BL2 has populated the parameters in secure DRAM. So we just use
125 * the reference passed in 'from_bl2' instead of copying. The 'data' parameter
126 * is not used since all the information is contained in 'from_bl2'. Also, BL2
127 * has flushed this information to memory, so we are guaranteed to pick up good
128 * data
Achin Gupta4f6ad662013-10-25 09:08:21 +0100129 ******************************************************************************/
Vikram Kanigirida567432014-04-15 18:08:08 +0100130void bl31_early_platform_setup(bl31_params_t *from_bl2,
Vikram Kanigirid8c9d262014-05-16 18:48:12 +0100131 void *plat_params_from_bl2)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100132{
Vikram Kanigiri3684abf2014-03-27 14:33:15 +0000133 /* Initialize the console to provide early debug support */
134 console_init(PL011_UART0_BASE);
135
Achin Gupta4f6ad662013-10-25 09:08:21 +0100136 /* Initialize the platform config for future decision making */
Dan Handleyea451572014-05-15 14:53:30 +0100137 fvp_config_setup();
Vikram Kanigiri96377452014-04-24 11:02:16 +0100138
139#if RESET_TO_BL31
140 /* There are no parameters from BL2 if BL31 is a reset vector */
141 assert(from_bl2 == NULL);
142 assert(plat_params_from_bl2 == NULL);
143
144
145 /*
146 * Do initial security configuration to allow DRAM/device access. On
147 * Base FVP only DRAM security is programmable (via TrustZone), but
148 * other platforms might have more programmable security devices
149 * present.
150 */
Dan Handleyea451572014-05-15 14:53:30 +0100151 fvp_security_setup();
Vikram Kanigiri96377452014-04-24 11:02:16 +0100152#else
153 /* Check params passed from BL2 should not be NULL,
154 * We are not checking plat_params_from_bl2 as NULL as we are not
155 * using it on FVP
156 */
157 assert(from_bl2 != NULL);
158 assert(from_bl2->h.type == PARAM_BL31);
159 assert(from_bl2->h.version >= VERSION_1);
160
161 bl2_to_bl31_params = from_bl2;
Andrew Thoelkea55566d2014-05-28 22:22:55 +0100162 assert(((unsigned long)plat_params_from_bl2) == FVP_BL31_PLAT_PARAM_VAL);
Vikram Kanigiri96377452014-04-24 11:02:16 +0100163#endif
Achin Gupta4f6ad662013-10-25 09:08:21 +0100164}
165
166/*******************************************************************************
167 * Initialize the gic, configure the CLCD and zero out variables needed by the
168 * secondaries to boot up correctly.
169 ******************************************************************************/
170void bl31_platform_setup()
171{
172 unsigned int reg_val;
173
Ian Spray84687392014-01-02 16:57:12 +0000174 /* Initialize the gic cpu and distributor interfaces */
175 gic_setup();
Achin Gupta4f6ad662013-10-25 09:08:21 +0100176
177 /*
178 * TODO: Configure the CLCD before handing control to
179 * linux. Need to see if a separate driver is needed
180 * instead.
181 */
182 mmio_write_32(VE_SYSREGS_BASE + V2M_SYS_CFGDATA, 0);
183 mmio_write_32(VE_SYSREGS_BASE + V2M_SYS_CFGCTRL,
184 (1ull << 31) | (1 << 30) | (7 << 20) | (0 << 16));
185
Sandrine Bailleux3fa98472014-03-31 11:25:18 +0100186 /* Enable and initialize the System level generic timer */
187 mmio_write_32(SYS_CNTCTL_BASE + CNTCR_OFF, CNTCR_FCREQ(0) | CNTCR_EN);
188
Achin Gupta4f6ad662013-10-25 09:08:21 +0100189 /* Allow access to the System counter timer module */
190 reg_val = (1 << CNTACR_RPCT_SHIFT) | (1 << CNTACR_RVCT_SHIFT);
191 reg_val |= (1 << CNTACR_RFRQ_SHIFT) | (1 << CNTACR_RVOFF_SHIFT);
192 reg_val |= (1 << CNTACR_RWVT_SHIFT) | (1 << CNTACR_RWPT_SHIFT);
193 mmio_write_32(SYS_TIMCTL_BASE + CNTACR_BASE(0), reg_val);
194 mmio_write_32(SYS_TIMCTL_BASE + CNTACR_BASE(1), reg_val);
195
196 reg_val = (1 << CNTNSAR_NS_SHIFT(0)) | (1 << CNTNSAR_NS_SHIFT(1));
197 mmio_write_32(SYS_TIMCTL_BASE + CNTNSAR, reg_val);
198
199 /* Intialize the power controller */
200 fvp_pwrc_setup();
201
Ian Spray84687392014-01-02 16:57:12 +0000202 /* Topologies are best known to the platform. */
Dan Handleyea451572014-05-15 14:53:30 +0100203 fvp_setup_topology();
Achin Gupta4f6ad662013-10-25 09:08:21 +0100204}
205
206/*******************************************************************************
207 * Perform the very early platform specific architectural setup here. At the
208 * moment this is only intializes the mmu in a quick and dirty way.
209 ******************************************************************************/
210void bl31_plat_arch_setup()
211{
Vikram Kanigiri96377452014-04-24 11:02:16 +0100212#if RESET_TO_BL31
213 fvp_cci_setup();
Vikram Kanigiri96377452014-04-24 11:02:16 +0100214
Dan Handleyea451572014-05-15 14:53:30 +0100215#endif
216 fvp_configure_mmu_el3(BL31_RO_BASE,
217 (BL31_COHERENT_RAM_LIMIT - BL31_RO_BASE),
218 BL31_RO_BASE,
219 BL31_RO_LIMIT,
220 BL31_COHERENT_RAM_BASE,
221 BL31_COHERENT_RAM_LIMIT);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100222}
Vikram Kanigiri96377452014-04-24 11:02:16 +0100223
224#if RESET_TO_BL31
225/*******************************************************************************
226 * Generate the entry point info for Non Secure and Secure images
227 * for transferring control from BL31
228 ******************************************************************************/
Dan Handleyea451572014-05-15 14:53:30 +0100229void fvp_get_entry_point_info(unsigned long target_security,
Vikram Kanigiri96377452014-04-24 11:02:16 +0100230 entry_point_info_t *target_entry_info)
231{
232 if (target_security == NON_SECURE) {
233 SET_PARAM_HEAD(target_entry_info,
234 PARAM_EP,
235 VERSION_1,
236 0);
237 /*
238 * Tell BL31 where the non-trusted software image
239 * is located and the entry state information
240 */
241 target_entry_info->pc = plat_get_ns_image_entrypoint();
242
243 fvp_set_bl33_ep_info(target_entry_info);
244
245 } else {
246 SET_PARAM_HEAD(target_entry_info,
247 PARAM_EP,
248 VERSION_1,
249 0);
250 if (BL32_BASE != 0) {
251 /* Hard coding entry point to the base of the BL32 */
252 target_entry_info->pc = BL32_BASE;
253 fvp_set_bl32_ep_info(target_entry_info);
254 }
255 }
256}
257#endif