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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Soby Mathew73308d02018-01-09 14:36:14 +00002 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
Sandrine Bailleuxc10bd2c2013-11-12 16:41:16 +00007#include <arch.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +01008#include <bl_common.h>
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +01009#include <el3_common_macros.S>
dp-arm3cac7862016-09-19 11:18:44 +010010#include <pmf_asm_macros.S>
11#include <runtime_instr.h>
Antonio Nino Diaz7c2a3ca2018-02-23 15:07:54 +000012#include <xlat_mmu_helpers.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010013
14 .globl bl31_entrypoint
Soby Mathewd0194872016-04-29 19:01:30 +010015 .globl bl31_warm_entrypoint
Achin Gupta4f6ad662013-10-25 09:08:21 +010016
Achin Gupta4f6ad662013-10-25 09:08:21 +010017 /* -----------------------------------------------------
18 * bl31_entrypoint() is the cold boot entrypoint,
19 * executed only by the primary cpu.
20 * -----------------------------------------------------
21 */
22
Andrew Thoelke38bde412014-03-18 13:46:55 +000023func bl31_entrypoint
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +010024#if !RESET_TO_BL31
Vikram Kanigirida567432014-04-15 18:08:08 +010025 /* ---------------------------------------------------------------
Soby Mathew73308d02018-01-09 14:36:14 +000026 * Stash the previous bootloader arguments x0 - x3 for later use.
Vikram Kanigirida567432014-04-15 18:08:08 +010027 * ---------------------------------------------------------------
Sandrine Bailleuxc10bd2c2013-11-12 16:41:16 +000028 */
Vikram Kanigiria3a5e4a2014-05-15 18:27:15 +010029 mov x20, x0
30 mov x21, x1
Soby Mathew73308d02018-01-09 14:36:14 +000031 mov x22, x2
32 mov x23, x3
Sandrine Bailleuxc10bd2c2013-11-12 16:41:16 +000033
Harry Liebel4f603682014-01-14 18:11:48 +000034 /* ---------------------------------------------------------------------
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +010035 * For !RESET_TO_BL31 systems, only the primary CPU ever reaches
36 * bl31_entrypoint() during the cold boot flow, so the cold/warm boot
37 * and primary/secondary CPU logic should not be executed in this case.
Harry Liebel4f603682014-01-14 18:11:48 +000038 *
David Cunadofee86532017-04-13 22:38:29 +010039 * Also, assume that the previous bootloader has already initialised the
40 * SCTLR_EL3, including the endianness, and has initialised the memory.
Harry Liebel4f603682014-01-14 18:11:48 +000041 * ---------------------------------------------------------------------
42 */
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +010043 el3_entrypoint_common \
David Cunadofee86532017-04-13 22:38:29 +010044 _init_sctlr=0 \
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +010045 _warm_boot_mailbox=0 \
46 _secondary_cold_boot=0 \
47 _init_memory=0 \
48 _init_c_runtime=1 \
49 _exception_vectors=runtime_exceptions
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +010050#else
Sandrine Bailleux449dbd52015-06-02 17:19:43 +010051 /* ---------------------------------------------------------------------
52 * For RESET_TO_BL31 systems which have a programmable reset address,
53 * bl31_entrypoint() is executed only on the cold boot path so we can
54 * skip the warm boot mailbox mechanism.
55 * ---------------------------------------------------------------------
56 */
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +010057 el3_entrypoint_common \
David Cunadofee86532017-04-13 22:38:29 +010058 _init_sctlr=1 \
Sandrine Bailleux449dbd52015-06-02 17:19:43 +010059 _warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \
Sandrine Bailleuxb21b02f2015-10-30 15:05:17 +000060 _secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +010061 _init_memory=1 \
62 _init_c_runtime=1 \
63 _exception_vectors=runtime_exceptions
Jeenu Viswambharancaa84932014-02-06 10:36:15 +000064
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +010065 /* ---------------------------------------------------------------------
Juan Castillo7d199412015-12-14 09:35:25 +000066 * For RESET_TO_BL31 systems, BL31 is the first bootloader to run so
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +010067 * there's no argument to relay from a previous bootloader. Zero the
68 * arguments passed to the platform layer to reflect that.
69 * ---------------------------------------------------------------------
Achin Gupta4f6ad662013-10-25 09:08:21 +010070 */
Soby Mathew73308d02018-01-09 14:36:14 +000071 mov x20, 0
72 mov x21, 0
73 mov x22, 0
74 mov x23, 0
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +010075#endif /* RESET_TO_BL31 */
Achin Gupta4f6ad662013-10-25 09:08:21 +010076 /* ---------------------------------------------
77 * Perform platform specific early arch. setup
78 * ---------------------------------------------
79 */
Soby Mathew73308d02018-01-09 14:36:14 +000080 mov x0, x20
81 mov x1, x21
82 mov x2, x22
83 mov x3, x23
84 bl bl31_early_platform_setup2
Achin Gupta4f6ad662013-10-25 09:08:21 +010085 bl bl31_plat_arch_setup
86
87 /* ---------------------------------------------
Jeenu Viswambharancaa84932014-02-06 10:36:15 +000088 * Jump to main function.
Achin Guptab739f222014-01-18 16:50:09 +000089 * ---------------------------------------------
90 */
Jeenu Viswambharancaa84932014-02-06 10:36:15 +000091 bl bl31_main
Achin Guptab739f222014-01-18 16:50:09 +000092
Achin Guptae9c4a642015-09-11 16:03:13 +010093 /* -------------------------------------------------------------
94 * Clean the .data & .bss sections to main memory. This ensures
95 * that any global data which was initialised by the primary CPU
96 * is visible to secondary CPUs before they enable their data
97 * caches and participate in coherency.
98 * -------------------------------------------------------------
99 */
100 adr x0, __DATA_START__
101 adr x1, __DATA_END__
102 sub x1, x1, x0
103 bl clean_dcache_range
104
105 adr x0, __BSS_START__
106 adr x1, __BSS_END__
107 sub x1, x1, x0
108 bl clean_dcache_range
109
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000110 b el3_exit
Kévin Petita877c252015-03-24 14:03:57 +0000111endfunc bl31_entrypoint
Soby Mathewd0194872016-04-29 19:01:30 +0100112
113 /* --------------------------------------------------------------------
114 * This CPU has been physically powered up. It is either resuming from
115 * suspend or has simply been turned on. In both cases, call the BL31
116 * warmboot entrypoint
117 * --------------------------------------------------------------------
118 */
119func bl31_warm_entrypoint
dp-arm3cac7862016-09-19 11:18:44 +0100120#if ENABLE_RUNTIME_INSTRUMENTATION
121
122 /*
123 * This timestamp update happens with cache off. The next
124 * timestamp collection will need to do cache maintenance prior
125 * to timestamp update.
126 */
127 pmf_calc_timestamp_addr rt_instr_svc RT_INSTR_EXIT_HW_LOW_PWR
128 mrs x1, cntpct_el0
129 str x1, [x0]
130#endif
131
Soby Mathewd0194872016-04-29 19:01:30 +0100132 /*
133 * On the warm boot path, most of the EL3 initialisations performed by
134 * 'el3_entrypoint_common' must be skipped:
135 *
136 * - Only when the platform bypasses the BL1/BL31 entrypoint by
David Cunadofee86532017-04-13 22:38:29 +0100137 * programming the reset address do we need to initialise SCTLR_EL3.
Soby Mathewd0194872016-04-29 19:01:30 +0100138 * In other cases, we assume this has been taken care by the
139 * entrypoint code.
140 *
141 * - No need to determine the type of boot, we know it is a warm boot.
142 *
143 * - Do not try to distinguish between primary and secondary CPUs, this
144 * notion only exists for a cold boot.
145 *
146 * - No need to initialise the memory or the C runtime environment,
147 * it has been done once and for all on the cold boot path.
148 */
149 el3_entrypoint_common \
David Cunadofee86532017-04-13 22:38:29 +0100150 _init_sctlr=PROGRAMMABLE_RESET_ADDRESS \
Soby Mathewd0194872016-04-29 19:01:30 +0100151 _warm_boot_mailbox=0 \
152 _secondary_cold_boot=0 \
153 _init_memory=0 \
154 _init_c_runtime=0 \
155 _exception_vectors=runtime_exceptions
156
Jeenu Viswambharan46144962017-01-05 10:37:21 +0000157 /*
158 * We're about to enable MMU and participate in PSCI state coordination.
159 *
160 * The PSCI implementation invokes platform routines that enable CPUs to
161 * participate in coherency. On a system where CPUs are not
Soby Mathew043fe9c2017-04-10 22:35:42 +0100162 * cache-coherent without appropriate platform specific programming,
163 * having caches enabled until such time might lead to coherency issues
164 * (resulting from stale data getting speculatively fetched, among
165 * others). Therefore we keep data caches disabled even after enabling
166 * the MMU for such platforms.
Jeenu Viswambharan46144962017-01-05 10:37:21 +0000167 *
Soby Mathew043fe9c2017-04-10 22:35:42 +0100168 * On systems with hardware-assisted coherency, or on single cluster
169 * platforms, such platform specific programming is not required to
170 * enter coherency (as CPUs already are); and there's no reason to have
171 * caches disabled either.
Soby Mathewd0194872016-04-29 19:01:30 +0100172 */
173 mov x0, #DISABLE_DCACHE
174 bl bl31_plat_enable_mmu
175
Soby Mathew043fe9c2017-04-10 22:35:42 +0100176#if HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY
177 mrs x0, sctlr_el3
178 orr x0, x0, #SCTLR_C_BIT
179 msr sctlr_el3, x0
180 isb
181#endif
182
Soby Mathewd0194872016-04-29 19:01:30 +0100183 bl psci_warmboot_entrypoint
184
dp-arm3cac7862016-09-19 11:18:44 +0100185#if ENABLE_RUNTIME_INSTRUMENTATION
186 pmf_calc_timestamp_addr rt_instr_svc RT_INSTR_EXIT_PSCI
187 mov x19, x0
188
189 /*
190 * Invalidate before updating timestamp to ensure previous timestamp
191 * updates on the same cache line with caches disabled are properly
192 * seen by the same core. Without the cache invalidate, the core might
193 * write into a stale cache line.
194 */
195 mov x1, #PMF_TS_SIZE
196 mov x20, x30
197 bl inv_dcache_range
198 mov x30, x20
199
200 mrs x0, cntpct_el0
201 str x0, [x19]
202#endif
Soby Mathewd0194872016-04-29 19:01:30 +0100203 b el3_exit
204endfunc bl31_warm_entrypoint