Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 1 | /* |
Jayanth Dodderi Chidanand | cc02b96 | 2023-04-12 18:05:58 +0100 | [diff] [blame] | 2 | * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved. |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 5 | */ |
| 6 | #include <arch.h> |
| 7 | #include <asm_macros.S> |
| 8 | #include <assert_macros.S> |
| 9 | #include <cortex_a72.h> |
| 10 | #include <cpu_macros.S> |
| 11 | #include <plat_macros.S> |
Bipin Ravi | cf4d50a | 2022-02-15 23:24:51 -0600 | [diff] [blame] | 12 | #include "wa_cve_2022_23960_bhb_vector.S" |
| 13 | |
| 14 | #if WORKAROUND_CVE_2022_23960 |
| 15 | wa_cve_2022_23960_bhb_vector_table CORTEX_A72_BHB_LOOP_COUNT, cortex_a72 |
| 16 | #endif /* WORKAROUND_CVE_2022_23960 */ |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 17 | |
| 18 | /* --------------------------------------------- |
| 19 | * Disable L1 data cache and unified L2 cache |
| 20 | * --------------------------------------------- |
| 21 | */ |
| 22 | func cortex_a72_disable_dcache |
| 23 | mrs x1, sctlr_el3 |
| 24 | bic x1, x1, #SCTLR_C_BIT |
| 25 | msr sctlr_el3, x1 |
| 26 | isb |
| 27 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 28 | endfunc cortex_a72_disable_dcache |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 29 | |
| 30 | /* --------------------------------------------- |
| 31 | * Disable all types of L2 prefetches. |
| 32 | * --------------------------------------------- |
| 33 | */ |
| 34 | func cortex_a72_disable_l2_prefetch |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 35 | mrs x0, CORTEX_A72_ECTLR_EL1 |
| 36 | orr x0, x0, #CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT |
| 37 | mov x1, #CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK |
| 38 | orr x1, x1, #CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 39 | bic x0, x0, x1 |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 40 | msr CORTEX_A72_ECTLR_EL1, x0 |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 41 | isb |
| 42 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 43 | endfunc cortex_a72_disable_l2_prefetch |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 44 | |
| 45 | /* --------------------------------------------- |
| 46 | * Disable the load-store hardware prefetcher. |
| 47 | * --------------------------------------------- |
| 48 | */ |
| 49 | func cortex_a72_disable_hw_prefetcher |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 50 | mrs x0, CORTEX_A72_CPUACTLR_EL1 |
| 51 | orr x0, x0, #CORTEX_A72_CPUACTLR_EL1_DISABLE_L1_DCACHE_HW_PFTCH |
| 52 | msr CORTEX_A72_CPUACTLR_EL1, x0 |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 53 | isb |
| 54 | dsb ish |
| 55 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 56 | endfunc cortex_a72_disable_hw_prefetcher |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 57 | |
| 58 | /* --------------------------------------------- |
| 59 | * Disable intra-cluster coherency |
| 60 | * --------------------------------------------- |
| 61 | */ |
| 62 | func cortex_a72_disable_smp |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 63 | mrs x0, CORTEX_A72_ECTLR_EL1 |
| 64 | bic x0, x0, #CORTEX_A72_ECTLR_SMP_BIT |
| 65 | msr CORTEX_A72_ECTLR_EL1, x0 |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 66 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 67 | endfunc cortex_a72_disable_smp |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 68 | |
| 69 | /* --------------------------------------------- |
| 70 | * Disable debug interfaces |
| 71 | * --------------------------------------------- |
| 72 | */ |
| 73 | func cortex_a72_disable_ext_debug |
| 74 | mov x0, #1 |
| 75 | msr osdlr_el1, x0 |
| 76 | isb |
| 77 | dsb sy |
| 78 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 79 | endfunc cortex_a72_disable_ext_debug |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 80 | |
Jayanth Dodderi Chidanand | cc02b96 | 2023-04-12 18:05:58 +0100 | [diff] [blame] | 81 | func check_smccc_arch_workaround_3 |
| 82 | cpu_check_csv2 x0, 1f |
| 83 | mov x0, #ERRATA_APPLIES |
| 84 | ret |
| 85 | 1: |
| 86 | mov x0, #ERRATA_NOT_APPLIES |
| 87 | ret |
| 88 | endfunc check_smccc_arch_workaround_3 |
| 89 | |
Jayanth Dodderi Chidanand | b1cd7d5 | 2023-04-12 18:35:45 +0100 | [diff] [blame^] | 90 | workaround_reset_start cortex_a72, ERRATUM(859971), ERRATA_A72_859971 |
Eleanor Bonnici | c3b4ca1 | 2017-08-02 18:33:41 +0100 | [diff] [blame] | 91 | mrs x1, CORTEX_A72_CPUACTLR_EL1 |
| 92 | orr x1, x1, #CORTEX_A72_CPUACTLR_EL1_DIS_INSTR_PREFETCH |
| 93 | msr CORTEX_A72_CPUACTLR_EL1, x1 |
Jayanth Dodderi Chidanand | b1cd7d5 | 2023-04-12 18:35:45 +0100 | [diff] [blame^] | 94 | workaround_reset_end cortex_a72, ERRATUM(859971) |
Eleanor Bonnici | c3b4ca1 | 2017-08-02 18:33:41 +0100 | [diff] [blame] | 95 | |
Jayanth Dodderi Chidanand | b1cd7d5 | 2023-04-12 18:35:45 +0100 | [diff] [blame^] | 96 | check_erratum_ls cortex_a72, ERRATUM(859971), CPU_REV(0, 3) |
Eleanor Bonnici | c3b4ca1 | 2017-08-02 18:33:41 +0100 | [diff] [blame] | 97 | |
Jayanth Dodderi Chidanand | b1cd7d5 | 2023-04-12 18:35:45 +0100 | [diff] [blame^] | 98 | /* Due to the nature of the errata it is applied unconditionally when chosen */ |
| 99 | check_erratum_chosen cortex_a72, ERRATUM(1319367), ERRATA_A72_1319367 |
| 100 | /* erratum workaround is interleaved with generic code */ |
| 101 | add_erratum_entry cortex_a72, ERRATUM(1319367), ERRATA_A72_1319367, NO_APPLY_AT_RESET |
| 102 | |
| 103 | workaround_reset_start cortex_a72, CVE(2017, 5715), WORKAROUND_CVE_2017_5715 |
| 104 | #if IMAGE_BL31 |
| 105 | adr x0, wa_cve_2017_5715_mmu_vbar |
| 106 | msr vbar_el3, x0 |
Jayanth Dodderi Chidanand | cc02b96 | 2023-04-12 18:05:58 +0100 | [diff] [blame] | 107 | #endif |
Jayanth Dodderi Chidanand | b1cd7d5 | 2023-04-12 18:35:45 +0100 | [diff] [blame^] | 108 | workaround_reset_end cortex_a72, CVE(2017, 5715) |
Jayanth Dodderi Chidanand | cc02b96 | 2023-04-12 18:05:58 +0100 | [diff] [blame] | 109 | |
Jayanth Dodderi Chidanand | b1cd7d5 | 2023-04-12 18:35:45 +0100 | [diff] [blame^] | 110 | check_erratum_custom_start cortex_a72, CVE(2017, 5715) |
Dimitris Papastamos | 780cc95 | 2018-03-12 13:27:02 +0000 | [diff] [blame] | 111 | cpu_check_csv2 x0, 1f |
Dimitris Papastamos | 858bd61 | 2018-01-16 10:32:47 +0000 | [diff] [blame] | 112 | #if WORKAROUND_CVE_2017_5715 |
| 113 | mov x0, #ERRATA_APPLIES |
| 114 | #else |
| 115 | mov x0, #ERRATA_MISSING |
| 116 | #endif |
| 117 | ret |
Dimitris Papastamos | 780cc95 | 2018-03-12 13:27:02 +0000 | [diff] [blame] | 118 | 1: |
| 119 | mov x0, #ERRATA_NOT_APPLIES |
| 120 | ret |
Jayanth Dodderi Chidanand | b1cd7d5 | 2023-04-12 18:35:45 +0100 | [diff] [blame^] | 121 | check_erratum_custom_end cortex_a72, CVE(2017, 5715) |
Dimitris Papastamos | e6625ec | 2018-04-05 14:38:26 +0100 | [diff] [blame] | 122 | |
Jayanth Dodderi Chidanand | b1cd7d5 | 2023-04-12 18:35:45 +0100 | [diff] [blame^] | 123 | workaround_reset_start cortex_a72, CVE(2018, 3639), WORKAROUND_CVE_2018_3639 |
| 124 | mrs x0, CORTEX_A72_CPUACTLR_EL1 |
| 125 | orr x0, x0, #CORTEX_A72_CPUACTLR_EL1_DIS_LOAD_PASS_STORE |
| 126 | msr CORTEX_A72_CPUACTLR_EL1, x0 |
| 127 | isb |
| 128 | dsb sy |
| 129 | workaround_reset_end cortex_a72, CVE(2018, 3639) |
| 130 | check_erratum_chosen cortex_a72, CVE(2018, 3639), WORKAROUND_CVE_2018_3639 |
Bipin Ravi | cf4d50a | 2022-02-15 23:24:51 -0600 | [diff] [blame] | 131 | |
Jayanth Dodderi Chidanand | b1cd7d5 | 2023-04-12 18:35:45 +0100 | [diff] [blame^] | 132 | workaround_reset_start cortex_a72, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 |
| 133 | #if IMAGE_BL31 |
| 134 | /* Skip installing vector table again if already done for CVE(2017, 5715) */ |
Bipin Ravi | cf4d50a | 2022-02-15 23:24:51 -0600 | [diff] [blame] | 135 | /* |
| 136 | * The Cortex-A72 generic vectors are overridden to apply the |
Jayanth Dodderi Chidanand | b1cd7d5 | 2023-04-12 18:35:45 +0100 | [diff] [blame^] | 137 | * mitigation on exception entry from lower ELs for revisions >= r1p0 |
Bipin Ravi | cf4d50a | 2022-02-15 23:24:51 -0600 | [diff] [blame] | 138 | * which has CSV2 implemented. |
| 139 | */ |
| 140 | adr x0, wa_cve_vbar_cortex_a72 |
Jayanth Dodderi Chidanand | b1cd7d5 | 2023-04-12 18:35:45 +0100 | [diff] [blame^] | 141 | mrs x1, vbar_el3 |
| 142 | cmp x0, x1 |
| 143 | b.eq 1f |
Bipin Ravi | cf4d50a | 2022-02-15 23:24:51 -0600 | [diff] [blame] | 144 | msr vbar_el3, x0 |
Jayanth Dodderi Chidanand | b1cd7d5 | 2023-04-12 18:35:45 +0100 | [diff] [blame^] | 145 | 1: |
| 146 | #endif /* IMAGE_BL31 */ |
| 147 | workaround_reset_end cortex_a72, CVE(2022, 23960) |
Bipin Ravi | cf4d50a | 2022-02-15 23:24:51 -0600 | [diff] [blame] | 148 | |
Jayanth Dodderi Chidanand | b1cd7d5 | 2023-04-12 18:35:45 +0100 | [diff] [blame^] | 149 | check_erratum_custom_start cortex_a72, CVE(2022, 23960) |
| 150 | #if WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 |
| 151 | cpu_check_csv2 x0, 1f |
| 152 | mov x0, #ERRATA_APPLIES |
| 153 | ret |
| 154 | 1: |
| 155 | #if WORKAROUND_CVE_2022_23960 |
| 156 | mov x0, #ERRATA_APPLIES |
| 157 | #else |
| 158 | mov x0, #ERRATA_MISSING |
Bipin Ravi | cf4d50a | 2022-02-15 23:24:51 -0600 | [diff] [blame] | 159 | #endif /* WORKAROUND_CVE_2022_23960 */ |
Jayanth Dodderi Chidanand | b1cd7d5 | 2023-04-12 18:35:45 +0100 | [diff] [blame^] | 160 | ret |
| 161 | #endif /* WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 */ |
| 162 | mov x0, #ERRATA_MISSING |
| 163 | ret |
| 164 | check_erratum_custom_end cortex_a72, CVE(2022, 23960) |
Dimitris Papastamos | 446f7f1 | 2017-11-30 14:53:53 +0000 | [diff] [blame] | 165 | |
Jayanth Dodderi Chidanand | b1cd7d5 | 2023-04-12 18:35:45 +0100 | [diff] [blame^] | 166 | cpu_reset_func_start cortex_a72 |
Dimitris Papastamos | e6625ec | 2018-04-05 14:38:26 +0100 | [diff] [blame] | 167 | |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 168 | /* --------------------------------------------- |
Eleanor Bonnici | c3b4ca1 | 2017-08-02 18:33:41 +0100 | [diff] [blame] | 169 | * Enable the SMP bit. |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 170 | * --------------------------------------------- |
| 171 | */ |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 172 | mrs x0, CORTEX_A72_ECTLR_EL1 |
| 173 | orr x0, x0, #CORTEX_A72_ECTLR_SMP_BIT |
| 174 | msr CORTEX_A72_ECTLR_EL1, x0 |
Jayanth Dodderi Chidanand | b1cd7d5 | 2023-04-12 18:35:45 +0100 | [diff] [blame^] | 175 | |
| 176 | cpu_reset_func_end cortex_a72 |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 177 | |
| 178 | /* ---------------------------------------------------- |
| 179 | * The CPU Ops core power down function for Cortex-A72. |
| 180 | * ---------------------------------------------------- |
| 181 | */ |
| 182 | func cortex_a72_core_pwr_dwn |
| 183 | mov x18, x30 |
| 184 | |
| 185 | /* --------------------------------------------- |
| 186 | * Turn off caches. |
| 187 | * --------------------------------------------- |
| 188 | */ |
| 189 | bl cortex_a72_disable_dcache |
| 190 | |
| 191 | /* --------------------------------------------- |
| 192 | * Disable the L2 prefetches. |
| 193 | * --------------------------------------------- |
| 194 | */ |
| 195 | bl cortex_a72_disable_l2_prefetch |
| 196 | |
| 197 | /* --------------------------------------------- |
| 198 | * Disable the load-store hardware prefetcher. |
| 199 | * --------------------------------------------- |
| 200 | */ |
| 201 | bl cortex_a72_disable_hw_prefetcher |
| 202 | |
| 203 | /* --------------------------------------------- |
| 204 | * Flush L1 caches. |
| 205 | * --------------------------------------------- |
| 206 | */ |
| 207 | mov x0, #DCCISW |
| 208 | bl dcsw_op_level1 |
| 209 | |
| 210 | /* --------------------------------------------- |
| 211 | * Come out of intra cluster coherency |
| 212 | * --------------------------------------------- |
| 213 | */ |
| 214 | bl cortex_a72_disable_smp |
| 215 | |
| 216 | /* --------------------------------------------- |
| 217 | * Force the debug interfaces to be quiescent |
| 218 | * --------------------------------------------- |
| 219 | */ |
| 220 | mov x30, x18 |
| 221 | b cortex_a72_disable_ext_debug |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 222 | endfunc cortex_a72_core_pwr_dwn |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 223 | |
| 224 | /* ------------------------------------------------------- |
| 225 | * The CPU Ops cluster power down function for Cortex-A72. |
| 226 | * ------------------------------------------------------- |
| 227 | */ |
| 228 | func cortex_a72_cluster_pwr_dwn |
| 229 | mov x18, x30 |
| 230 | |
| 231 | /* --------------------------------------------- |
| 232 | * Turn off caches. |
| 233 | * --------------------------------------------- |
| 234 | */ |
| 235 | bl cortex_a72_disable_dcache |
| 236 | |
| 237 | /* --------------------------------------------- |
| 238 | * Disable the L2 prefetches. |
| 239 | * --------------------------------------------- |
| 240 | */ |
| 241 | bl cortex_a72_disable_l2_prefetch |
| 242 | |
| 243 | /* --------------------------------------------- |
| 244 | * Disable the load-store hardware prefetcher. |
| 245 | * --------------------------------------------- |
| 246 | */ |
| 247 | bl cortex_a72_disable_hw_prefetcher |
| 248 | |
| 249 | #if !SKIP_A72_L1_FLUSH_PWR_DWN |
| 250 | /* --------------------------------------------- |
| 251 | * Flush L1 caches. |
| 252 | * --------------------------------------------- |
| 253 | */ |
| 254 | mov x0, #DCCISW |
| 255 | bl dcsw_op_level1 |
| 256 | #endif |
| 257 | |
| 258 | /* --------------------------------------------- |
| 259 | * Disable the optional ACP. |
| 260 | * --------------------------------------------- |
| 261 | */ |
| 262 | bl plat_disable_acp |
| 263 | |
| 264 | /* ------------------------------------------------- |
| 265 | * Flush the L2 caches. |
| 266 | * ------------------------------------------------- |
| 267 | */ |
| 268 | mov x0, #DCCISW |
| 269 | bl dcsw_op_level2 |
| 270 | |
| 271 | /* --------------------------------------------- |
| 272 | * Come out of intra cluster coherency |
| 273 | * --------------------------------------------- |
| 274 | */ |
| 275 | bl cortex_a72_disable_smp |
| 276 | |
| 277 | /* --------------------------------------------- |
| 278 | * Force the debug interfaces to be quiescent |
| 279 | * --------------------------------------------- |
| 280 | */ |
| 281 | mov x30, x18 |
| 282 | b cortex_a72_disable_ext_debug |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 283 | endfunc cortex_a72_cluster_pwr_dwn |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 284 | |
Jayanth Dodderi Chidanand | b1cd7d5 | 2023-04-12 18:35:45 +0100 | [diff] [blame^] | 285 | errata_report_shim cortex_a72 |
Eleanor Bonnici | c3b4ca1 | 2017-08-02 18:33:41 +0100 | [diff] [blame] | 286 | |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 287 | /* --------------------------------------------- |
| 288 | * This function provides cortex_a72 specific |
| 289 | * register information for crash reporting. |
| 290 | * It needs to return with x6 pointing to |
| 291 | * a list of register names in ascii and |
| 292 | * x8 - x15 having values of registers to be |
| 293 | * reported. |
| 294 | * --------------------------------------------- |
| 295 | */ |
| 296 | .section .rodata.cortex_a72_regs, "aS" |
| 297 | cortex_a72_regs: /* The ascii list of register names to be reported */ |
Naga Sureshkumar Relli | 6a72a91 | 2016-07-01 12:52:41 +0530 | [diff] [blame] | 298 | .asciz "cpuectlr_el1", "cpumerrsr_el1", "l2merrsr_el1", "" |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 299 | |
| 300 | func cortex_a72_cpu_reg_dump |
| 301 | adr x6, cortex_a72_regs |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 302 | mrs x8, CORTEX_A72_ECTLR_EL1 |
| 303 | mrs x9, CORTEX_A72_MERRSR_EL1 |
| 304 | mrs x10, CORTEX_A72_L2MERRSR_EL1 |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 305 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 306 | endfunc cortex_a72_cpu_reg_dump |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 307 | |
Dimitris Papastamos | ba51d9e | 2018-05-16 11:36:14 +0100 | [diff] [blame] | 308 | declare_cpu_ops_wa cortex_a72, CORTEX_A72_MIDR, \ |
Jeenu Viswambharan | ee5eb80 | 2016-11-18 12:58:28 +0000 | [diff] [blame] | 309 | cortex_a72_reset_func, \ |
Jayanth Dodderi Chidanand | b1cd7d5 | 2023-04-12 18:35:45 +0100 | [diff] [blame^] | 310 | check_erratum_cortex_a72_5715, \ |
Dimitris Papastamos | ba51d9e | 2018-05-16 11:36:14 +0100 | [diff] [blame] | 311 | CPU_NO_EXTRA2_FUNC, \ |
Bipin Ravi | caa2e05 | 2022-02-23 23:45:50 -0600 | [diff] [blame] | 312 | check_smccc_arch_workaround_3, \ |
Jeenu Viswambharan | ee5eb80 | 2016-11-18 12:58:28 +0000 | [diff] [blame] | 313 | cortex_a72_core_pwr_dwn, \ |
| 314 | cortex_a72_cluster_pwr_dwn |