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git01.mediatek.com / filogic / atf / c47e0115b4818dce61f938d609ce4df4e997efe2 / . / lib / cpus / aarch64 / cortex_a72.S
blob: 2d054fcc9bc29c702e02ada09ec3ca6680a97188 [file] [log] [blame]
Vikram Kanigiric47e0112015-02-17 11:50:28 +0000[diff] [blame^]1/*
2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30#include <arch.h>
31#include <asm_macros.S>
32#include <assert_macros.S>
33#include <cortex_a72.h>
34#include <cpu_macros.S>
35#include <plat_macros.S>
36
37 /* ---------------------------------------------
38 * Disable L1 data cache and unified L2 cache
39 * ---------------------------------------------
40 */
41func cortex_a72_disable_dcache
42 mrs x1, sctlr_el3
43 bic x1, x1, #SCTLR_C_BIT
44 msr sctlr_el3, x1
45 isb
46 ret
47
48 /* ---------------------------------------------
49 * Disable all types of L2 prefetches.
50 * ---------------------------------------------
51 */
52func cortex_a72_disable_l2_prefetch
53 mrs x0, CPUECTLR_EL1
54 orr x0, x0, #CPUECTLR_DIS_TWD_ACC_PFTCH_BIT
55 mov x1, #CPUECTLR_L2_IPFTCH_DIST_MASK
56 orr x1, x1, #CPUECTLR_L2_DPFTCH_DIST_MASK
57 bic x0, x0, x1
58 msr CPUECTLR_EL1, x0
59 isb
60 ret
61
62 /* ---------------------------------------------
63 * Disable the load-store hardware prefetcher.
64 * ---------------------------------------------
65 */
66func cortex_a72_disable_hw_prefetcher
67 mrs x0, CPUACTLR_EL1
68 orr x0, x0, #CPUACTLR_DISABLE_L1_DCACHE_HW_PFTCH
69 msr CPUACTLR_EL1, x0
70 isb
71 dsb ish
72 ret
73
74 /* ---------------------------------------------
75 * Disable intra-cluster coherency
76 * ---------------------------------------------
77 */
78func cortex_a72_disable_smp
79 mrs x0, CPUECTLR_EL1
80 bic x0, x0, #CPUECTLR_SMP_BIT
81 msr CPUECTLR_EL1, x0
82 ret
83
84 /* ---------------------------------------------
85 * Disable debug interfaces
86 * ---------------------------------------------
87 */
88func cortex_a72_disable_ext_debug
89 mov x0, #1
90 msr osdlr_el1, x0
91 isb
92 dsb sy
93 ret
94
95 /* -------------------------------------------------
96 * The CPU Ops reset function for Cortex-A72.
97 * -------------------------------------------------
98 */
99func cortex_a72_reset_func
100 /* ---------------------------------------------
101 * As a bare minimum enable the SMP bit.
102 * ---------------------------------------------
103 */
104 mrs x0, CPUECTLR_EL1
105 orr x0, x0, #CPUECTLR_SMP_BIT
106 msr CPUECTLR_EL1, x0
107 isb
108 ret
109
110 /* ----------------------------------------------------
111 * The CPU Ops core power down function for Cortex-A72.
112 * ----------------------------------------------------
113 */
114func cortex_a72_core_pwr_dwn
115 mov x18, x30
116
117 /* ---------------------------------------------
118 * Turn off caches.
119 * ---------------------------------------------
120 */
121 bl cortex_a72_disable_dcache
122
123 /* ---------------------------------------------
124 * Disable the L2 prefetches.
125 * ---------------------------------------------
126 */
127 bl cortex_a72_disable_l2_prefetch
128
129 /* ---------------------------------------------
130 * Disable the load-store hardware prefetcher.
131 * ---------------------------------------------
132 */
133 bl cortex_a72_disable_hw_prefetcher
134
135 /* ---------------------------------------------
136 * Flush L1 caches.
137 * ---------------------------------------------
138 */
139 mov x0, #DCCISW
140 bl dcsw_op_level1
141
142 /* ---------------------------------------------
143 * Come out of intra cluster coherency
144 * ---------------------------------------------
145 */
146 bl cortex_a72_disable_smp
147
148 /* ---------------------------------------------
149 * Force the debug interfaces to be quiescent
150 * ---------------------------------------------
151 */
152 mov x30, x18
153 b cortex_a72_disable_ext_debug
154
155 /* -------------------------------------------------------
156 * The CPU Ops cluster power down function for Cortex-A72.
157 * -------------------------------------------------------
158 */
159func cortex_a72_cluster_pwr_dwn
160 mov x18, x30
161
162 /* ---------------------------------------------
163 * Turn off caches.
164 * ---------------------------------------------
165 */
166 bl cortex_a72_disable_dcache
167
168 /* ---------------------------------------------
169 * Disable the L2 prefetches.
170 * ---------------------------------------------
171 */
172 bl cortex_a72_disable_l2_prefetch
173
174 /* ---------------------------------------------
175 * Disable the load-store hardware prefetcher.
176 * ---------------------------------------------
177 */
178 bl cortex_a72_disable_hw_prefetcher
179
180#if !SKIP_A72_L1_FLUSH_PWR_DWN
181 /* ---------------------------------------------
182 * Flush L1 caches.
183 * ---------------------------------------------
184 */
185 mov x0, #DCCISW
186 bl dcsw_op_level1
187#endif
188
189 /* ---------------------------------------------
190 * Disable the optional ACP.
191 * ---------------------------------------------
192 */
193 bl plat_disable_acp
194
195 /* -------------------------------------------------
196 * Flush the L2 caches.
197 * -------------------------------------------------
198 */
199 mov x0, #DCCISW
200 bl dcsw_op_level2
201
202 /* ---------------------------------------------
203 * Come out of intra cluster coherency
204 * ---------------------------------------------
205 */
206 bl cortex_a72_disable_smp
207
208 /* ---------------------------------------------
209 * Force the debug interfaces to be quiescent
210 * ---------------------------------------------
211 */
212 mov x30, x18
213 b cortex_a72_disable_ext_debug
214
215 /* ---------------------------------------------
216 * This function provides cortex_a72 specific
217 * register information for crash reporting.
218 * It needs to return with x6 pointing to
219 * a list of register names in ascii and
220 * x8 - x15 having values of registers to be
221 * reported.
222 * ---------------------------------------------
223 */
224.section .rodata.cortex_a72_regs, "aS"
225cortex_a72_regs: /* The ascii list of register names to be reported */
226 .asciz "cpuectlr_el1", ""
227
228func cortex_a72_cpu_reg_dump
229 adr x6, cortex_a72_regs
230 mrs x8, CPUECTLR_EL1
231 ret
232
233
234declare_cpu_ops cortex_a72, CORTEX_A72_MIDR