Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 1 | /* |
Bipin Ravi | cf4d50a | 2022-02-15 23:24:51 -0600 | [diff] [blame^] | 2 | * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 5 | */ |
| 6 | #include <arch.h> |
| 7 | #include <asm_macros.S> |
| 8 | #include <assert_macros.S> |
| 9 | #include <cortex_a72.h> |
| 10 | #include <cpu_macros.S> |
| 11 | #include <plat_macros.S> |
Bipin Ravi | cf4d50a | 2022-02-15 23:24:51 -0600 | [diff] [blame^] | 12 | #include "wa_cve_2022_23960_bhb_vector.S" |
| 13 | |
| 14 | #if WORKAROUND_CVE_2022_23960 |
| 15 | wa_cve_2022_23960_bhb_vector_table CORTEX_A72_BHB_LOOP_COUNT, cortex_a72 |
| 16 | #endif /* WORKAROUND_CVE_2022_23960 */ |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 17 | |
| 18 | /* --------------------------------------------- |
| 19 | * Disable L1 data cache and unified L2 cache |
| 20 | * --------------------------------------------- |
| 21 | */ |
| 22 | func cortex_a72_disable_dcache |
| 23 | mrs x1, sctlr_el3 |
| 24 | bic x1, x1, #SCTLR_C_BIT |
| 25 | msr sctlr_el3, x1 |
| 26 | isb |
| 27 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 28 | endfunc cortex_a72_disable_dcache |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 29 | |
| 30 | /* --------------------------------------------- |
| 31 | * Disable all types of L2 prefetches. |
| 32 | * --------------------------------------------- |
| 33 | */ |
| 34 | func cortex_a72_disable_l2_prefetch |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 35 | mrs x0, CORTEX_A72_ECTLR_EL1 |
| 36 | orr x0, x0, #CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT |
| 37 | mov x1, #CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK |
| 38 | orr x1, x1, #CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 39 | bic x0, x0, x1 |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 40 | msr CORTEX_A72_ECTLR_EL1, x0 |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 41 | isb |
| 42 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 43 | endfunc cortex_a72_disable_l2_prefetch |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 44 | |
| 45 | /* --------------------------------------------- |
| 46 | * Disable the load-store hardware prefetcher. |
| 47 | * --------------------------------------------- |
| 48 | */ |
| 49 | func cortex_a72_disable_hw_prefetcher |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 50 | mrs x0, CORTEX_A72_CPUACTLR_EL1 |
| 51 | orr x0, x0, #CORTEX_A72_CPUACTLR_EL1_DISABLE_L1_DCACHE_HW_PFTCH |
| 52 | msr CORTEX_A72_CPUACTLR_EL1, x0 |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 53 | isb |
| 54 | dsb ish |
| 55 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 56 | endfunc cortex_a72_disable_hw_prefetcher |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 57 | |
| 58 | /* --------------------------------------------- |
| 59 | * Disable intra-cluster coherency |
| 60 | * --------------------------------------------- |
| 61 | */ |
| 62 | func cortex_a72_disable_smp |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 63 | mrs x0, CORTEX_A72_ECTLR_EL1 |
| 64 | bic x0, x0, #CORTEX_A72_ECTLR_SMP_BIT |
| 65 | msr CORTEX_A72_ECTLR_EL1, x0 |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 66 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 67 | endfunc cortex_a72_disable_smp |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 68 | |
| 69 | /* --------------------------------------------- |
| 70 | * Disable debug interfaces |
| 71 | * --------------------------------------------- |
| 72 | */ |
| 73 | func cortex_a72_disable_ext_debug |
| 74 | mov x0, #1 |
| 75 | msr osdlr_el1, x0 |
| 76 | isb |
| 77 | dsb sy |
| 78 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 79 | endfunc cortex_a72_disable_ext_debug |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 80 | |
Eleanor Bonnici | c3b4ca1 | 2017-08-02 18:33:41 +0100 | [diff] [blame] | 81 | /* -------------------------------------------------- |
| 82 | * Errata Workaround for Cortex A72 Errata #859971. |
| 83 | * This applies only to revision <= r0p3 of Cortex A72. |
| 84 | * Inputs: |
| 85 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 86 | * Shall clobber: |
| 87 | * -------------------------------------------------- |
| 88 | */ |
| 89 | func errata_a72_859971_wa |
| 90 | mov x17,x30 |
| 91 | bl check_errata_859971 |
| 92 | cbz x0, 1f |
| 93 | mrs x1, CORTEX_A72_CPUACTLR_EL1 |
| 94 | orr x1, x1, #CORTEX_A72_CPUACTLR_EL1_DIS_INSTR_PREFETCH |
| 95 | msr CORTEX_A72_CPUACTLR_EL1, x1 |
| 96 | 1: |
| 97 | ret x17 |
| 98 | endfunc errata_a72_859971_wa |
| 99 | |
| 100 | func check_errata_859971 |
| 101 | mov x1, #0x03 |
| 102 | b cpu_rev_var_ls |
| 103 | endfunc check_errata_859971 |
| 104 | |
Dimitris Papastamos | 858bd61 | 2018-01-16 10:32:47 +0000 | [diff] [blame] | 105 | func check_errata_cve_2017_5715 |
Dimitris Papastamos | 780cc95 | 2018-03-12 13:27:02 +0000 | [diff] [blame] | 106 | cpu_check_csv2 x0, 1f |
Dimitris Papastamos | 858bd61 | 2018-01-16 10:32:47 +0000 | [diff] [blame] | 107 | #if WORKAROUND_CVE_2017_5715 |
| 108 | mov x0, #ERRATA_APPLIES |
| 109 | #else |
| 110 | mov x0, #ERRATA_MISSING |
| 111 | #endif |
| 112 | ret |
Dimitris Papastamos | 780cc95 | 2018-03-12 13:27:02 +0000 | [diff] [blame] | 113 | 1: |
| 114 | mov x0, #ERRATA_NOT_APPLIES |
| 115 | ret |
Dimitris Papastamos | 858bd61 | 2018-01-16 10:32:47 +0000 | [diff] [blame] | 116 | endfunc check_errata_cve_2017_5715 |
| 117 | |
Dimitris Papastamos | e6625ec | 2018-04-05 14:38:26 +0100 | [diff] [blame] | 118 | func check_errata_cve_2018_3639 |
| 119 | #if WORKAROUND_CVE_2018_3639 |
| 120 | mov x0, #ERRATA_APPLIES |
| 121 | #else |
| 122 | mov x0, #ERRATA_MISSING |
| 123 | #endif |
| 124 | ret |
| 125 | endfunc check_errata_cve_2018_3639 |
| 126 | |
Manish V Badarkhe | 7672edf | 2020-08-03 18:43:14 +0100 | [diff] [blame] | 127 | /* -------------------------------------------------- |
| 128 | * Errata workaround for Cortex A72 Errata #1319367. |
| 129 | * This applies to all revisions of Cortex A72. |
| 130 | * -------------------------------------------------- |
| 131 | */ |
| 132 | func check_errata_1319367 |
| 133 | #if ERRATA_A72_1319367 |
| 134 | mov x0, #ERRATA_APPLIES |
| 135 | #else |
| 136 | mov x0, #ERRATA_MISSING |
| 137 | #endif |
| 138 | ret |
| 139 | endfunc check_errata_1319367 |
| 140 | |
Bipin Ravi | cf4d50a | 2022-02-15 23:24:51 -0600 | [diff] [blame^] | 141 | func check_errata_cve_2022_23960 |
| 142 | #if WORKAROUND_CVE_2022_23960 |
| 143 | mov x0, #ERRATA_APPLIES |
| 144 | #else |
| 145 | mov x0, #ERRATA_MISSING |
| 146 | #endif |
| 147 | ret |
| 148 | endfunc check_errata_cve_2022_23960 |
| 149 | |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 150 | /* ------------------------------------------------- |
| 151 | * The CPU Ops reset function for Cortex-A72. |
| 152 | * ------------------------------------------------- |
| 153 | */ |
| 154 | func cortex_a72_reset_func |
Eleanor Bonnici | c3b4ca1 | 2017-08-02 18:33:41 +0100 | [diff] [blame] | 155 | mov x19, x30 |
| 156 | bl cpu_get_rev_var |
| 157 | mov x18, x0 |
| 158 | |
| 159 | #if ERRATA_A72_859971 |
| 160 | mov x0, x18 |
| 161 | bl errata_a72_859971_wa |
| 162 | #endif |
Dimitris Papastamos | 446f7f1 | 2017-11-30 14:53:53 +0000 | [diff] [blame] | 163 | |
Bipin Ravi | cf4d50a | 2022-02-15 23:24:51 -0600 | [diff] [blame^] | 164 | #if IMAGE_BL31 && (WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960) |
Dimitris Papastamos | 780cc95 | 2018-03-12 13:27:02 +0000 | [diff] [blame] | 165 | cpu_check_csv2 x0, 1f |
Dimitris Papastamos | 570c06a | 2018-04-06 15:29:34 +0100 | [diff] [blame] | 166 | adr x0, wa_cve_2017_5715_mmu_vbar |
Dimitris Papastamos | 446f7f1 | 2017-11-30 14:53:53 +0000 | [diff] [blame] | 167 | msr vbar_el3, x0 |
Dimitris Papastamos | bb0aa39 | 2018-06-07 13:20:19 +0100 | [diff] [blame] | 168 | /* isb will be performed before returning from this function */ |
Bipin Ravi | cf4d50a | 2022-02-15 23:24:51 -0600 | [diff] [blame^] | 169 | |
| 170 | /* Skip CVE_2022_23960 mitigation if cve_2017_5715 mitigation applied */ |
| 171 | b 2f |
Dimitris Papastamos | 780cc95 | 2018-03-12 13:27:02 +0000 | [diff] [blame] | 172 | 1: |
Bipin Ravi | cf4d50a | 2022-02-15 23:24:51 -0600 | [diff] [blame^] | 173 | #if WORKAROUND_CVE_2022_23960 |
| 174 | /* |
| 175 | * The Cortex-A72 generic vectors are overridden to apply the |
| 176 | * mitigation on exception entry from lower ELs for revisions >= r1p0 |
| 177 | * which has CSV2 implemented. |
| 178 | */ |
| 179 | adr x0, wa_cve_vbar_cortex_a72 |
| 180 | msr vbar_el3, x0 |
| 181 | |
| 182 | /* isb will be performed before returning from this function */ |
| 183 | #endif /* WORKAROUND_CVE_2022_23960 */ |
| 184 | 2: |
| 185 | #endif /* IMAGE_BL31 && (WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960) */ |
Dimitris Papastamos | 446f7f1 | 2017-11-30 14:53:53 +0000 | [diff] [blame] | 186 | |
Dimitris Papastamos | e6625ec | 2018-04-05 14:38:26 +0100 | [diff] [blame] | 187 | #if WORKAROUND_CVE_2018_3639 |
| 188 | mrs x0, CORTEX_A72_CPUACTLR_EL1 |
| 189 | orr x0, x0, #CORTEX_A72_CPUACTLR_EL1_DIS_LOAD_PASS_STORE |
| 190 | msr CORTEX_A72_CPUACTLR_EL1, x0 |
| 191 | isb |
| 192 | dsb sy |
| 193 | #endif |
| 194 | |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 195 | /* --------------------------------------------- |
Eleanor Bonnici | c3b4ca1 | 2017-08-02 18:33:41 +0100 | [diff] [blame] | 196 | * Enable the SMP bit. |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 197 | * --------------------------------------------- |
| 198 | */ |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 199 | mrs x0, CORTEX_A72_ECTLR_EL1 |
| 200 | orr x0, x0, #CORTEX_A72_ECTLR_SMP_BIT |
| 201 | msr CORTEX_A72_ECTLR_EL1, x0 |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 202 | isb |
Eleanor Bonnici | c3b4ca1 | 2017-08-02 18:33:41 +0100 | [diff] [blame] | 203 | ret x19 |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 204 | endfunc cortex_a72_reset_func |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 205 | |
| 206 | /* ---------------------------------------------------- |
| 207 | * The CPU Ops core power down function for Cortex-A72. |
| 208 | * ---------------------------------------------------- |
| 209 | */ |
| 210 | func cortex_a72_core_pwr_dwn |
| 211 | mov x18, x30 |
| 212 | |
| 213 | /* --------------------------------------------- |
| 214 | * Turn off caches. |
| 215 | * --------------------------------------------- |
| 216 | */ |
| 217 | bl cortex_a72_disable_dcache |
| 218 | |
| 219 | /* --------------------------------------------- |
| 220 | * Disable the L2 prefetches. |
| 221 | * --------------------------------------------- |
| 222 | */ |
| 223 | bl cortex_a72_disable_l2_prefetch |
| 224 | |
| 225 | /* --------------------------------------------- |
| 226 | * Disable the load-store hardware prefetcher. |
| 227 | * --------------------------------------------- |
| 228 | */ |
| 229 | bl cortex_a72_disable_hw_prefetcher |
| 230 | |
| 231 | /* --------------------------------------------- |
| 232 | * Flush L1 caches. |
| 233 | * --------------------------------------------- |
| 234 | */ |
| 235 | mov x0, #DCCISW |
| 236 | bl dcsw_op_level1 |
| 237 | |
| 238 | /* --------------------------------------------- |
| 239 | * Come out of intra cluster coherency |
| 240 | * --------------------------------------------- |
| 241 | */ |
| 242 | bl cortex_a72_disable_smp |
| 243 | |
| 244 | /* --------------------------------------------- |
| 245 | * Force the debug interfaces to be quiescent |
| 246 | * --------------------------------------------- |
| 247 | */ |
| 248 | mov x30, x18 |
| 249 | b cortex_a72_disable_ext_debug |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 250 | endfunc cortex_a72_core_pwr_dwn |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 251 | |
| 252 | /* ------------------------------------------------------- |
| 253 | * The CPU Ops cluster power down function for Cortex-A72. |
| 254 | * ------------------------------------------------------- |
| 255 | */ |
| 256 | func cortex_a72_cluster_pwr_dwn |
| 257 | mov x18, x30 |
| 258 | |
| 259 | /* --------------------------------------------- |
| 260 | * Turn off caches. |
| 261 | * --------------------------------------------- |
| 262 | */ |
| 263 | bl cortex_a72_disable_dcache |
| 264 | |
| 265 | /* --------------------------------------------- |
| 266 | * Disable the L2 prefetches. |
| 267 | * --------------------------------------------- |
| 268 | */ |
| 269 | bl cortex_a72_disable_l2_prefetch |
| 270 | |
| 271 | /* --------------------------------------------- |
| 272 | * Disable the load-store hardware prefetcher. |
| 273 | * --------------------------------------------- |
| 274 | */ |
| 275 | bl cortex_a72_disable_hw_prefetcher |
| 276 | |
| 277 | #if !SKIP_A72_L1_FLUSH_PWR_DWN |
| 278 | /* --------------------------------------------- |
| 279 | * Flush L1 caches. |
| 280 | * --------------------------------------------- |
| 281 | */ |
| 282 | mov x0, #DCCISW |
| 283 | bl dcsw_op_level1 |
| 284 | #endif |
| 285 | |
| 286 | /* --------------------------------------------- |
| 287 | * Disable the optional ACP. |
| 288 | * --------------------------------------------- |
| 289 | */ |
| 290 | bl plat_disable_acp |
| 291 | |
| 292 | /* ------------------------------------------------- |
| 293 | * Flush the L2 caches. |
| 294 | * ------------------------------------------------- |
| 295 | */ |
| 296 | mov x0, #DCCISW |
| 297 | bl dcsw_op_level2 |
| 298 | |
| 299 | /* --------------------------------------------- |
| 300 | * Come out of intra cluster coherency |
| 301 | * --------------------------------------------- |
| 302 | */ |
| 303 | bl cortex_a72_disable_smp |
| 304 | |
| 305 | /* --------------------------------------------- |
| 306 | * Force the debug interfaces to be quiescent |
| 307 | * --------------------------------------------- |
| 308 | */ |
| 309 | mov x30, x18 |
| 310 | b cortex_a72_disable_ext_debug |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 311 | endfunc cortex_a72_cluster_pwr_dwn |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 312 | |
Eleanor Bonnici | c3b4ca1 | 2017-08-02 18:33:41 +0100 | [diff] [blame] | 313 | #if REPORT_ERRATA |
| 314 | /* |
| 315 | * Errata printing function for Cortex A72. Must follow AAPCS. |
| 316 | */ |
| 317 | func cortex_a72_errata_report |
| 318 | stp x8, x30, [sp, #-16]! |
| 319 | |
| 320 | bl cpu_get_rev_var |
| 321 | mov x8, x0 |
| 322 | |
| 323 | /* |
| 324 | * Report all errata. The revision-variant information is passed to |
| 325 | * checking functions of each errata. |
| 326 | */ |
| 327 | report_errata ERRATA_A72_859971, cortex_a72, 859971 |
Manish V Badarkhe | 7672edf | 2020-08-03 18:43:14 +0100 | [diff] [blame] | 328 | report_errata ERRATA_A72_1319367, cortex_a72, 1319367 |
Dimitris Papastamos | 858bd61 | 2018-01-16 10:32:47 +0000 | [diff] [blame] | 329 | report_errata WORKAROUND_CVE_2017_5715, cortex_a72, cve_2017_5715 |
Dimitris Papastamos | e6625ec | 2018-04-05 14:38:26 +0100 | [diff] [blame] | 330 | report_errata WORKAROUND_CVE_2018_3639, cortex_a72, cve_2018_3639 |
Bipin Ravi | cf4d50a | 2022-02-15 23:24:51 -0600 | [diff] [blame^] | 331 | report_errata WORKAROUND_CVE_2022_23960, cortex_a72, cve_2022_23960 |
Eleanor Bonnici | c3b4ca1 | 2017-08-02 18:33:41 +0100 | [diff] [blame] | 332 | |
| 333 | ldp x8, x30, [sp], #16 |
| 334 | ret |
| 335 | endfunc cortex_a72_errata_report |
| 336 | #endif |
| 337 | |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 338 | /* --------------------------------------------- |
| 339 | * This function provides cortex_a72 specific |
| 340 | * register information for crash reporting. |
| 341 | * It needs to return with x6 pointing to |
| 342 | * a list of register names in ascii and |
| 343 | * x8 - x15 having values of registers to be |
| 344 | * reported. |
| 345 | * --------------------------------------------- |
| 346 | */ |
| 347 | .section .rodata.cortex_a72_regs, "aS" |
| 348 | cortex_a72_regs: /* The ascii list of register names to be reported */ |
Naga Sureshkumar Relli | 6a72a91 | 2016-07-01 12:52:41 +0530 | [diff] [blame] | 349 | .asciz "cpuectlr_el1", "cpumerrsr_el1", "l2merrsr_el1", "" |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 350 | |
| 351 | func cortex_a72_cpu_reg_dump |
| 352 | adr x6, cortex_a72_regs |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 353 | mrs x8, CORTEX_A72_ECTLR_EL1 |
| 354 | mrs x9, CORTEX_A72_MERRSR_EL1 |
| 355 | mrs x10, CORTEX_A72_L2MERRSR_EL1 |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 356 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 357 | endfunc cortex_a72_cpu_reg_dump |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 358 | |
Dimitris Papastamos | ba51d9e | 2018-05-16 11:36:14 +0100 | [diff] [blame] | 359 | declare_cpu_ops_wa cortex_a72, CORTEX_A72_MIDR, \ |
Jeenu Viswambharan | ee5eb80 | 2016-11-18 12:58:28 +0000 | [diff] [blame] | 360 | cortex_a72_reset_func, \ |
Dimitris Papastamos | 914757c | 2018-03-12 14:47:09 +0000 | [diff] [blame] | 361 | check_errata_cve_2017_5715, \ |
Dimitris Papastamos | ba51d9e | 2018-05-16 11:36:14 +0100 | [diff] [blame] | 362 | CPU_NO_EXTRA2_FUNC, \ |
Jeenu Viswambharan | ee5eb80 | 2016-11-18 12:58:28 +0000 | [diff] [blame] | 363 | cortex_a72_core_pwr_dwn, \ |
| 364 | cortex_a72_cluster_pwr_dwn |