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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Jeenu Viswambharan96c7df02017-11-30 12:54:15 +00002 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +01007#ifndef ARCH_H
8#define ARCH_H
Achin Gupta4f6ad662013-10-25 09:08:21 +01009
Scott Brandenbf404c02017-04-10 11:45:52 -070010#include <utils_def.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010011
12/*******************************************************************************
13 * MIDR bit definitions
14 ******************************************************************************/
Varun Wadekarc6a11f62017-05-25 18:04:48 -070015#define MIDR_IMPL_MASK U(0xff)
16#define MIDR_IMPL_SHIFT U(0x18)
17#define MIDR_VAR_SHIFT U(20)
18#define MIDR_VAR_BITS U(4)
19#define MIDR_VAR_MASK U(0xf)
20#define MIDR_REV_SHIFT U(0)
21#define MIDR_REV_BITS U(4)
22#define MIDR_REV_MASK U(0xf)
23#define MIDR_PN_MASK U(0xfff)
24#define MIDR_PN_SHIFT U(0x4)
Achin Gupta4f6ad662013-10-25 09:08:21 +010025
26/*******************************************************************************
27 * MPIDR macros
28 ******************************************************************************/
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010029#define MPIDR_MT_MASK (ULL(1) << 24)
Achin Gupta4f6ad662013-10-25 09:08:21 +010030#define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK
Varun Wadekarc6a11f62017-05-25 18:04:48 -070031#define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS)
32#define MPIDR_AFFINITY_BITS U(8)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010033#define MPIDR_AFFLVL_MASK ULL(0xff)
Varun Wadekarc6a11f62017-05-25 18:04:48 -070034#define MPIDR_AFF0_SHIFT U(0)
35#define MPIDR_AFF1_SHIFT U(8)
36#define MPIDR_AFF2_SHIFT U(16)
37#define MPIDR_AFF3_SHIFT U(32)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +000038#define MPIDR_AFF_SHIFT(_n) MPIDR_AFF##_n##_SHIFT
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010039#define MPIDR_AFFINITY_MASK ULL(0xff00ffffff)
Varun Wadekarc6a11f62017-05-25 18:04:48 -070040#define MPIDR_AFFLVL_SHIFT U(3)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +000041#define MPIDR_AFFLVL0 ULL(0x0)
42#define MPIDR_AFFLVL1 ULL(0x1)
43#define MPIDR_AFFLVL2 ULL(0x2)
44#define MPIDR_AFFLVL3 ULL(0x3)
45#define MPIDR_AFFLVL(_n) MPIDR_AFFLVL##_n
Vikram Kanigiri4e97e542015-02-26 15:25:58 +000046#define MPIDR_AFFLVL0_VAL(mpidr) \
Antonio Nino Diaz34235a32018-07-11 16:45:49 +010047 (((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK)
Vikram Kanigiri4e97e542015-02-26 15:25:58 +000048#define MPIDR_AFFLVL1_VAL(mpidr) \
Antonio Nino Diaz34235a32018-07-11 16:45:49 +010049 (((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK)
Vikram Kanigiri4e97e542015-02-26 15:25:58 +000050#define MPIDR_AFFLVL2_VAL(mpidr) \
Antonio Nino Diaz34235a32018-07-11 16:45:49 +010051 (((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK)
Vikram Kanigiri4e97e542015-02-26 15:25:58 +000052#define MPIDR_AFFLVL3_VAL(mpidr) \
Antonio Nino Diaz34235a32018-07-11 16:45:49 +010053 (((mpidr) >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK)
Soby Mathewe2b2d8f2014-12-04 14:14:12 +000054/*
55 * The MPIDR_MAX_AFFLVL count starts from 0. Take care to
56 * add one while using this macro to define array sizes.
57 * TODO: Support only the first 3 affinity levels for now.
58 */
Varun Wadekarc6a11f62017-05-25 18:04:48 -070059#define MPIDR_MAX_AFFLVL U(2)
Achin Gupta4f6ad662013-10-25 09:08:21 +010060
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +000061#define MPID_MASK (MPIDR_MT_MASK | \
62 (MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT) | \
63 (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT) | \
64 (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) | \
65 (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT))
66
67#define MPIDR_AFF_ID(mpid, n) \
68 (((mpid) >> MPIDR_AFF_SHIFT(n)) & MPIDR_AFFLVL_MASK)
69
70/*
71 * An invalid MPID. This value can be used by functions that return an MPID to
72 * indicate an error.
73 */
74#define INVALID_MPID U(0xFFFFFFFF)
Achin Gupta4f6ad662013-10-25 09:08:21 +010075
76/*******************************************************************************
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010077 * Definitions for CPU system register interface to GICv3
78 ******************************************************************************/
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +000079#define ICC_IGRPEN1_EL1 S3_0_C12_C12_7
80#define ICC_SGI1R S3_0_C12_C11_5
81#define ICC_SRE_EL1 S3_0_C12_C12_5
82#define ICC_SRE_EL2 S3_4_C12_C9_5
83#define ICC_SRE_EL3 S3_6_C12_C12_5
84#define ICC_CTLR_EL1 S3_0_C12_C12_4
85#define ICC_CTLR_EL3 S3_6_C12_C12_4
86#define ICC_PMR_EL1 S3_0_C4_C6_0
87#define ICC_RPR_EL1 S3_0_C12_C11_3
88#define ICC_IGRPEN1_EL3 S3_6_c12_c12_7
89#define ICC_IGRPEN0_EL1 S3_0_c12_c12_6
90#define ICC_HPPIR0_EL1 S3_0_c12_c8_2
91#define ICC_HPPIR1_EL1 S3_0_c12_c12_2
92#define ICC_IAR0_EL1 S3_0_c12_c8_0
93#define ICC_IAR1_EL1 S3_0_c12_c12_0
94#define ICC_EOIR0_EL1 S3_0_c12_c8_1
95#define ICC_EOIR1_EL1 S3_0_c12_c12_1
96#define ICC_SGI0R_EL1 S3_0_c12_c11_7
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010097
98/*******************************************************************************
Achin Guptac2b43af2013-10-31 11:27:43 +000099 * Generic timer memory mapped registers & offsets
100 ******************************************************************************/
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700101#define CNTCR_OFF U(0x000)
102#define CNTFID_OFF U(0x020)
Achin Guptac2b43af2013-10-31 11:27:43 +0000103
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700104#define CNTCR_EN (U(1) << 0)
105#define CNTCR_HDBG (U(1) << 1)
Sandrine Bailleux3fa98472014-03-31 11:25:18 +0100106#define CNTCR_FCREQ(x) ((x) << 8)
Achin Guptac2b43af2013-10-31 11:27:43 +0000107
108/*******************************************************************************
Achin Gupta4f6ad662013-10-25 09:08:21 +0100109 * System register bit definitions
110 ******************************************************************************/
111/* CLIDR definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700112#define LOUIS_SHIFT U(21)
113#define LOC_SHIFT U(24)
114#define CLIDR_FIELD_WIDTH U(3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100115
116/* CSSELR definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700117#define LEVEL_SHIFT U(1)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100118
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100119/* Data cache set/way op type defines */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700120#define DCISW U(0x0)
121#define DCCISW U(0x1)
122#define DCCSW U(0x2)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100123
124/* ID_AA64PFR0_EL1 definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700125#define ID_AA64PFR0_EL0_SHIFT U(0)
126#define ID_AA64PFR0_EL1_SHIFT U(4)
127#define ID_AA64PFR0_EL2_SHIFT U(8)
128#define ID_AA64PFR0_EL3_SHIFT U(12)
Dimitris Papastamose08005a2017-10-12 13:02:29 +0100129#define ID_AA64PFR0_AMU_SHIFT U(44)
130#define ID_AA64PFR0_AMU_LENGTH U(4)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100131#define ID_AA64PFR0_AMU_MASK ULL(0xf)
132#define ID_AA64PFR0_ELX_MASK ULL(0xf)
David Cunadoce88eee2017-10-20 11:30:57 +0100133#define ID_AA64PFR0_SVE_SHIFT U(32)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100134#define ID_AA64PFR0_SVE_MASK ULL(0xf)
David Cunadoce88eee2017-10-20 11:30:57 +0100135#define ID_AA64PFR0_SVE_LENGTH U(4)
Jeenu Viswambharan2da918c2018-07-31 16:13:33 +0100136#define ID_AA64PFR0_MPAM_SHIFT U(40)
137#define ID_AA64PFR0_MPAM_MASK ULL(0xf)
Dimitris Papastamos43e05ec2018-01-02 15:53:01 +0000138#define ID_AA64PFR0_CSV2_SHIFT U(56)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100139#define ID_AA64PFR0_CSV2_MASK ULL(0xf)
Dimitris Papastamos43e05ec2018-01-02 15:53:01 +0000140#define ID_AA64PFR0_CSV2_LENGTH U(4)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100141
dp-armee3457b2017-05-23 09:32:49 +0100142/* ID_AA64DFR0_EL1.PMS definitions (for ARMv8.2+) */
143#define ID_AA64DFR0_PMS_SHIFT U(32)
144#define ID_AA64DFR0_PMS_LENGTH U(4)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100145#define ID_AA64DFR0_PMS_MASK ULL(0xf)
dp-armee3457b2017-05-23 09:32:49 +0100146
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100147#define EL_IMPL_NONE ULL(0)
148#define EL_IMPL_A64ONLY ULL(1)
149#define EL_IMPL_A64_A32 ULL(2)
Jeenu Viswambharan2a9b8822017-02-21 14:40:44 +0000150
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700151#define ID_AA64PFR0_GIC_SHIFT U(24)
152#define ID_AA64PFR0_GIC_WIDTH U(4)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100153#define ID_AA64PFR0_GIC_MASK ((ULL(1) << ID_AA64PFR0_GIC_WIDTH) - ULL(1))
Achin Gupta92712a52015-09-03 14:18:02 +0100154
Antonio Nino Diazd1beee22016-12-13 15:28:54 +0000155/* ID_AA64MMFR0_EL1 definitions */
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100156#define ID_AA64MMFR0_EL1_PARANGE_SHIFT U(0)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100157#define ID_AA64MMFR0_EL1_PARANGE_MASK ULL(0xf)
Antonio Nino Diazd1beee22016-12-13 15:28:54 +0000158
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000159/* ID_AA64ISAR1_EL1 definitions */
160#define ID_AA64ISAR1_GPI_SHIFT U(28)
161#define ID_AA64ISAR1_GPI_WIDTH U(4)
162#define ID_AA64ISAR1_GPA_SHIFT U(24)
163#define ID_AA64ISAR1_GPA_WIDTH U(4)
164#define ID_AA64ISAR1_API_SHIFT U(8)
165#define ID_AA64ISAR1_API_WIDTH U(4)
166#define ID_AA64ISAR1_APA_SHIFT U(4)
167#define ID_AA64ISAR1_APA_WIDTH U(4)
168
169#define ID_AA64ISAR1_GPI_MASK \
170 (((ULL(1) << ID_AA64ISAR1_GPI_WIDTH) - ULL(1)) << ID_AA64ISAR1_GPI_SHIFT)
171#define ID_AA64ISAR1_GPA_MASK \
172 (((ULL(1) << ID_AA64ISAR1_GPA_WIDTH) - ULL(1)) << ID_AA64ISAR1_GPA_SHIFT)
173#define ID_AA64ISAR1_API_MASK \
174 (((ULL(1) << ID_AA64ISAR1_API_WIDTH) - ULL(1)) << ID_AA64ISAR1_API_SHIFT)
175#define ID_AA64ISAR1_APA_MASK \
176 (((ULL(1) << ID_AA64ISAR1_APA_WIDTH) - ULL(1)) << ID_AA64ISAR1_APA_SHIFT)
177
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700178#define PARANGE_0000 U(32)
179#define PARANGE_0001 U(36)
180#define PARANGE_0010 U(40)
181#define PARANGE_0011 U(42)
182#define PARANGE_0100 U(44)
183#define PARANGE_0101 U(48)
Antonio Nino Diazb9ef6642017-11-17 09:52:53 +0000184#define PARANGE_0110 U(52)
Antonio Nino Diazd1beee22016-12-13 15:28:54 +0000185
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100186#define ID_AA64MMFR0_EL1_TGRAN4_SHIFT U(28)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100187#define ID_AA64MMFR0_EL1_TGRAN4_MASK ULL(0xf)
188#define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED ULL(0x0)
189#define ID_AA64MMFR0_EL1_TGRAN4_NOT_SUPPORTED ULL(0xf)
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100190
191#define ID_AA64MMFR0_EL1_TGRAN64_SHIFT U(24)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100192#define ID_AA64MMFR0_EL1_TGRAN64_MASK ULL(0xf)
193#define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED ULL(0x0)
194#define ID_AA64MMFR0_EL1_TGRAN64_NOT_SUPPORTED ULL(0xf)
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100195
196#define ID_AA64MMFR0_EL1_TGRAN16_SHIFT U(20)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100197#define ID_AA64MMFR0_EL1_TGRAN16_MASK ULL(0xf)
198#define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED ULL(0x1)
199#define ID_AA64MMFR0_EL1_TGRAN16_NOT_SUPPORTED ULL(0x0)
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100200
Jeenu Viswambharanaa00aff2018-11-15 11:38:03 +0000201/* ID_AA64PFR1_EL1 definitions */
202#define ID_AA64PFR1_EL1_SSBS_SHIFT U(4)
203#define ID_AA64PFR1_EL1_SSBS_MASK ULL(0xf)
204
205#define SSBS_UNAVAILABLE ULL(0) /* No architectural SSBS support */
206
Achin Gupta4f6ad662013-10-25 09:08:21 +0100207/* ID_PFR1_EL1 definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700208#define ID_PFR1_VIRTEXT_SHIFT U(12)
209#define ID_PFR1_VIRTEXT_MASK U(0xf)
Antonio Nino Diaz34235a32018-07-11 16:45:49 +0100210#define GET_VIRT_EXT(id) (((id) >> ID_PFR1_VIRTEXT_SHIFT) \
Achin Gupta4f6ad662013-10-25 09:08:21 +0100211 & ID_PFR1_VIRTEXT_MASK)
212
213/* SCTLR definitions */
David Cunadofee86532017-04-13 22:38:29 +0100214#define SCTLR_EL2_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700215 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \
216 (U(1) << 11) | (U(1) << 5) | (U(1) << 4))
Achin Gupta4f6ad662013-10-25 09:08:21 +0100217
David Cunadofee86532017-04-13 22:38:29 +0100218#define SCTLR_EL1_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700219 (U(1) << 22) | (U(1) << 20) | (U(1) << 11))
Jens Wiklanderc93c9df2014-09-04 10:23:27 +0200220#define SCTLR_AARCH32_EL1_RES1 \
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700221 ((U(1) << 23) | (U(1) << 22) | (U(1) << 11) | \
222 (U(1) << 4) | (U(1) << 3))
Jens Wiklanderc93c9df2014-09-04 10:23:27 +0200223
David Cunadofee86532017-04-13 22:38:29 +0100224#define SCTLR_EL3_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \
225 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \
226 (U(1) << 11) | (U(1) << 5) | (U(1) << 4))
227
Jeenu Viswambharanaa00aff2018-11-15 11:38:03 +0000228#define SCTLR_M_BIT (ULL(1) << 0)
229#define SCTLR_A_BIT (ULL(1) << 1)
230#define SCTLR_C_BIT (ULL(1) << 2)
231#define SCTLR_SA_BIT (ULL(1) << 3)
232#define SCTLR_SA0_BIT (ULL(1) << 4)
233#define SCTLR_CP15BEN_BIT (ULL(1) << 5)
234#define SCTLR_ITD_BIT (ULL(1) << 7)
235#define SCTLR_SED_BIT (ULL(1) << 8)
236#define SCTLR_UMA_BIT (ULL(1) << 9)
237#define SCTLR_I_BIT (ULL(1) << 12)
238#define SCTLR_V_BIT (ULL(1) << 13)
239#define SCTLR_DZE_BIT (ULL(1) << 14)
240#define SCTLR_UCT_BIT (ULL(1) << 15)
241#define SCTLR_NTWI_BIT (ULL(1) << 16)
242#define SCTLR_NTWE_BIT (ULL(1) << 18)
243#define SCTLR_WXN_BIT (ULL(1) << 19)
244#define SCTLR_UWXN_BIT (ULL(1) << 20)
245#define SCTLR_E0E_BIT (ULL(1) << 24)
246#define SCTLR_EE_BIT (ULL(1) << 25)
247#define SCTLR_UCI_BIT (ULL(1) << 26)
248#define SCTLR_TRE_BIT (ULL(1) << 28)
249#define SCTLR_AFE_BIT (ULL(1) << 29)
250#define SCTLR_TE_BIT (ULL(1) << 30)
251#define SCTLR_DSSBS_BIT (ULL(1) << 44)
David Cunadofee86532017-04-13 22:38:29 +0100252#define SCTLR_RESET_VAL SCTLR_EL3_RES1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100253
Achin Gupta4f6ad662013-10-25 09:08:21 +0100254/* CPACR_El1 definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700255#define CPACR_EL1_FPEN(x) ((x) << 20)
256#define CPACR_EL1_FP_TRAP_EL0 U(0x1)
257#define CPACR_EL1_FP_TRAP_ALL U(0x2)
258#define CPACR_EL1_FP_TRAP_NONE U(0x3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100259
260/* SCR definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700261#define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5))
Jeenu Viswambharanf00da742017-12-08 12:13:51 +0000262#define SCR_FIEN_BIT (U(1) << 21)
Jeenu Viswambharancbad6612018-08-15 14:29:29 +0100263#define SCR_API_BIT (U(1) << 17)
264#define SCR_APK_BIT (U(1) << 16)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700265#define SCR_TWE_BIT (U(1) << 13)
266#define SCR_TWI_BIT (U(1) << 12)
267#define SCR_ST_BIT (U(1) << 11)
268#define SCR_RW_BIT (U(1) << 10)
269#define SCR_SIF_BIT (U(1) << 9)
270#define SCR_HCE_BIT (U(1) << 8)
271#define SCR_SMD_BIT (U(1) << 7)
272#define SCR_EA_BIT (U(1) << 3)
273#define SCR_FIQ_BIT (U(1) << 2)
274#define SCR_IRQ_BIT (U(1) << 1)
275#define SCR_NS_BIT (U(1) << 0)
276#define SCR_VALID_BIT_MASK U(0x2f8f)
David Cunadofee86532017-04-13 22:38:29 +0100277#define SCR_RESET_VAL SCR_RES1_BITS
Achin Gupta4f6ad662013-10-25 09:08:21 +0100278
David Cunadofee86532017-04-13 22:38:29 +0100279/* MDCR_EL3 definitions */
dp-arm595d0d52017-02-08 11:51:50 +0000280#define MDCR_SPD32(x) ((x) << 14)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700281#define MDCR_SPD32_LEGACY U(0x0)
282#define MDCR_SPD32_DISABLE U(0x2)
283#define MDCR_SPD32_ENABLE U(0x3)
284#define MDCR_SDD_BIT (U(1) << 16)
dp-armee3457b2017-05-23 09:32:49 +0100285#define MDCR_NSPB(x) ((x) << 12)
286#define MDCR_NSPB_EL1 U(0x3)
David Cunadofee86532017-04-13 22:38:29 +0100287#define MDCR_TDOSA_BIT (U(1) << 10)
288#define MDCR_TDA_BIT (U(1) << 9)
289#define MDCR_TPM_BIT (U(1) << 6)
290#define MDCR_EL3_RESET_VAL U(0x0)
dp-arm595d0d52017-02-08 11:51:50 +0000291
David Cunadofee86532017-04-13 22:38:29 +0100292/* MDCR_EL2 definitions */
dp-armee3457b2017-05-23 09:32:49 +0100293#define MDCR_EL2_TPMS (U(1) << 14)
294#define MDCR_EL2_E2PB(x) ((x) << 12)
295#define MDCR_EL2_E2PB_EL1 U(0x3)
David Cunadofee86532017-04-13 22:38:29 +0100296#define MDCR_EL2_TDRA_BIT (U(1) << 11)
297#define MDCR_EL2_TDOSA_BIT (U(1) << 10)
298#define MDCR_EL2_TDA_BIT (U(1) << 9)
299#define MDCR_EL2_TDE_BIT (U(1) << 8)
300#define MDCR_EL2_HPME_BIT (U(1) << 7)
301#define MDCR_EL2_TPM_BIT (U(1) << 6)
302#define MDCR_EL2_TPMCR_BIT (U(1) << 5)
303#define MDCR_EL2_RESET_VAL U(0x0)
304
305/* HSTR_EL2 definitions */
306#define HSTR_EL2_RESET_VAL U(0x0)
307#define HSTR_EL2_T_MASK U(0xff)
308
309/* CNTHP_CTL_EL2 definitions */
310#define CNTHP_CTL_ENABLE_BIT (U(1) << 0)
311#define CNTHP_CTL_RESET_VAL U(0x0)
312
313/* VTTBR_EL2 definitions */
314#define VTTBR_RESET_VAL ULL(0x0)
315#define VTTBR_VMID_MASK ULL(0xff)
316#define VTTBR_VMID_SHIFT U(48)
317#define VTTBR_BADDR_MASK ULL(0xffffffffffff)
318#define VTTBR_BADDR_SHIFT U(0)
dp-arm595d0d52017-02-08 11:51:50 +0000319
Achin Gupta4f6ad662013-10-25 09:08:21 +0100320/* HCR definitions */
Jeenu Viswambharancbad6612018-08-15 14:29:29 +0100321#define HCR_API_BIT (ULL(1) << 41)
322#define HCR_APK_BIT (ULL(1) << 40)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000323#define HCR_TGE_BIT (ULL(1) << 27)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700324#define HCR_RW_SHIFT U(31)
325#define HCR_RW_BIT (ULL(1) << HCR_RW_SHIFT)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100326#define HCR_AMO_BIT (ULL(1) << 5)
327#define HCR_IMO_BIT (ULL(1) << 4)
328#define HCR_FMO_BIT (ULL(1) << 3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100329
Gerald Lejeune851dc7e2016-03-22 11:11:46 +0100330/* ISR definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700331#define ISR_A_SHIFT U(8)
332#define ISR_I_SHIFT U(7)
333#define ISR_F_SHIFT U(6)
Gerald Lejeune851dc7e2016-03-22 11:11:46 +0100334
Achin Gupta4f6ad662013-10-25 09:08:21 +0100335/* CNTHCTL_EL2 definitions */
David Cunadofee86532017-04-13 22:38:29 +0100336#define CNTHCTL_RESET_VAL U(0x0)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700337#define EVNTEN_BIT (U(1) << 2)
338#define EL1PCEN_BIT (U(1) << 1)
339#define EL1PCTEN_BIT (U(1) << 0)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100340
341/* CNTKCTL_EL1 definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700342#define EL0PTEN_BIT (U(1) << 9)
343#define EL0VTEN_BIT (U(1) << 8)
344#define EL0PCTEN_BIT (U(1) << 0)
345#define EL0VCTEN_BIT (U(1) << 1)
346#define EVNTEN_BIT (U(1) << 2)
347#define EVNTDIR_BIT (U(1) << 3)
348#define EVNTI_SHIFT U(4)
349#define EVNTI_MASK U(0xf)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100350
351/* CPTR_EL3 definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700352#define TCPAC_BIT (U(1) << 31)
Dimitris Papastamose08005a2017-10-12 13:02:29 +0100353#define TAM_BIT (U(1) << 30)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700354#define TTA_BIT (U(1) << 20)
355#define TFP_BIT (U(1) << 10)
David Cunadoce88eee2017-10-20 11:30:57 +0100356#define CPTR_EZ_BIT (U(1) << 8)
David Cunadofee86532017-04-13 22:38:29 +0100357#define CPTR_EL3_RESET_VAL U(0x0)
358
359/* CPTR_EL2 definitions */
360#define CPTR_EL2_RES1 ((U(1) << 13) | (U(1) << 12) | (U(0x3ff)))
361#define CPTR_EL2_TCPAC_BIT (U(1) << 31)
Dimitris Papastamose08005a2017-10-12 13:02:29 +0100362#define CPTR_EL2_TAM_BIT (U(1) << 30)
David Cunadofee86532017-04-13 22:38:29 +0100363#define CPTR_EL2_TTA_BIT (U(1) << 20)
364#define CPTR_EL2_TFP_BIT (U(1) << 10)
David Cunadoce88eee2017-10-20 11:30:57 +0100365#define CPTR_EL2_TZ_BIT (U(1) << 8)
David Cunadofee86532017-04-13 22:38:29 +0100366#define CPTR_EL2_RESET_VAL CPTR_EL2_RES1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100367
368/* CPSR/SPSR definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700369#define DAIF_FIQ_BIT (U(1) << 0)
370#define DAIF_IRQ_BIT (U(1) << 1)
371#define DAIF_ABT_BIT (U(1) << 2)
372#define DAIF_DBG_BIT (U(1) << 3)
373#define SPSR_DAIF_SHIFT U(6)
374#define SPSR_DAIF_MASK U(0xf)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100375
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700376#define SPSR_AIF_SHIFT U(6)
377#define SPSR_AIF_MASK U(0x7)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100378
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700379#define SPSR_E_SHIFT U(9)
380#define SPSR_E_MASK U(0x1)
381#define SPSR_E_LITTLE U(0x0)
382#define SPSR_E_BIG U(0x1)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100383
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700384#define SPSR_T_SHIFT U(5)
385#define SPSR_T_MASK U(0x1)
386#define SPSR_T_ARM U(0x0)
387#define SPSR_T_THUMB U(0x1)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100388
Dimitris Papastamosc52ebdc2017-12-18 13:46:21 +0000389#define SPSR_M_SHIFT U(4)
390#define SPSR_M_MASK U(0x1)
391#define SPSR_M_AARCH64 U(0x0)
392#define SPSR_M_AARCH32 U(0x1)
393
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100394#define DISABLE_ALL_EXCEPTIONS \
395 (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT)
396
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000397#define DISABLE_INTERRUPTS (DAIF_FIQ_BIT | DAIF_IRQ_BIT)
398
Yatharth Kocharede39cb2016-11-14 12:01:04 +0000399/*
400 * RMR_EL3 definitions
401 */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700402#define RMR_EL3_RR_BIT (U(1) << 1)
403#define RMR_EL3_AA64_BIT (U(1) << 0)
Yatharth Kocharede39cb2016-11-14 12:01:04 +0000404
405/*
406 * HI-VECTOR address for AArch32 state
407 */
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000408#define HI_VECTOR_BASE U(0xFFFF0000)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100409
410/*
411 * TCR defintions
412 */
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000413#define TCR_EL3_RES1 ((ULL(1) << 31) | (ULL(1) << 23))
Antonio Nino Diaz128de8d2018-08-07 19:59:49 +0100414#define TCR_EL2_RES1 ((ULL(1) << 31) | (ULL(1) << 23))
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700415#define TCR_EL1_IPS_SHIFT U(32)
Antonio Nino Diaz128de8d2018-08-07 19:59:49 +0100416#define TCR_EL2_PS_SHIFT U(16)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700417#define TCR_EL3_PS_SHIFT U(16)
Lin Ma741a3822014-06-27 16:56:30 -0700418
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100419#define TCR_TxSZ_MIN ULL(16)
420#define TCR_TxSZ_MAX ULL(39)
Antonio Nino Diazd48ae612016-08-02 09:21:41 +0100421
Lin Ma741a3822014-06-27 16:56:30 -0700422/* (internal) physical address size bits in EL3/EL1 */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100423#define TCR_PS_BITS_4GB ULL(0x0)
424#define TCR_PS_BITS_64GB ULL(0x1)
425#define TCR_PS_BITS_1TB ULL(0x2)
426#define TCR_PS_BITS_4TB ULL(0x3)
427#define TCR_PS_BITS_16TB ULL(0x4)
428#define TCR_PS_BITS_256TB ULL(0x5)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100429
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700430#define ADDR_MASK_48_TO_63 ULL(0xFFFF000000000000)
431#define ADDR_MASK_44_TO_47 ULL(0x0000F00000000000)
432#define ADDR_MASK_42_TO_43 ULL(0x00000C0000000000)
433#define ADDR_MASK_40_TO_41 ULL(0x0000030000000000)
434#define ADDR_MASK_36_TO_39 ULL(0x000000F000000000)
435#define ADDR_MASK_32_TO_35 ULL(0x0000000F00000000)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100436
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100437#define TCR_RGN_INNER_NC (ULL(0x0) << 8)
438#define TCR_RGN_INNER_WBA (ULL(0x1) << 8)
439#define TCR_RGN_INNER_WT (ULL(0x2) << 8)
440#define TCR_RGN_INNER_WBNA (ULL(0x3) << 8)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100441
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100442#define TCR_RGN_OUTER_NC (ULL(0x0) << 10)
443#define TCR_RGN_OUTER_WBA (ULL(0x1) << 10)
444#define TCR_RGN_OUTER_WT (ULL(0x2) << 10)
445#define TCR_RGN_OUTER_WBNA (ULL(0x3) << 10)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100446
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100447#define TCR_SH_NON_SHAREABLE (ULL(0x0) << 12)
448#define TCR_SH_OUTER_SHAREABLE (ULL(0x2) << 12)
449#define TCR_SH_INNER_SHAREABLE (ULL(0x3) << 12)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100450
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100451#define TCR_TG0_SHIFT U(14)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100452#define TCR_TG0_MASK ULL(3)
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100453#define TCR_TG0_4K (ULL(0) << TCR_TG0_SHIFT)
454#define TCR_TG0_64K (ULL(1) << TCR_TG0_SHIFT)
455#define TCR_TG0_16K (ULL(2) << TCR_TG0_SHIFT)
456
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100457#define TCR_EPD0_BIT (ULL(1) << 7)
458#define TCR_EPD1_BIT (ULL(1) << 23)
Antonio Nino Diazc8274a82017-09-15 10:30:34 +0100459
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700460#define MODE_SP_SHIFT U(0x0)
461#define MODE_SP_MASK U(0x1)
462#define MODE_SP_EL0 U(0x0)
463#define MODE_SP_ELX U(0x1)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100464
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700465#define MODE_RW_SHIFT U(0x4)
466#define MODE_RW_MASK U(0x1)
467#define MODE_RW_64 U(0x0)
468#define MODE_RW_32 U(0x1)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100469
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700470#define MODE_EL_SHIFT U(0x2)
471#define MODE_EL_MASK U(0x3)
472#define MODE_EL3 U(0x3)
473#define MODE_EL2 U(0x2)
474#define MODE_EL1 U(0x1)
475#define MODE_EL0 U(0x0)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100476
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700477#define MODE32_SHIFT U(0)
478#define MODE32_MASK U(0xf)
479#define MODE32_usr U(0x0)
480#define MODE32_fiq U(0x1)
481#define MODE32_irq U(0x2)
482#define MODE32_svc U(0x3)
483#define MODE32_mon U(0x6)
484#define MODE32_abt U(0x7)
485#define MODE32_hyp U(0xa)
486#define MODE32_und U(0xb)
487#define MODE32_sys U(0xf)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100488
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100489#define GET_RW(mode) (((mode) >> MODE_RW_SHIFT) & MODE_RW_MASK)
490#define GET_EL(mode) (((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK)
491#define GET_SP(mode) (((mode) >> MODE_SP_SHIFT) & MODE_SP_MASK)
492#define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100493
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100494#define SPSR_64(el, sp, daif) \
Antonio Nino Diaze8811472018-04-17 15:10:18 +0100495 ((MODE_RW_64 << MODE_RW_SHIFT) | \
496 (((el) & MODE_EL_MASK) << MODE_EL_SHIFT) | \
497 (((sp) & MODE_SP_MASK) << MODE_SP_SHIFT) | \
498 (((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT))
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100499
500#define SPSR_MODE32(mode, isa, endian, aif) \
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700501 ((MODE_RW_32 << MODE_RW_SHIFT) | \
502 (((mode) & MODE32_MASK) << MODE32_SHIFT) | \
503 (((isa) & SPSR_T_MASK) << SPSR_T_SHIFT) | \
504 (((endian) & SPSR_E_MASK) << SPSR_E_SHIFT) | \
505 (((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT))
Achin Gupta4f6ad662013-10-25 09:08:21 +0100506
Dan Handley0cdebbd2015-03-30 17:15:16 +0100507/*
Isla Mitchellc4a1a072017-08-07 11:20:13 +0100508 * TTBR Definitions
509 */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100510#define TTBR_CNP_BIT ULL(0x1)
Isla Mitchellc4a1a072017-08-07 11:20:13 +0100511
512/*
Dan Handley0cdebbd2015-03-30 17:15:16 +0100513 * CTR_EL0 definitions
514 */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700515#define CTR_CWG_SHIFT U(24)
516#define CTR_CWG_MASK U(0xf)
517#define CTR_ERG_SHIFT U(20)
518#define CTR_ERG_MASK U(0xf)
519#define CTR_DMINLINE_SHIFT U(16)
520#define CTR_DMINLINE_MASK U(0xf)
521#define CTR_L1IP_SHIFT U(14)
522#define CTR_L1IP_MASK U(0x3)
523#define CTR_IMINLINE_SHIFT U(0)
524#define CTR_IMINLINE_MASK U(0xf)
Dan Handley0cdebbd2015-03-30 17:15:16 +0100525
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700526#define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */
Achin Gupta4f6ad662013-10-25 09:08:21 +0100527
Achin Gupta405406d2014-05-09 12:00:17 +0100528/* Physical timer control register bit fields shifts and masks */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700529#define CNTP_CTL_ENABLE_SHIFT U(0)
530#define CNTP_CTL_IMASK_SHIFT U(1)
531#define CNTP_CTL_ISTATUS_SHIFT U(2)
Achin Gupta405406d2014-05-09 12:00:17 +0100532
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700533#define CNTP_CTL_ENABLE_MASK U(1)
534#define CNTP_CTL_IMASK_MASK U(1)
535#define CNTP_CTL_ISTATUS_MASK U(1)
Achin Gupta405406d2014-05-09 12:00:17 +0100536
Achin Gupta4f6ad662013-10-25 09:08:21 +0100537/* Exception Syndrome register bits and bobs */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700538#define ESR_EC_SHIFT U(26)
539#define ESR_EC_MASK U(0x3f)
540#define ESR_EC_LENGTH U(6)
541#define EC_UNKNOWN U(0x0)
542#define EC_WFE_WFI U(0x1)
543#define EC_AARCH32_CP15_MRC_MCR U(0x3)
544#define EC_AARCH32_CP15_MRRC_MCRR U(0x4)
545#define EC_AARCH32_CP14_MRC_MCR U(0x5)
546#define EC_AARCH32_CP14_LDC_STC U(0x6)
547#define EC_FP_SIMD U(0x7)
548#define EC_AARCH32_CP10_MRC U(0x8)
549#define EC_AARCH32_CP14_MRRC_MCRR U(0xc)
550#define EC_ILLEGAL U(0xe)
551#define EC_AARCH32_SVC U(0x11)
552#define EC_AARCH32_HVC U(0x12)
553#define EC_AARCH32_SMC U(0x13)
554#define EC_AARCH64_SVC U(0x15)
555#define EC_AARCH64_HVC U(0x16)
556#define EC_AARCH64_SMC U(0x17)
557#define EC_AARCH64_SYS U(0x18)
558#define EC_IABORT_LOWER_EL U(0x20)
559#define EC_IABORT_CUR_EL U(0x21)
560#define EC_PC_ALIGN U(0x22)
561#define EC_DABORT_LOWER_EL U(0x24)
562#define EC_DABORT_CUR_EL U(0x25)
563#define EC_SP_ALIGN U(0x26)
564#define EC_AARCH32_FP U(0x28)
565#define EC_AARCH64_FP U(0x2c)
566#define EC_SERROR U(0x2f)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100567
Jeenu Viswambharan96c7df02017-11-30 12:54:15 +0000568/*
569 * External Abort bit in Instruction and Data Aborts synchronous exception
570 * syndromes.
571 */
572#define ESR_ISS_EABORT_EA_BIT U(9)
573
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700574#define EC_BITS(x) (((x) >> ESR_EC_SHIFT) & ESR_EC_MASK)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100575
Vignesh Radhakrishnanb4a72942017-03-03 10:58:05 -0800576/* Reset bit inside the Reset management register for EL3 (RMR_EL3) */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700577#define RMR_RESET_REQUEST_SHIFT U(0x1)
578#define RMR_WARM_RESET_CPU (U(1) << RMR_RESET_REQUEST_SHIFT)
Vignesh Radhakrishnanb4a72942017-03-03 10:58:05 -0800579
Dan Handleyed6ff952014-05-14 17:44:19 +0100580/*******************************************************************************
Antonio Nino Diazac998032017-02-27 17:23:54 +0000581 * Definitions of register offsets, fields and macros for CPU system
582 * instructions.
583 ******************************************************************************/
584
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700585#define TLBI_ADDR_SHIFT U(12)
Antonio Nino Diazac998032017-02-27 17:23:54 +0000586#define TLBI_ADDR_MASK ULL(0x00000FFFFFFFFFFF)
587#define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK)
588
589/*******************************************************************************
Dan Handleyed6ff952014-05-14 17:44:19 +0100590 * Definitions of register offsets and fields in the CNTCTLBase Frame of the
591 * system level implementation of the Generic Timer.
592 ******************************************************************************/
Soby Mathew2d9f7952018-06-11 16:21:30 +0100593#define CNTCTLBASE_CNTFRQ U(0x0)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700594#define CNTNSAR U(0x4)
595#define CNTNSAR_NS_SHIFT(x) (x)
Dan Handleyed6ff952014-05-14 17:44:19 +0100596
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700597#define CNTACR_BASE(x) (U(0x40) + ((x) << 2))
598#define CNTACR_RPCT_SHIFT U(0x0)
599#define CNTACR_RVCT_SHIFT U(0x1)
600#define CNTACR_RFRQ_SHIFT U(0x2)
601#define CNTACR_RVOFF_SHIFT U(0x3)
602#define CNTACR_RWVT_SHIFT U(0x4)
603#define CNTACR_RWPT_SHIFT U(0x5)
Dan Handleyed6ff952014-05-14 17:44:19 +0100604
Soby Mathew2d9f7952018-06-11 16:21:30 +0100605/*******************************************************************************
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000606 * Definitions of register offsets and fields in the CNTBaseN Frame of the
Soby Mathew2d9f7952018-06-11 16:21:30 +0100607 * system level implementation of the Generic Timer.
608 ******************************************************************************/
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000609/* Physical Count register. */
610#define CNTPCT_LO U(0x0)
611/* Counter Frequency register. */
612#define CNTBASEN_CNTFRQ U(0x10)
613/* Physical Timer CompareValue register. */
614#define CNTP_CVAL_LO U(0x20)
615/* Physical Timer Control register. */
616#define CNTP_CTL U(0x2c)
Soby Mathew2d9f7952018-06-11 16:21:30 +0100617
David Cunado5f55e282016-10-31 17:37:34 +0000618/* PMCR_EL0 definitions */
David Cunado4168f2f2017-10-02 17:41:39 +0100619#define PMCR_EL0_RESET_VAL U(0x0)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700620#define PMCR_EL0_N_SHIFT U(11)
621#define PMCR_EL0_N_MASK U(0x1f)
David Cunado5f55e282016-10-31 17:37:34 +0000622#define PMCR_EL0_N_BITS (PMCR_EL0_N_MASK << PMCR_EL0_N_SHIFT)
David Cunado4168f2f2017-10-02 17:41:39 +0100623#define PMCR_EL0_LC_BIT (U(1) << 6)
624#define PMCR_EL0_DP_BIT (U(1) << 5)
625#define PMCR_EL0_X_BIT (U(1) << 4)
626#define PMCR_EL0_D_BIT (U(1) << 3)
David Cunado5f55e282016-10-31 17:37:34 +0000627
Isla Mitchell02c63072017-07-21 14:44:36 +0100628/*******************************************************************************
David Cunadoce88eee2017-10-20 11:30:57 +0100629 * Definitions for system register interface to SVE
630 ******************************************************************************/
631#define ZCR_EL3 S3_6_C1_C2_0
632#define ZCR_EL2 S3_4_C1_C2_0
633
634/* ZCR_EL3 definitions */
635#define ZCR_EL3_LEN_MASK U(0xf)
636
637/* ZCR_EL2 definitions */
638#define ZCR_EL2_LEN_MASK U(0xf)
639
640/*******************************************************************************
Isla Mitchell02c63072017-07-21 14:44:36 +0100641 * Definitions of MAIR encodings for device and normal memory
642 ******************************************************************************/
643/*
644 * MAIR encodings for device memory attributes.
645 */
646#define MAIR_DEV_nGnRnE ULL(0x0)
647#define MAIR_DEV_nGnRE ULL(0x4)
648#define MAIR_DEV_nGRE ULL(0x8)
649#define MAIR_DEV_GRE ULL(0xc)
650
651/*
652 * MAIR encodings for normal memory attributes.
653 *
654 * Cache Policy
655 * WT: Write Through
656 * WB: Write Back
657 * NC: Non-Cacheable
658 *
659 * Transient Hint
660 * NTR: Non-Transient
661 * TR: Transient
662 *
663 * Allocation Policy
664 * RA: Read Allocate
665 * WA: Write Allocate
666 * RWA: Read and Write Allocate
667 * NA: No Allocation
668 */
669#define MAIR_NORM_WT_TR_WA ULL(0x1)
670#define MAIR_NORM_WT_TR_RA ULL(0x2)
671#define MAIR_NORM_WT_TR_RWA ULL(0x3)
672#define MAIR_NORM_NC ULL(0x4)
673#define MAIR_NORM_WB_TR_WA ULL(0x5)
674#define MAIR_NORM_WB_TR_RA ULL(0x6)
675#define MAIR_NORM_WB_TR_RWA ULL(0x7)
676#define MAIR_NORM_WT_NTR_NA ULL(0x8)
677#define MAIR_NORM_WT_NTR_WA ULL(0x9)
678#define MAIR_NORM_WT_NTR_RA ULL(0xa)
679#define MAIR_NORM_WT_NTR_RWA ULL(0xb)
680#define MAIR_NORM_WB_NTR_NA ULL(0xc)
681#define MAIR_NORM_WB_NTR_WA ULL(0xd)
682#define MAIR_NORM_WB_NTR_RA ULL(0xe)
683#define MAIR_NORM_WB_NTR_RWA ULL(0xf)
684
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100685#define MAIR_NORM_OUTER_SHIFT U(4)
Isla Mitchell02c63072017-07-21 14:44:36 +0100686
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100687#define MAKE_MAIR_NORMAL_MEMORY(inner, outer) \
688 ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT))
Isla Mitchell02c63072017-07-21 14:44:36 +0100689
Jeenu Viswambharan1dc771b2017-10-19 09:15:15 +0100690/* PAR_EL1 fields */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100691#define PAR_F_SHIFT U(0)
692#define PAR_F_MASK ULL(0x1)
693#define PAR_ADDR_SHIFT U(12)
694#define PAR_ADDR_MASK (BIT(40) - ULL(1)) /* 40-bits-wide page address */
Jeenu Viswambharan1dc771b2017-10-19 09:15:15 +0100695
Dimitris Papastamos5bdbb472017-10-13 12:06:06 +0100696/*******************************************************************************
697 * Definitions for system register interface to SPE
698 ******************************************************************************/
699#define PMBLIMITR_EL1 S3_0_C9_C10_0
700
Dimitris Papastamose08005a2017-10-12 13:02:29 +0100701/*******************************************************************************
Jeenu Viswambharan2da918c2018-07-31 16:13:33 +0100702 * Definitions for system register interface to MPAM
703 ******************************************************************************/
704#define MPAMIDR_EL1 S3_0_C10_C4_4
705#define MPAM2_EL2 S3_4_C10_C5_0
706#define MPAMHCR_EL2 S3_4_C10_C4_0
707#define MPAM3_EL3 S3_6_C10_C5_0
708
709/*******************************************************************************
Dimitris Papastamose08005a2017-10-12 13:02:29 +0100710 * Definitions for system register interface to AMU for ARMv8.4 onwards
711 ******************************************************************************/
712#define AMCR_EL0 S3_3_C13_C2_0
713#define AMCFGR_EL0 S3_3_C13_C2_1
714#define AMCGCR_EL0 S3_3_C13_C2_2
715#define AMUSERENR_EL0 S3_3_C13_C2_3
716#define AMCNTENCLR0_EL0 S3_3_C13_C2_4
717#define AMCNTENSET0_EL0 S3_3_C13_C2_5
718#define AMCNTENCLR1_EL0 S3_3_C13_C3_0
719#define AMCNTENSET1_EL0 S3_3_C13_C3_1
720
721/* Activity Monitor Group 0 Event Counter Registers */
722#define AMEVCNTR00_EL0 S3_3_C13_C4_0
723#define AMEVCNTR01_EL0 S3_3_C13_C4_1
724#define AMEVCNTR02_EL0 S3_3_C13_C4_2
725#define AMEVCNTR03_EL0 S3_3_C13_C4_3
726
727/* Activity Monitor Group 0 Event Type Registers */
728#define AMEVTYPER00_EL0 S3_3_C13_C6_0
729#define AMEVTYPER01_EL0 S3_3_C13_C6_1
730#define AMEVTYPER02_EL0 S3_3_C13_C6_2
731#define AMEVTYPER03_EL0 S3_3_C13_C6_3
732
Dimitris Papastamos525c37a2017-11-13 09:49:45 +0000733/* Activity Monitor Group 1 Event Counter Registers */
734#define AMEVCNTR10_EL0 S3_3_C13_C12_0
735#define AMEVCNTR11_EL0 S3_3_C13_C12_1
736#define AMEVCNTR12_EL0 S3_3_C13_C12_2
737#define AMEVCNTR13_EL0 S3_3_C13_C12_3
738#define AMEVCNTR14_EL0 S3_3_C13_C12_4
739#define AMEVCNTR15_EL0 S3_3_C13_C12_5
740#define AMEVCNTR16_EL0 S3_3_C13_C12_6
741#define AMEVCNTR17_EL0 S3_3_C13_C12_7
742#define AMEVCNTR18_EL0 S3_3_C13_C13_0
743#define AMEVCNTR19_EL0 S3_3_C13_C13_1
744#define AMEVCNTR1A_EL0 S3_3_C13_C13_2
745#define AMEVCNTR1B_EL0 S3_3_C13_C13_3
746#define AMEVCNTR1C_EL0 S3_3_C13_C13_4
747#define AMEVCNTR1D_EL0 S3_3_C13_C13_5
748#define AMEVCNTR1E_EL0 S3_3_C13_C13_6
749#define AMEVCNTR1F_EL0 S3_3_C13_C13_7
750
751/* Activity Monitor Group 1 Event Type Registers */
752#define AMEVTYPER10_EL0 S3_3_C13_C14_0
753#define AMEVTYPER11_EL0 S3_3_C13_C14_1
754#define AMEVTYPER12_EL0 S3_3_C13_C14_2
755#define AMEVTYPER13_EL0 S3_3_C13_C14_3
756#define AMEVTYPER14_EL0 S3_3_C13_C14_4
757#define AMEVTYPER15_EL0 S3_3_C13_C14_5
758#define AMEVTYPER16_EL0 S3_3_C13_C14_6
759#define AMEVTYPER17_EL0 S3_3_C13_C14_7
760#define AMEVTYPER18_EL0 S3_3_C13_C15_0
761#define AMEVTYPER19_EL0 S3_3_C13_C15_1
762#define AMEVTYPER1A_EL0 S3_3_C13_C15_2
763#define AMEVTYPER1B_EL0 S3_3_C13_C15_3
764#define AMEVTYPER1C_EL0 S3_3_C13_C15_4
765#define AMEVTYPER1D_EL0 S3_3_C13_C15_5
766#define AMEVTYPER1E_EL0 S3_3_C13_C15_6
767#define AMEVTYPER1F_EL0 S3_3_C13_C15_7
768
769/* AMCGCR_EL0 definitions */
770#define AMCGCR_EL0_CG1NC_SHIFT U(8)
771#define AMCGCR_EL0_CG1NC_LENGTH U(8)
772#define AMCGCR_EL0_CG1NC_MASK U(0xff)
773
Jeenu Viswambharan2da918c2018-07-31 16:13:33 +0100774/* MPAM register definitions */
775#define MPAM3_EL3_MPAMEN_BIT (ULL(1) << 63)
776
777#define MPAMIDR_HAS_HCR_BIT (ULL(1) << 17)
778
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100779/*******************************************************************************
780 * RAS system registers
781 *******************************************************************************/
782#define DISR_EL1 S3_0_C12_C1_1
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100783#define DISR_A_BIT U(31)
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100784
Jeenu Viswambharan19f6cf22017-12-07 08:43:05 +0000785#define ERRIDR_EL1 S3_0_C5_C3_0
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100786#define ERRIDR_MASK U(0xffff)
Jeenu Viswambharan19f6cf22017-12-07 08:43:05 +0000787
788#define ERRSELR_EL1 S3_0_C5_C3_1
789
790/* System register access to Standard Error Record registers */
791#define ERXFR_EL1 S3_0_C5_C4_0
792#define ERXCTLR_EL1 S3_0_C5_C4_1
793#define ERXSTATUS_EL1 S3_0_C5_C4_2
794#define ERXADDR_EL1 S3_0_C5_C4_3
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000795#define ERXPFGF_EL1 S3_0_C5_C4_4
796#define ERXPFGCTL_EL1 S3_0_C5_C4_5
797#define ERXPFGCDN_EL1 S3_0_C5_C4_6
Jan Dabros82ef8bf2018-08-30 13:52:23 +0200798#define ERXMISC0_EL1 S3_0_C5_C5_0
799#define ERXMISC1_EL1 S3_0_C5_C5_1
Jeenu Viswambharan19f6cf22017-12-07 08:43:05 +0000800
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000801#define ERXCTLR_ED_BIT (U(1) << 0)
802#define ERXCTLR_UE_BIT (U(1) << 4)
803
804#define ERXPFGCTL_UC_BIT (U(1) << 1)
805#define ERXPFGCTL_UEU_BIT (U(1) << 2)
806#define ERXPFGCTL_CDEN_BIT (U(1) << 31)
807
808/*******************************************************************************
809 * Armv8.3 Pointer Authentication Registers
810 *******************************************************************************/
811#define APGAKeyLo_EL1 S3_0_C2_C3_0
812
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +0100813#endif /* ARCH_H */