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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Jeenu Viswambharan96c7df02017-11-30 12:54:15 +00002 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +01007#ifndef ARCH_H
8#define ARCH_H
Achin Gupta4f6ad662013-10-25 09:08:21 +01009
Scott Brandenbf404c02017-04-10 11:45:52 -070010#include <utils_def.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010011
12/*******************************************************************************
13 * MIDR bit definitions
14 ******************************************************************************/
Varun Wadekarc6a11f62017-05-25 18:04:48 -070015#define MIDR_IMPL_MASK U(0xff)
16#define MIDR_IMPL_SHIFT U(0x18)
17#define MIDR_VAR_SHIFT U(20)
18#define MIDR_VAR_BITS U(4)
19#define MIDR_VAR_MASK U(0xf)
20#define MIDR_REV_SHIFT U(0)
21#define MIDR_REV_BITS U(4)
22#define MIDR_REV_MASK U(0xf)
23#define MIDR_PN_MASK U(0xfff)
24#define MIDR_PN_SHIFT U(0x4)
Achin Gupta4f6ad662013-10-25 09:08:21 +010025
26/*******************************************************************************
27 * MPIDR macros
28 ******************************************************************************/
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010029#define MPIDR_MT_MASK (ULL(1) << 24)
Achin Gupta4f6ad662013-10-25 09:08:21 +010030#define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK
Varun Wadekarc6a11f62017-05-25 18:04:48 -070031#define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS)
32#define MPIDR_AFFINITY_BITS U(8)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010033#define MPIDR_AFFLVL_MASK ULL(0xff)
Varun Wadekarc6a11f62017-05-25 18:04:48 -070034#define MPIDR_AFF0_SHIFT U(0)
35#define MPIDR_AFF1_SHIFT U(8)
36#define MPIDR_AFF2_SHIFT U(16)
37#define MPIDR_AFF3_SHIFT U(32)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010038#define MPIDR_AFFINITY_MASK ULL(0xff00ffffff)
Varun Wadekarc6a11f62017-05-25 18:04:48 -070039#define MPIDR_AFFLVL_SHIFT U(3)
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +010040#define MPIDR_AFFLVL0 U(0x0)
41#define MPIDR_AFFLVL1 U(0x1)
42#define MPIDR_AFFLVL2 U(0x2)
43#define MPIDR_AFFLVL3 U(0x3)
Vikram Kanigiri4e97e542015-02-26 15:25:58 +000044#define MPIDR_AFFLVL0_VAL(mpidr) \
Antonio Nino Diaz34235a32018-07-11 16:45:49 +010045 (((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK)
Vikram Kanigiri4e97e542015-02-26 15:25:58 +000046#define MPIDR_AFFLVL1_VAL(mpidr) \
Antonio Nino Diaz34235a32018-07-11 16:45:49 +010047 (((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK)
Vikram Kanigiri4e97e542015-02-26 15:25:58 +000048#define MPIDR_AFFLVL2_VAL(mpidr) \
Antonio Nino Diaz34235a32018-07-11 16:45:49 +010049 (((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK)
Vikram Kanigiri4e97e542015-02-26 15:25:58 +000050#define MPIDR_AFFLVL3_VAL(mpidr) \
Antonio Nino Diaz34235a32018-07-11 16:45:49 +010051 (((mpidr) >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK)
Soby Mathewe2b2d8f2014-12-04 14:14:12 +000052/*
53 * The MPIDR_MAX_AFFLVL count starts from 0. Take care to
54 * add one while using this macro to define array sizes.
55 * TODO: Support only the first 3 affinity levels for now.
56 */
Varun Wadekarc6a11f62017-05-25 18:04:48 -070057#define MPIDR_MAX_AFFLVL U(2)
Achin Gupta4f6ad662013-10-25 09:08:21 +010058
59/* Constant to highlight the assumption that MPIDR allocation starts from 0 */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010060#define FIRST_MPIDR ULL(0)
Achin Gupta4f6ad662013-10-25 09:08:21 +010061
62/*******************************************************************************
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010063 * Definitions for CPU system register interface to GICv3
64 ******************************************************************************/
65#define ICC_SRE_EL1 S3_0_C12_C12_5
66#define ICC_SRE_EL2 S3_4_C12_C9_5
67#define ICC_SRE_EL3 S3_6_C12_C12_5
68#define ICC_CTLR_EL1 S3_0_C12_C12_4
69#define ICC_CTLR_EL3 S3_6_C12_C12_4
70#define ICC_PMR_EL1 S3_0_C4_C6_0
Jeenu Viswambharanb1e957e2017-09-22 08:32:09 +010071#define ICC_RPR_EL1 S3_0_C12_C11_3
Achin Gupta92712a52015-09-03 14:18:02 +010072#define ICC_IGRPEN1_EL3 S3_6_c12_c12_7
73#define ICC_IGRPEN0_EL1 S3_0_c12_c12_6
74#define ICC_HPPIR0_EL1 S3_0_c12_c8_2
75#define ICC_HPPIR1_EL1 S3_0_c12_c12_2
76#define ICC_IAR0_EL1 S3_0_c12_c8_0
77#define ICC_IAR1_EL1 S3_0_c12_c12_0
78#define ICC_EOIR0_EL1 S3_0_c12_c8_1
79#define ICC_EOIR1_EL1 S3_0_c12_c12_1
Jeenu Viswambharanab14e9b2017-09-22 08:32:09 +010080#define ICC_SGI0R_EL1 S3_0_c12_c11_7
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010081
82/*******************************************************************************
Achin Guptac2b43af2013-10-31 11:27:43 +000083 * Generic timer memory mapped registers & offsets
84 ******************************************************************************/
Varun Wadekarc6a11f62017-05-25 18:04:48 -070085#define CNTCR_OFF U(0x000)
86#define CNTFID_OFF U(0x020)
Achin Guptac2b43af2013-10-31 11:27:43 +000087
Varun Wadekarc6a11f62017-05-25 18:04:48 -070088#define CNTCR_EN (U(1) << 0)
89#define CNTCR_HDBG (U(1) << 1)
Sandrine Bailleux3fa98472014-03-31 11:25:18 +010090#define CNTCR_FCREQ(x) ((x) << 8)
Achin Guptac2b43af2013-10-31 11:27:43 +000091
92/*******************************************************************************
Achin Gupta4f6ad662013-10-25 09:08:21 +010093 * System register bit definitions
94 ******************************************************************************/
95/* CLIDR definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -070096#define LOUIS_SHIFT U(21)
97#define LOC_SHIFT U(24)
98#define CLIDR_FIELD_WIDTH U(3)
Achin Gupta4f6ad662013-10-25 09:08:21 +010099
100/* CSSELR definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700101#define LEVEL_SHIFT U(1)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100102
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100103/* Data cache set/way op type defines */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700104#define DCISW U(0x0)
105#define DCCISW U(0x1)
106#define DCCSW U(0x2)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100107
108/* ID_AA64PFR0_EL1 definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700109#define ID_AA64PFR0_EL0_SHIFT U(0)
110#define ID_AA64PFR0_EL1_SHIFT U(4)
111#define ID_AA64PFR0_EL2_SHIFT U(8)
112#define ID_AA64PFR0_EL3_SHIFT U(12)
Dimitris Papastamose08005a2017-10-12 13:02:29 +0100113#define ID_AA64PFR0_AMU_SHIFT U(44)
114#define ID_AA64PFR0_AMU_LENGTH U(4)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100115#define ID_AA64PFR0_AMU_MASK ULL(0xf)
116#define ID_AA64PFR0_ELX_MASK ULL(0xf)
David Cunadoce88eee2017-10-20 11:30:57 +0100117#define ID_AA64PFR0_SVE_SHIFT U(32)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100118#define ID_AA64PFR0_SVE_MASK ULL(0xf)
David Cunadoce88eee2017-10-20 11:30:57 +0100119#define ID_AA64PFR0_SVE_LENGTH U(4)
Jeenu Viswambharan2da918c2018-07-31 16:13:33 +0100120#define ID_AA64PFR0_MPAM_SHIFT U(40)
121#define ID_AA64PFR0_MPAM_MASK ULL(0xf)
Dimitris Papastamos43e05ec2018-01-02 15:53:01 +0000122#define ID_AA64PFR0_CSV2_SHIFT U(56)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100123#define ID_AA64PFR0_CSV2_MASK ULL(0xf)
Dimitris Papastamos43e05ec2018-01-02 15:53:01 +0000124#define ID_AA64PFR0_CSV2_LENGTH U(4)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100125
dp-armee3457b2017-05-23 09:32:49 +0100126/* ID_AA64DFR0_EL1.PMS definitions (for ARMv8.2+) */
127#define ID_AA64DFR0_PMS_SHIFT U(32)
128#define ID_AA64DFR0_PMS_LENGTH U(4)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100129#define ID_AA64DFR0_PMS_MASK ULL(0xf)
dp-armee3457b2017-05-23 09:32:49 +0100130
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100131#define EL_IMPL_NONE ULL(0)
132#define EL_IMPL_A64ONLY ULL(1)
133#define EL_IMPL_A64_A32 ULL(2)
Jeenu Viswambharan2a9b8822017-02-21 14:40:44 +0000134
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700135#define ID_AA64PFR0_GIC_SHIFT U(24)
136#define ID_AA64PFR0_GIC_WIDTH U(4)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100137#define ID_AA64PFR0_GIC_MASK ((ULL(1) << ID_AA64PFR0_GIC_WIDTH) - ULL(1))
Achin Gupta92712a52015-09-03 14:18:02 +0100138
Antonio Nino Diazd1beee22016-12-13 15:28:54 +0000139/* ID_AA64MMFR0_EL1 definitions */
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100140#define ID_AA64MMFR0_EL1_PARANGE_SHIFT U(0)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100141#define ID_AA64MMFR0_EL1_PARANGE_MASK ULL(0xf)
Antonio Nino Diazd1beee22016-12-13 15:28:54 +0000142
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700143#define PARANGE_0000 U(32)
144#define PARANGE_0001 U(36)
145#define PARANGE_0010 U(40)
146#define PARANGE_0011 U(42)
147#define PARANGE_0100 U(44)
148#define PARANGE_0101 U(48)
Antonio Nino Diazb9ef6642017-11-17 09:52:53 +0000149#define PARANGE_0110 U(52)
Antonio Nino Diazd1beee22016-12-13 15:28:54 +0000150
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100151#define ID_AA64MMFR0_EL1_TGRAN4_SHIFT U(28)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100152#define ID_AA64MMFR0_EL1_TGRAN4_MASK ULL(0xf)
153#define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED ULL(0x0)
154#define ID_AA64MMFR0_EL1_TGRAN4_NOT_SUPPORTED ULL(0xf)
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100155
156#define ID_AA64MMFR0_EL1_TGRAN64_SHIFT U(24)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100157#define ID_AA64MMFR0_EL1_TGRAN64_MASK ULL(0xf)
158#define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED ULL(0x0)
159#define ID_AA64MMFR0_EL1_TGRAN64_NOT_SUPPORTED ULL(0xf)
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100160
161#define ID_AA64MMFR0_EL1_TGRAN16_SHIFT U(20)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100162#define ID_AA64MMFR0_EL1_TGRAN16_MASK ULL(0xf)
163#define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED ULL(0x1)
164#define ID_AA64MMFR0_EL1_TGRAN16_NOT_SUPPORTED ULL(0x0)
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100165
Achin Gupta4f6ad662013-10-25 09:08:21 +0100166/* ID_PFR1_EL1 definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700167#define ID_PFR1_VIRTEXT_SHIFT U(12)
168#define ID_PFR1_VIRTEXT_MASK U(0xf)
Antonio Nino Diaz34235a32018-07-11 16:45:49 +0100169#define GET_VIRT_EXT(id) (((id) >> ID_PFR1_VIRTEXT_SHIFT) \
Achin Gupta4f6ad662013-10-25 09:08:21 +0100170 & ID_PFR1_VIRTEXT_MASK)
171
172/* SCTLR definitions */
David Cunadofee86532017-04-13 22:38:29 +0100173#define SCTLR_EL2_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700174 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \
175 (U(1) << 11) | (U(1) << 5) | (U(1) << 4))
Achin Gupta4f6ad662013-10-25 09:08:21 +0100176
David Cunadofee86532017-04-13 22:38:29 +0100177#define SCTLR_EL1_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700178 (U(1) << 22) | (U(1) << 20) | (U(1) << 11))
Jens Wiklanderc93c9df2014-09-04 10:23:27 +0200179#define SCTLR_AARCH32_EL1_RES1 \
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700180 ((U(1) << 23) | (U(1) << 22) | (U(1) << 11) | \
181 (U(1) << 4) | (U(1) << 3))
Jens Wiklanderc93c9df2014-09-04 10:23:27 +0200182
David Cunadofee86532017-04-13 22:38:29 +0100183#define SCTLR_EL3_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \
184 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \
185 (U(1) << 11) | (U(1) << 5) | (U(1) << 4))
186
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700187#define SCTLR_M_BIT (U(1) << 0)
188#define SCTLR_A_BIT (U(1) << 1)
189#define SCTLR_C_BIT (U(1) << 2)
190#define SCTLR_SA_BIT (U(1) << 3)
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100191#define SCTLR_SA0_BIT (U(1) << 4)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700192#define SCTLR_CP15BEN_BIT (U(1) << 5)
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100193#define SCTLR_ITD_BIT (U(1) << 7)
194#define SCTLR_SED_BIT (U(1) << 8)
195#define SCTLR_UMA_BIT (U(1) << 9)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700196#define SCTLR_I_BIT (U(1) << 12)
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100197#define SCTLR_V_BIT (U(1) << 13)
198#define SCTLR_DZE_BIT (U(1) << 14)
199#define SCTLR_UCT_BIT (U(1) << 15)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700200#define SCTLR_NTWI_BIT (U(1) << 16)
201#define SCTLR_NTWE_BIT (U(1) << 18)
202#define SCTLR_WXN_BIT (U(1) << 19)
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100203#define SCTLR_UWXN_BIT (U(1) << 20)
204#define SCTLR_E0E_BIT (U(1) << 24)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700205#define SCTLR_EE_BIT (U(1) << 25)
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100206#define SCTLR_UCI_BIT (U(1) << 26)
207#define SCTLR_TRE_BIT (U(1) << 28)
208#define SCTLR_AFE_BIT (U(1) << 29)
209#define SCTLR_TE_BIT (U(1) << 30)
David Cunadofee86532017-04-13 22:38:29 +0100210#define SCTLR_RESET_VAL SCTLR_EL3_RES1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100211
Achin Gupta4f6ad662013-10-25 09:08:21 +0100212/* CPACR_El1 definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700213#define CPACR_EL1_FPEN(x) ((x) << 20)
214#define CPACR_EL1_FP_TRAP_EL0 U(0x1)
215#define CPACR_EL1_FP_TRAP_ALL U(0x2)
216#define CPACR_EL1_FP_TRAP_NONE U(0x3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100217
218/* SCR definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700219#define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5))
Jeenu Viswambharanf00da742017-12-08 12:13:51 +0000220#define SCR_FIEN_BIT (U(1) << 21)
Jeenu Viswambharancbad6612018-08-15 14:29:29 +0100221#define SCR_API_BIT (U(1) << 17)
222#define SCR_APK_BIT (U(1) << 16)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700223#define SCR_TWE_BIT (U(1) << 13)
224#define SCR_TWI_BIT (U(1) << 12)
225#define SCR_ST_BIT (U(1) << 11)
226#define SCR_RW_BIT (U(1) << 10)
227#define SCR_SIF_BIT (U(1) << 9)
228#define SCR_HCE_BIT (U(1) << 8)
229#define SCR_SMD_BIT (U(1) << 7)
230#define SCR_EA_BIT (U(1) << 3)
231#define SCR_FIQ_BIT (U(1) << 2)
232#define SCR_IRQ_BIT (U(1) << 1)
233#define SCR_NS_BIT (U(1) << 0)
234#define SCR_VALID_BIT_MASK U(0x2f8f)
David Cunadofee86532017-04-13 22:38:29 +0100235#define SCR_RESET_VAL SCR_RES1_BITS
Achin Gupta4f6ad662013-10-25 09:08:21 +0100236
David Cunadofee86532017-04-13 22:38:29 +0100237/* MDCR_EL3 definitions */
dp-arm595d0d52017-02-08 11:51:50 +0000238#define MDCR_SPD32(x) ((x) << 14)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700239#define MDCR_SPD32_LEGACY U(0x0)
240#define MDCR_SPD32_DISABLE U(0x2)
241#define MDCR_SPD32_ENABLE U(0x3)
242#define MDCR_SDD_BIT (U(1) << 16)
dp-armee3457b2017-05-23 09:32:49 +0100243#define MDCR_NSPB(x) ((x) << 12)
244#define MDCR_NSPB_EL1 U(0x3)
David Cunadofee86532017-04-13 22:38:29 +0100245#define MDCR_TDOSA_BIT (U(1) << 10)
246#define MDCR_TDA_BIT (U(1) << 9)
247#define MDCR_TPM_BIT (U(1) << 6)
248#define MDCR_EL3_RESET_VAL U(0x0)
dp-arm595d0d52017-02-08 11:51:50 +0000249
David Cunadofee86532017-04-13 22:38:29 +0100250/* MDCR_EL2 definitions */
dp-armee3457b2017-05-23 09:32:49 +0100251#define MDCR_EL2_TPMS (U(1) << 14)
252#define MDCR_EL2_E2PB(x) ((x) << 12)
253#define MDCR_EL2_E2PB_EL1 U(0x3)
David Cunadofee86532017-04-13 22:38:29 +0100254#define MDCR_EL2_TDRA_BIT (U(1) << 11)
255#define MDCR_EL2_TDOSA_BIT (U(1) << 10)
256#define MDCR_EL2_TDA_BIT (U(1) << 9)
257#define MDCR_EL2_TDE_BIT (U(1) << 8)
258#define MDCR_EL2_HPME_BIT (U(1) << 7)
259#define MDCR_EL2_TPM_BIT (U(1) << 6)
260#define MDCR_EL2_TPMCR_BIT (U(1) << 5)
261#define MDCR_EL2_RESET_VAL U(0x0)
262
263/* HSTR_EL2 definitions */
264#define HSTR_EL2_RESET_VAL U(0x0)
265#define HSTR_EL2_T_MASK U(0xff)
266
267/* CNTHP_CTL_EL2 definitions */
268#define CNTHP_CTL_ENABLE_BIT (U(1) << 0)
269#define CNTHP_CTL_RESET_VAL U(0x0)
270
271/* VTTBR_EL2 definitions */
272#define VTTBR_RESET_VAL ULL(0x0)
273#define VTTBR_VMID_MASK ULL(0xff)
274#define VTTBR_VMID_SHIFT U(48)
275#define VTTBR_BADDR_MASK ULL(0xffffffffffff)
276#define VTTBR_BADDR_SHIFT U(0)
dp-arm595d0d52017-02-08 11:51:50 +0000277
Achin Gupta4f6ad662013-10-25 09:08:21 +0100278/* HCR definitions */
Jeenu Viswambharancbad6612018-08-15 14:29:29 +0100279#define HCR_API_BIT (ULL(1) << 41)
280#define HCR_APK_BIT (ULL(1) << 40)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700281#define HCR_RW_SHIFT U(31)
282#define HCR_RW_BIT (ULL(1) << HCR_RW_SHIFT)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100283#define HCR_AMO_BIT (ULL(1) << 5)
284#define HCR_IMO_BIT (ULL(1) << 4)
285#define HCR_FMO_BIT (ULL(1) << 3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100286
Gerald Lejeune851dc7e2016-03-22 11:11:46 +0100287/* ISR definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700288#define ISR_A_SHIFT U(8)
289#define ISR_I_SHIFT U(7)
290#define ISR_F_SHIFT U(6)
Gerald Lejeune851dc7e2016-03-22 11:11:46 +0100291
Achin Gupta4f6ad662013-10-25 09:08:21 +0100292/* CNTHCTL_EL2 definitions */
David Cunadofee86532017-04-13 22:38:29 +0100293#define CNTHCTL_RESET_VAL U(0x0)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700294#define EVNTEN_BIT (U(1) << 2)
295#define EL1PCEN_BIT (U(1) << 1)
296#define EL1PCTEN_BIT (U(1) << 0)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100297
298/* CNTKCTL_EL1 definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700299#define EL0PTEN_BIT (U(1) << 9)
300#define EL0VTEN_BIT (U(1) << 8)
301#define EL0PCTEN_BIT (U(1) << 0)
302#define EL0VCTEN_BIT (U(1) << 1)
303#define EVNTEN_BIT (U(1) << 2)
304#define EVNTDIR_BIT (U(1) << 3)
305#define EVNTI_SHIFT U(4)
306#define EVNTI_MASK U(0xf)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100307
308/* CPTR_EL3 definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700309#define TCPAC_BIT (U(1) << 31)
Dimitris Papastamose08005a2017-10-12 13:02:29 +0100310#define TAM_BIT (U(1) << 30)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700311#define TTA_BIT (U(1) << 20)
312#define TFP_BIT (U(1) << 10)
David Cunadoce88eee2017-10-20 11:30:57 +0100313#define CPTR_EZ_BIT (U(1) << 8)
David Cunadofee86532017-04-13 22:38:29 +0100314#define CPTR_EL3_RESET_VAL U(0x0)
315
316/* CPTR_EL2 definitions */
317#define CPTR_EL2_RES1 ((U(1) << 13) | (U(1) << 12) | (U(0x3ff)))
318#define CPTR_EL2_TCPAC_BIT (U(1) << 31)
Dimitris Papastamose08005a2017-10-12 13:02:29 +0100319#define CPTR_EL2_TAM_BIT (U(1) << 30)
David Cunadofee86532017-04-13 22:38:29 +0100320#define CPTR_EL2_TTA_BIT (U(1) << 20)
321#define CPTR_EL2_TFP_BIT (U(1) << 10)
David Cunadoce88eee2017-10-20 11:30:57 +0100322#define CPTR_EL2_TZ_BIT (U(1) << 8)
David Cunadofee86532017-04-13 22:38:29 +0100323#define CPTR_EL2_RESET_VAL CPTR_EL2_RES1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100324
325/* CPSR/SPSR definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700326#define DAIF_FIQ_BIT (U(1) << 0)
327#define DAIF_IRQ_BIT (U(1) << 1)
328#define DAIF_ABT_BIT (U(1) << 2)
329#define DAIF_DBG_BIT (U(1) << 3)
330#define SPSR_DAIF_SHIFT U(6)
331#define SPSR_DAIF_MASK U(0xf)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100332
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700333#define SPSR_AIF_SHIFT U(6)
334#define SPSR_AIF_MASK U(0x7)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100335
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700336#define SPSR_E_SHIFT U(9)
337#define SPSR_E_MASK U(0x1)
338#define SPSR_E_LITTLE U(0x0)
339#define SPSR_E_BIG U(0x1)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100340
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700341#define SPSR_T_SHIFT U(5)
342#define SPSR_T_MASK U(0x1)
343#define SPSR_T_ARM U(0x0)
344#define SPSR_T_THUMB U(0x1)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100345
Dimitris Papastamosc52ebdc2017-12-18 13:46:21 +0000346#define SPSR_M_SHIFT U(4)
347#define SPSR_M_MASK U(0x1)
348#define SPSR_M_AARCH64 U(0x0)
349#define SPSR_M_AARCH32 U(0x1)
350
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100351#define DISABLE_ALL_EXCEPTIONS \
352 (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT)
353
Yatharth Kocharede39cb2016-11-14 12:01:04 +0000354/*
355 * RMR_EL3 definitions
356 */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700357#define RMR_EL3_RR_BIT (U(1) << 1)
358#define RMR_EL3_AA64_BIT (U(1) << 0)
Yatharth Kocharede39cb2016-11-14 12:01:04 +0000359
360/*
361 * HI-VECTOR address for AArch32 state
362 */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700363#define HI_VECTOR_BASE U(0xFFFF0000)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100364
365/*
366 * TCR defintions
367 */
Antonio Nino Diazf94e40d2017-09-14 15:57:44 +0100368#define TCR_EL3_RES1 ((U(1) << 31) | (U(1) << 23))
Antonio Nino Diaz128de8d2018-08-07 19:59:49 +0100369#define TCR_EL2_RES1 ((ULL(1) << 31) | (ULL(1) << 23))
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700370#define TCR_EL1_IPS_SHIFT U(32)
Antonio Nino Diaz128de8d2018-08-07 19:59:49 +0100371#define TCR_EL2_PS_SHIFT U(16)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700372#define TCR_EL3_PS_SHIFT U(16)
Lin Ma741a3822014-06-27 16:56:30 -0700373
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100374#define TCR_TxSZ_MIN ULL(16)
375#define TCR_TxSZ_MAX ULL(39)
Antonio Nino Diazd48ae612016-08-02 09:21:41 +0100376
Lin Ma741a3822014-06-27 16:56:30 -0700377/* (internal) physical address size bits in EL3/EL1 */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100378#define TCR_PS_BITS_4GB ULL(0x0)
379#define TCR_PS_BITS_64GB ULL(0x1)
380#define TCR_PS_BITS_1TB ULL(0x2)
381#define TCR_PS_BITS_4TB ULL(0x3)
382#define TCR_PS_BITS_16TB ULL(0x4)
383#define TCR_PS_BITS_256TB ULL(0x5)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100384
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700385#define ADDR_MASK_48_TO_63 ULL(0xFFFF000000000000)
386#define ADDR_MASK_44_TO_47 ULL(0x0000F00000000000)
387#define ADDR_MASK_42_TO_43 ULL(0x00000C0000000000)
388#define ADDR_MASK_40_TO_41 ULL(0x0000030000000000)
389#define ADDR_MASK_36_TO_39 ULL(0x000000F000000000)
390#define ADDR_MASK_32_TO_35 ULL(0x0000000F00000000)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100391
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100392#define TCR_RGN_INNER_NC (ULL(0x0) << 8)
393#define TCR_RGN_INNER_WBA (ULL(0x1) << 8)
394#define TCR_RGN_INNER_WT (ULL(0x2) << 8)
395#define TCR_RGN_INNER_WBNA (ULL(0x3) << 8)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100396
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100397#define TCR_RGN_OUTER_NC (ULL(0x0) << 10)
398#define TCR_RGN_OUTER_WBA (ULL(0x1) << 10)
399#define TCR_RGN_OUTER_WT (ULL(0x2) << 10)
400#define TCR_RGN_OUTER_WBNA (ULL(0x3) << 10)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100401
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100402#define TCR_SH_NON_SHAREABLE (ULL(0x0) << 12)
403#define TCR_SH_OUTER_SHAREABLE (ULL(0x2) << 12)
404#define TCR_SH_INNER_SHAREABLE (ULL(0x3) << 12)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100405
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100406#define TCR_TG0_SHIFT U(14)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100407#define TCR_TG0_MASK ULL(3)
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100408#define TCR_TG0_4K (ULL(0) << TCR_TG0_SHIFT)
409#define TCR_TG0_64K (ULL(1) << TCR_TG0_SHIFT)
410#define TCR_TG0_16K (ULL(2) << TCR_TG0_SHIFT)
411
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100412#define TCR_EPD0_BIT (ULL(1) << 7)
413#define TCR_EPD1_BIT (ULL(1) << 23)
Antonio Nino Diazc8274a82017-09-15 10:30:34 +0100414
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700415#define MODE_SP_SHIFT U(0x0)
416#define MODE_SP_MASK U(0x1)
417#define MODE_SP_EL0 U(0x0)
418#define MODE_SP_ELX U(0x1)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100419
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700420#define MODE_RW_SHIFT U(0x4)
421#define MODE_RW_MASK U(0x1)
422#define MODE_RW_64 U(0x0)
423#define MODE_RW_32 U(0x1)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100424
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700425#define MODE_EL_SHIFT U(0x2)
426#define MODE_EL_MASK U(0x3)
427#define MODE_EL3 U(0x3)
428#define MODE_EL2 U(0x2)
429#define MODE_EL1 U(0x1)
430#define MODE_EL0 U(0x0)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100431
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700432#define MODE32_SHIFT U(0)
433#define MODE32_MASK U(0xf)
434#define MODE32_usr U(0x0)
435#define MODE32_fiq U(0x1)
436#define MODE32_irq U(0x2)
437#define MODE32_svc U(0x3)
438#define MODE32_mon U(0x6)
439#define MODE32_abt U(0x7)
440#define MODE32_hyp U(0xa)
441#define MODE32_und U(0xb)
442#define MODE32_sys U(0xf)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100443
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100444#define GET_RW(mode) (((mode) >> MODE_RW_SHIFT) & MODE_RW_MASK)
445#define GET_EL(mode) (((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK)
446#define GET_SP(mode) (((mode) >> MODE_SP_SHIFT) & MODE_SP_MASK)
447#define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100448
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100449#define SPSR_64(el, sp, daif) \
Antonio Nino Diaze8811472018-04-17 15:10:18 +0100450 ((MODE_RW_64 << MODE_RW_SHIFT) | \
451 (((el) & MODE_EL_MASK) << MODE_EL_SHIFT) | \
452 (((sp) & MODE_SP_MASK) << MODE_SP_SHIFT) | \
453 (((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT))
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100454
455#define SPSR_MODE32(mode, isa, endian, aif) \
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700456 ((MODE_RW_32 << MODE_RW_SHIFT) | \
457 (((mode) & MODE32_MASK) << MODE32_SHIFT) | \
458 (((isa) & SPSR_T_MASK) << SPSR_T_SHIFT) | \
459 (((endian) & SPSR_E_MASK) << SPSR_E_SHIFT) | \
460 (((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT))
Achin Gupta4f6ad662013-10-25 09:08:21 +0100461
Dan Handley0cdebbd2015-03-30 17:15:16 +0100462/*
Isla Mitchellc4a1a072017-08-07 11:20:13 +0100463 * TTBR Definitions
464 */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100465#define TTBR_CNP_BIT ULL(0x1)
Isla Mitchellc4a1a072017-08-07 11:20:13 +0100466
467/*
Dan Handley0cdebbd2015-03-30 17:15:16 +0100468 * CTR_EL0 definitions
469 */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700470#define CTR_CWG_SHIFT U(24)
471#define CTR_CWG_MASK U(0xf)
472#define CTR_ERG_SHIFT U(20)
473#define CTR_ERG_MASK U(0xf)
474#define CTR_DMINLINE_SHIFT U(16)
475#define CTR_DMINLINE_MASK U(0xf)
476#define CTR_L1IP_SHIFT U(14)
477#define CTR_L1IP_MASK U(0x3)
478#define CTR_IMINLINE_SHIFT U(0)
479#define CTR_IMINLINE_MASK U(0xf)
Dan Handley0cdebbd2015-03-30 17:15:16 +0100480
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700481#define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */
Achin Gupta4f6ad662013-10-25 09:08:21 +0100482
Achin Gupta405406d2014-05-09 12:00:17 +0100483/* Physical timer control register bit fields shifts and masks */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700484#define CNTP_CTL_ENABLE_SHIFT U(0)
485#define CNTP_CTL_IMASK_SHIFT U(1)
486#define CNTP_CTL_ISTATUS_SHIFT U(2)
Achin Gupta405406d2014-05-09 12:00:17 +0100487
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700488#define CNTP_CTL_ENABLE_MASK U(1)
489#define CNTP_CTL_IMASK_MASK U(1)
490#define CNTP_CTL_ISTATUS_MASK U(1)
Achin Gupta405406d2014-05-09 12:00:17 +0100491
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700492#define get_cntp_ctl_enable(x) (((x) >> CNTP_CTL_ENABLE_SHIFT) & \
Achin Gupta405406d2014-05-09 12:00:17 +0100493 CNTP_CTL_ENABLE_MASK)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700494#define get_cntp_ctl_imask(x) (((x) >> CNTP_CTL_IMASK_SHIFT) & \
Achin Gupta405406d2014-05-09 12:00:17 +0100495 CNTP_CTL_IMASK_MASK)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700496#define get_cntp_ctl_istatus(x) (((x) >> CNTP_CTL_ISTATUS_SHIFT) & \
Achin Gupta405406d2014-05-09 12:00:17 +0100497 CNTP_CTL_ISTATUS_MASK)
498
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700499#define set_cntp_ctl_enable(x) ((x) |= (U(1) << CNTP_CTL_ENABLE_SHIFT))
500#define set_cntp_ctl_imask(x) ((x) |= (U(1) << CNTP_CTL_IMASK_SHIFT))
Achin Gupta405406d2014-05-09 12:00:17 +0100501
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700502#define clr_cntp_ctl_enable(x) ((x) &= ~(U(1) << CNTP_CTL_ENABLE_SHIFT))
503#define clr_cntp_ctl_imask(x) ((x) &= ~(U(1) << CNTP_CTL_IMASK_SHIFT))
Achin Gupta405406d2014-05-09 12:00:17 +0100504
Achin Gupta4f6ad662013-10-25 09:08:21 +0100505/* Exception Syndrome register bits and bobs */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700506#define ESR_EC_SHIFT U(26)
507#define ESR_EC_MASK U(0x3f)
508#define ESR_EC_LENGTH U(6)
509#define EC_UNKNOWN U(0x0)
510#define EC_WFE_WFI U(0x1)
511#define EC_AARCH32_CP15_MRC_MCR U(0x3)
512#define EC_AARCH32_CP15_MRRC_MCRR U(0x4)
513#define EC_AARCH32_CP14_MRC_MCR U(0x5)
514#define EC_AARCH32_CP14_LDC_STC U(0x6)
515#define EC_FP_SIMD U(0x7)
516#define EC_AARCH32_CP10_MRC U(0x8)
517#define EC_AARCH32_CP14_MRRC_MCRR U(0xc)
518#define EC_ILLEGAL U(0xe)
519#define EC_AARCH32_SVC U(0x11)
520#define EC_AARCH32_HVC U(0x12)
521#define EC_AARCH32_SMC U(0x13)
522#define EC_AARCH64_SVC U(0x15)
523#define EC_AARCH64_HVC U(0x16)
524#define EC_AARCH64_SMC U(0x17)
525#define EC_AARCH64_SYS U(0x18)
526#define EC_IABORT_LOWER_EL U(0x20)
527#define EC_IABORT_CUR_EL U(0x21)
528#define EC_PC_ALIGN U(0x22)
529#define EC_DABORT_LOWER_EL U(0x24)
530#define EC_DABORT_CUR_EL U(0x25)
531#define EC_SP_ALIGN U(0x26)
532#define EC_AARCH32_FP U(0x28)
533#define EC_AARCH64_FP U(0x2c)
534#define EC_SERROR U(0x2f)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100535
Jeenu Viswambharan96c7df02017-11-30 12:54:15 +0000536/*
537 * External Abort bit in Instruction and Data Aborts synchronous exception
538 * syndromes.
539 */
540#define ESR_ISS_EABORT_EA_BIT U(9)
541
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700542#define EC_BITS(x) (((x) >> ESR_EC_SHIFT) & ESR_EC_MASK)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100543
Vignesh Radhakrishnanb4a72942017-03-03 10:58:05 -0800544/* Reset bit inside the Reset management register for EL3 (RMR_EL3) */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700545#define RMR_RESET_REQUEST_SHIFT U(0x1)
546#define RMR_WARM_RESET_CPU (U(1) << RMR_RESET_REQUEST_SHIFT)
Vignesh Radhakrishnanb4a72942017-03-03 10:58:05 -0800547
Dan Handleyed6ff952014-05-14 17:44:19 +0100548/*******************************************************************************
Antonio Nino Diazac998032017-02-27 17:23:54 +0000549 * Definitions of register offsets, fields and macros for CPU system
550 * instructions.
551 ******************************************************************************/
552
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700553#define TLBI_ADDR_SHIFT U(12)
Antonio Nino Diazac998032017-02-27 17:23:54 +0000554#define TLBI_ADDR_MASK ULL(0x00000FFFFFFFFFFF)
555#define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK)
556
557/*******************************************************************************
Dan Handleyed6ff952014-05-14 17:44:19 +0100558 * Definitions of register offsets and fields in the CNTCTLBase Frame of the
559 * system level implementation of the Generic Timer.
560 ******************************************************************************/
Soby Mathew2d9f7952018-06-11 16:21:30 +0100561#define CNTCTLBASE_CNTFRQ U(0x0)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700562#define CNTNSAR U(0x4)
563#define CNTNSAR_NS_SHIFT(x) (x)
Dan Handleyed6ff952014-05-14 17:44:19 +0100564
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700565#define CNTACR_BASE(x) (U(0x40) + ((x) << 2))
566#define CNTACR_RPCT_SHIFT U(0x0)
567#define CNTACR_RVCT_SHIFT U(0x1)
568#define CNTACR_RFRQ_SHIFT U(0x2)
569#define CNTACR_RVOFF_SHIFT U(0x3)
570#define CNTACR_RWVT_SHIFT U(0x4)
571#define CNTACR_RWPT_SHIFT U(0x5)
Dan Handleyed6ff952014-05-14 17:44:19 +0100572
Soby Mathew2d9f7952018-06-11 16:21:30 +0100573/*******************************************************************************
574 * Definitions of register offsets in the CNTBaseN Frame of the
575 * system level implementation of the Generic Timer.
576 ******************************************************************************/
577#define CNTBASE_CNTFRQ U(0x10)
578
David Cunado5f55e282016-10-31 17:37:34 +0000579/* PMCR_EL0 definitions */
David Cunado4168f2f2017-10-02 17:41:39 +0100580#define PMCR_EL0_RESET_VAL U(0x0)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700581#define PMCR_EL0_N_SHIFT U(11)
582#define PMCR_EL0_N_MASK U(0x1f)
David Cunado5f55e282016-10-31 17:37:34 +0000583#define PMCR_EL0_N_BITS (PMCR_EL0_N_MASK << PMCR_EL0_N_SHIFT)
David Cunado4168f2f2017-10-02 17:41:39 +0100584#define PMCR_EL0_LC_BIT (U(1) << 6)
585#define PMCR_EL0_DP_BIT (U(1) << 5)
586#define PMCR_EL0_X_BIT (U(1) << 4)
587#define PMCR_EL0_D_BIT (U(1) << 3)
David Cunado5f55e282016-10-31 17:37:34 +0000588
Isla Mitchell02c63072017-07-21 14:44:36 +0100589/*******************************************************************************
David Cunadoce88eee2017-10-20 11:30:57 +0100590 * Definitions for system register interface to SVE
591 ******************************************************************************/
592#define ZCR_EL3 S3_6_C1_C2_0
593#define ZCR_EL2 S3_4_C1_C2_0
594
595/* ZCR_EL3 definitions */
596#define ZCR_EL3_LEN_MASK U(0xf)
597
598/* ZCR_EL2 definitions */
599#define ZCR_EL2_LEN_MASK U(0xf)
600
601/*******************************************************************************
Isla Mitchell02c63072017-07-21 14:44:36 +0100602 * Definitions of MAIR encodings for device and normal memory
603 ******************************************************************************/
604/*
605 * MAIR encodings for device memory attributes.
606 */
607#define MAIR_DEV_nGnRnE ULL(0x0)
608#define MAIR_DEV_nGnRE ULL(0x4)
609#define MAIR_DEV_nGRE ULL(0x8)
610#define MAIR_DEV_GRE ULL(0xc)
611
612/*
613 * MAIR encodings for normal memory attributes.
614 *
615 * Cache Policy
616 * WT: Write Through
617 * WB: Write Back
618 * NC: Non-Cacheable
619 *
620 * Transient Hint
621 * NTR: Non-Transient
622 * TR: Transient
623 *
624 * Allocation Policy
625 * RA: Read Allocate
626 * WA: Write Allocate
627 * RWA: Read and Write Allocate
628 * NA: No Allocation
629 */
630#define MAIR_NORM_WT_TR_WA ULL(0x1)
631#define MAIR_NORM_WT_TR_RA ULL(0x2)
632#define MAIR_NORM_WT_TR_RWA ULL(0x3)
633#define MAIR_NORM_NC ULL(0x4)
634#define MAIR_NORM_WB_TR_WA ULL(0x5)
635#define MAIR_NORM_WB_TR_RA ULL(0x6)
636#define MAIR_NORM_WB_TR_RWA ULL(0x7)
637#define MAIR_NORM_WT_NTR_NA ULL(0x8)
638#define MAIR_NORM_WT_NTR_WA ULL(0x9)
639#define MAIR_NORM_WT_NTR_RA ULL(0xa)
640#define MAIR_NORM_WT_NTR_RWA ULL(0xb)
641#define MAIR_NORM_WB_NTR_NA ULL(0xc)
642#define MAIR_NORM_WB_NTR_WA ULL(0xd)
643#define MAIR_NORM_WB_NTR_RA ULL(0xe)
644#define MAIR_NORM_WB_NTR_RWA ULL(0xf)
645
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100646#define MAIR_NORM_OUTER_SHIFT U(4)
Isla Mitchell02c63072017-07-21 14:44:36 +0100647
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100648#define MAKE_MAIR_NORMAL_MEMORY(inner, outer) \
649 ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT))
Isla Mitchell02c63072017-07-21 14:44:36 +0100650
Jeenu Viswambharan1dc771b2017-10-19 09:15:15 +0100651/* PAR_EL1 fields */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100652#define PAR_F_SHIFT U(0)
653#define PAR_F_MASK ULL(0x1)
654#define PAR_ADDR_SHIFT U(12)
655#define PAR_ADDR_MASK (BIT(40) - ULL(1)) /* 40-bits-wide page address */
Jeenu Viswambharan1dc771b2017-10-19 09:15:15 +0100656
Dimitris Papastamos5bdbb472017-10-13 12:06:06 +0100657/*******************************************************************************
658 * Definitions for system register interface to SPE
659 ******************************************************************************/
660#define PMBLIMITR_EL1 S3_0_C9_C10_0
661
Dimitris Papastamose08005a2017-10-12 13:02:29 +0100662/*******************************************************************************
Jeenu Viswambharan2da918c2018-07-31 16:13:33 +0100663 * Definitions for system register interface to MPAM
664 ******************************************************************************/
665#define MPAMIDR_EL1 S3_0_C10_C4_4
666#define MPAM2_EL2 S3_4_C10_C5_0
667#define MPAMHCR_EL2 S3_4_C10_C4_0
668#define MPAM3_EL3 S3_6_C10_C5_0
669
670/*******************************************************************************
Dimitris Papastamose08005a2017-10-12 13:02:29 +0100671 * Definitions for system register interface to AMU for ARMv8.4 onwards
672 ******************************************************************************/
673#define AMCR_EL0 S3_3_C13_C2_0
674#define AMCFGR_EL0 S3_3_C13_C2_1
675#define AMCGCR_EL0 S3_3_C13_C2_2
676#define AMUSERENR_EL0 S3_3_C13_C2_3
677#define AMCNTENCLR0_EL0 S3_3_C13_C2_4
678#define AMCNTENSET0_EL0 S3_3_C13_C2_5
679#define AMCNTENCLR1_EL0 S3_3_C13_C3_0
680#define AMCNTENSET1_EL0 S3_3_C13_C3_1
681
682/* Activity Monitor Group 0 Event Counter Registers */
683#define AMEVCNTR00_EL0 S3_3_C13_C4_0
684#define AMEVCNTR01_EL0 S3_3_C13_C4_1
685#define AMEVCNTR02_EL0 S3_3_C13_C4_2
686#define AMEVCNTR03_EL0 S3_3_C13_C4_3
687
688/* Activity Monitor Group 0 Event Type Registers */
689#define AMEVTYPER00_EL0 S3_3_C13_C6_0
690#define AMEVTYPER01_EL0 S3_3_C13_C6_1
691#define AMEVTYPER02_EL0 S3_3_C13_C6_2
692#define AMEVTYPER03_EL0 S3_3_C13_C6_3
693
Dimitris Papastamos525c37a2017-11-13 09:49:45 +0000694/* Activity Monitor Group 1 Event Counter Registers */
695#define AMEVCNTR10_EL0 S3_3_C13_C12_0
696#define AMEVCNTR11_EL0 S3_3_C13_C12_1
697#define AMEVCNTR12_EL0 S3_3_C13_C12_2
698#define AMEVCNTR13_EL0 S3_3_C13_C12_3
699#define AMEVCNTR14_EL0 S3_3_C13_C12_4
700#define AMEVCNTR15_EL0 S3_3_C13_C12_5
701#define AMEVCNTR16_EL0 S3_3_C13_C12_6
702#define AMEVCNTR17_EL0 S3_3_C13_C12_7
703#define AMEVCNTR18_EL0 S3_3_C13_C13_0
704#define AMEVCNTR19_EL0 S3_3_C13_C13_1
705#define AMEVCNTR1A_EL0 S3_3_C13_C13_2
706#define AMEVCNTR1B_EL0 S3_3_C13_C13_3
707#define AMEVCNTR1C_EL0 S3_3_C13_C13_4
708#define AMEVCNTR1D_EL0 S3_3_C13_C13_5
709#define AMEVCNTR1E_EL0 S3_3_C13_C13_6
710#define AMEVCNTR1F_EL0 S3_3_C13_C13_7
711
712/* Activity Monitor Group 1 Event Type Registers */
713#define AMEVTYPER10_EL0 S3_3_C13_C14_0
714#define AMEVTYPER11_EL0 S3_3_C13_C14_1
715#define AMEVTYPER12_EL0 S3_3_C13_C14_2
716#define AMEVTYPER13_EL0 S3_3_C13_C14_3
717#define AMEVTYPER14_EL0 S3_3_C13_C14_4
718#define AMEVTYPER15_EL0 S3_3_C13_C14_5
719#define AMEVTYPER16_EL0 S3_3_C13_C14_6
720#define AMEVTYPER17_EL0 S3_3_C13_C14_7
721#define AMEVTYPER18_EL0 S3_3_C13_C15_0
722#define AMEVTYPER19_EL0 S3_3_C13_C15_1
723#define AMEVTYPER1A_EL0 S3_3_C13_C15_2
724#define AMEVTYPER1B_EL0 S3_3_C13_C15_3
725#define AMEVTYPER1C_EL0 S3_3_C13_C15_4
726#define AMEVTYPER1D_EL0 S3_3_C13_C15_5
727#define AMEVTYPER1E_EL0 S3_3_C13_C15_6
728#define AMEVTYPER1F_EL0 S3_3_C13_C15_7
729
730/* AMCGCR_EL0 definitions */
731#define AMCGCR_EL0_CG1NC_SHIFT U(8)
732#define AMCGCR_EL0_CG1NC_LENGTH U(8)
733#define AMCGCR_EL0_CG1NC_MASK U(0xff)
734
Jeenu Viswambharan2da918c2018-07-31 16:13:33 +0100735/* MPAM register definitions */
736#define MPAM3_EL3_MPAMEN_BIT (ULL(1) << 63)
737
738#define MPAMIDR_HAS_HCR_BIT (ULL(1) << 17)
739
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100740/*******************************************************************************
741 * RAS system registers
742 *******************************************************************************/
743#define DISR_EL1 S3_0_C12_C1_1
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100744#define DISR_A_BIT U(31)
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100745
Jeenu Viswambharan19f6cf22017-12-07 08:43:05 +0000746#define ERRIDR_EL1 S3_0_C5_C3_0
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100747#define ERRIDR_MASK U(0xffff)
Jeenu Viswambharan19f6cf22017-12-07 08:43:05 +0000748
749#define ERRSELR_EL1 S3_0_C5_C3_1
750
751/* System register access to Standard Error Record registers */
752#define ERXFR_EL1 S3_0_C5_C4_0
753#define ERXCTLR_EL1 S3_0_C5_C4_1
754#define ERXSTATUS_EL1 S3_0_C5_C4_2
755#define ERXADDR_EL1 S3_0_C5_C4_3
Jan Dabros82ef8bf2018-08-30 13:52:23 +0200756#define ERXMISC0_EL1 S3_0_C5_C5_0
757#define ERXMISC1_EL1 S3_0_C5_C5_1
Jeenu Viswambharan19f6cf22017-12-07 08:43:05 +0000758
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +0100759#endif /* ARCH_H */