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Achin Gupta92712a52015-09-03 14:18:02 +01001/*
Heyi Guoc5bd63c2020-05-19 14:01:49 +08002 * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
Achin Gupta92712a52015-09-03 14:18:02 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta92712a52015-09-03 14:18:02 +01005 */
6
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00007#include <assert.h>
8
Achin Gupta92712a52015-09-03 14:18:02 +01009#include <arch.h>
10#include <arch_helpers.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011#include <common/debug.h>
12#include <common/interrupt_props.h>
13#include <drivers/arm/gic_common.h>
14
Soby Mathew50f6fe42016-02-01 17:59:22 +000015#include "../common/gic_common_private.h"
Achin Gupta92712a52015-09-03 14:18:02 +010016#include "gicv3_private.h"
17
Achin Gupta92712a52015-09-03 14:18:02 +010018/******************************************************************************
19 * This function marks the core as awake in the re-distributor and
20 * ensures that the interface is active.
21 *****************************************************************************/
22void gicv3_rdistif_mark_core_awake(uintptr_t gicr_base)
23{
24 /*
25 * The WAKER_PS_BIT should be changed to 0
26 * only when WAKER_CA_BIT is 1.
27 */
Antonio Nino Diazca994e72018-08-21 10:02:33 +010028 assert((gicr_read_waker(gicr_base) & WAKER_CA_BIT) != 0U);
Achin Gupta92712a52015-09-03 14:18:02 +010029
30 /* Mark the connected core as awake */
31 gicr_write_waker(gicr_base, gicr_read_waker(gicr_base) & ~WAKER_PS_BIT);
32
33 /* Wait till the WAKER_CA_BIT changes to 0 */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +010034 while ((gicr_read_waker(gicr_base) & WAKER_CA_BIT) != 0U) {
35 }
Achin Gupta92712a52015-09-03 14:18:02 +010036}
37
Achin Gupta92712a52015-09-03 14:18:02 +010038/******************************************************************************
39 * This function marks the core as asleep in the re-distributor and ensures
40 * that the interface is quiescent.
41 *****************************************************************************/
42void gicv3_rdistif_mark_core_asleep(uintptr_t gicr_base)
43{
44 /* Mark the connected core as asleep */
45 gicr_write_waker(gicr_base, gicr_read_waker(gicr_base) | WAKER_PS_BIT);
46
47 /* Wait till the WAKER_CA_BIT changes to 1 */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +010048 while ((gicr_read_waker(gicr_base) & WAKER_CA_BIT) == 0U) {
49 }
Achin Gupta92712a52015-09-03 14:18:02 +010050}
51
Achin Gupta92712a52015-09-03 14:18:02 +010052/*******************************************************************************
53 * This function probes the Redistributor frames when the driver is initialised
54 * and saves their base addresses. These base addresses are used later to
55 * initialise each Redistributor interface.
56 ******************************************************************************/
57void gicv3_rdistif_base_addrs_probe(uintptr_t *rdistif_base_addrs,
58 unsigned int rdistif_num,
59 uintptr_t gicr_base,
60 mpidr_hash_fn mpidr_to_core_pos)
61{
Soby Mathewa0fedc42016-06-16 14:52:04 +010062 u_register_t mpidr;
Achin Gupta92712a52015-09-03 14:18:02 +010063 unsigned int proc_num;
Antonio Nino Diazca994e72018-08-21 10:02:33 +010064 uint64_t typer_val;
Achin Gupta92712a52015-09-03 14:18:02 +010065 uintptr_t rdistif_base = gicr_base;
66
Antonio Nino Diazca994e72018-08-21 10:02:33 +010067 assert(rdistif_base_addrs != NULL);
Achin Gupta92712a52015-09-03 14:18:02 +010068
69 /*
70 * Iterate over the Redistributor frames. Store the base address of each
71 * frame in the platform provided array. Use the "Processor Number"
72 * field to index into the array if the platform has not provided a hash
73 * function to convert an MPIDR (obtained from the "Affinity Value"
74 * field into a linear index.
75 */
76 do {
77 typer_val = gicr_read_typer(rdistif_base);
Antonio Nino Diazca994e72018-08-21 10:02:33 +010078 if (mpidr_to_core_pos != NULL) {
Achin Gupta92712a52015-09-03 14:18:02 +010079 mpidr = mpidr_from_gicr_typer(typer_val);
80 proc_num = mpidr_to_core_pos(mpidr);
81 } else {
82 proc_num = (typer_val >> TYPER_PROC_NUM_SHIFT) &
83 TYPER_PROC_NUM_MASK;
84 }
Soby Mathewd1463bd2019-01-17 14:57:54 +000085
Alexei Fedorova6e6ae02020-04-06 16:27:54 +010086 if (proc_num < rdistif_num) {
Soby Mathewd1463bd2019-01-17 14:57:54 +000087 rdistif_base_addrs[proc_num] = rdistif_base;
Alexei Fedorova6e6ae02020-04-06 16:27:54 +010088 }
Andre Przywaraf70f4b92021-05-18 15:51:06 +010089 rdistif_base += gicv3_redist_size(typer_val);
Antonio Nino Diazca994e72018-08-21 10:02:33 +010090 } while ((typer_val & TYPER_LAST_BIT) == 0U);
Achin Gupta92712a52015-09-03 14:18:02 +010091}
92
93/*******************************************************************************
Heyi Guo06f85b42021-01-20 18:50:16 +080094 * Helper function to get the maximum SPI INTID + 1.
95 ******************************************************************************/
96unsigned int gicv3_get_spi_limit(uintptr_t gicd_base)
97{
98 unsigned int spi_limit;
99 unsigned int typer_reg = gicd_read_typer(gicd_base);
100
101 /* (maximum SPI INTID + 1) is equal to 32 * (GICD_TYPER.ITLinesNumber+1) */
102 spi_limit = ((typer_reg & TYPER_IT_LINES_NO_MASK) + 1U) << 5;
103
104 /* Filter out special INTIDs 1020-1023 */
105 if (spi_limit > (MAX_SPI_ID + 1U)) {
106 return MAX_SPI_ID + 1U;
107 }
108
109 return spi_limit;
110}
111
Heyi Guo60ce8252021-01-20 18:50:16 +0800112#if GIC_EXT_INTID
113/*******************************************************************************
114 * Helper function to get the maximum ESPI INTID + 1.
115 ******************************************************************************/
116unsigned int gicv3_get_espi_limit(uintptr_t gicd_base)
117{
118 unsigned int typer_reg = gicd_read_typer(gicd_base);
119
120 /* Check if extended SPI range is implemented */
121 if ((typer_reg & TYPER_ESPI) != 0U) {
122 /*
123 * (maximum ESPI INTID + 1) is equal to
124 * 32 * (GICD_TYPER.ESPI_range + 1) + 4096
125 */
126 return ((((typer_reg >> TYPER_ESPI_RANGE_SHIFT) &
127 TYPER_ESPI_RANGE_MASK) + 1U) << 5) + MIN_ESPI_ID;
128 }
129
130 return 0U;
131}
132#endif /* GIC_EXT_INTID */
133
Heyi Guo06f85b42021-01-20 18:50:16 +0800134/*******************************************************************************
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100135 * Helper function to configure the default attributes of (E)SPIs.
Achin Gupta92712a52015-09-03 14:18:02 +0100136 ******************************************************************************/
Daniel Boulby4e83abb2018-05-01 15:15:34 +0100137void gicv3_spis_config_defaults(uintptr_t gicd_base)
Achin Gupta92712a52015-09-03 14:18:02 +0100138{
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100139 unsigned int i, num_ints;
140#if GIC_EXT_INTID
141 unsigned int num_eints;
142#endif
Achin Gupta92712a52015-09-03 14:18:02 +0100143
Heyi Guo79bc7a72021-01-20 19:05:51 +0800144 num_ints = gicv3_get_spi_limit(gicd_base);
Heyi Guoce380252021-01-21 10:34:00 +0800145 INFO("Maximum SPI INTID supported: %u\n", num_ints - 1);
Heyi Guo0d5d24d2020-05-19 15:41:14 +0800146
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100147 /* Treat all (E)SPIs as G1NS by default. We do 32 at a time. */
148 for (i = MIN_SPI_ID; i < num_ints; i += (1U << IGROUPR_SHIFT)) {
149 gicd_write_igroupr(gicd_base, i, ~0U);
150 }
Achin Gupta92712a52015-09-03 14:18:02 +0100151
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100152#if GIC_EXT_INTID
Heyi Guo79bc7a72021-01-20 19:05:51 +0800153 num_eints = gicv3_get_espi_limit(gicd_base);
154 if (num_eints != 0U) {
Heyi Guoce380252021-01-21 10:34:00 +0800155 INFO("Maximum ESPI INTID supported: %u\n", num_eints - 1);
Achin Gupta92712a52015-09-03 14:18:02 +0100156
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100157 for (i = MIN_ESPI_ID; i < num_eints;
158 i += (1U << IGROUPR_SHIFT)) {
159 gicd_write_igroupr(gicd_base, i, ~0U);
160 }
161 } else {
Heyi Guoce380252021-01-21 10:34:00 +0800162 INFO("ESPI range is not implemented.\n");
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100163 }
164#endif
165
166 /* Setup the default (E)SPI priorities doing four at a time */
167 for (i = MIN_SPI_ID; i < num_ints; i += (1U << IPRIORITYR_SHIFT)) {
168 gicd_write_ipriorityr(gicd_base, i, GICD_IPRIORITYR_DEF_VAL);
169 }
170
171#if GIC_EXT_INTID
172 for (i = MIN_ESPI_ID; i < num_eints;
173 i += (1U << IPRIORITYR_SHIFT)) {
174 gicd_write_ipriorityr(gicd_base, i, GICD_IPRIORITYR_DEF_VAL);
175 }
176#endif
Achin Gupta92712a52015-09-03 14:18:02 +0100177 /*
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100178 * Treat all (E)SPIs as level triggered by default, write 16 at a time
Achin Gupta92712a52015-09-03 14:18:02 +0100179 */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100180 for (i = MIN_SPI_ID; i < num_ints; i += (1U << ICFGR_SHIFT)) {
181 gicd_write_icfgr(gicd_base, i, 0U);
182 }
183
184#if GIC_EXT_INTID
185 for (i = MIN_ESPI_ID; i < num_eints; i += (1U << ICFGR_SHIFT)) {
186 gicd_write_icfgr(gicd_base, i, 0U);
187 }
188#endif
Achin Gupta92712a52015-09-03 14:18:02 +0100189}
190
Achin Gupta92712a52015-09-03 14:18:02 +0100191/*******************************************************************************
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100192 * Helper function to configure properties of secure (E)SPIs
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100193 ******************************************************************************/
Daniel Boulby4e83abb2018-05-01 15:15:34 +0100194unsigned int gicv3_secure_spis_config_props(uintptr_t gicd_base,
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100195 const interrupt_prop_t *interrupt_props,
196 unsigned int interrupt_props_num)
197{
198 unsigned int i;
199 const interrupt_prop_t *current_prop;
200 unsigned long long gic_affinity_val;
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100201 unsigned int ctlr_enable = 0U;
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100202
203 /* Make sure there's a valid property array */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100204 if (interrupt_props_num > 0U) {
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100205 assert(interrupt_props != NULL);
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100206 }
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100207
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100208 for (i = 0U; i < interrupt_props_num; i++) {
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100209 current_prop = &interrupt_props[i];
210
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100211 unsigned int intr_num = current_prop->intr_num;
212
213 /* Skip SGI, (E)PPI and LPI interrupts */
214 if (!IS_SPI(intr_num)) {
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100215 continue;
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100216 }
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100217
218 /* Configure this interrupt as a secure interrupt */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100219 gicd_clr_igroupr(gicd_base, intr_num);
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100220
221 /* Configure this interrupt as G0 or a G1S interrupt */
222 assert((current_prop->intr_grp == INTR_GROUP0) ||
223 (current_prop->intr_grp == INTR_GROUP1S));
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100224
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100225 if (current_prop->intr_grp == INTR_GROUP1S) {
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100226 gicd_set_igrpmodr(gicd_base, intr_num);
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100227 ctlr_enable |= CTLR_ENABLE_G1S_BIT;
228 } else {
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100229 gicd_clr_igrpmodr(gicd_base, intr_num);
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100230 ctlr_enable |= CTLR_ENABLE_G0_BIT;
231 }
232
233 /* Set interrupt configuration */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100234 gicd_set_icfgr(gicd_base, intr_num, current_prop->intr_cfg);
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100235
236 /* Set the priority of this interrupt */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100237 gicd_set_ipriorityr(gicd_base, intr_num,
238 current_prop->intr_pri);
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100239
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100240 /* Target (E)SPIs to the primary CPU */
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100241 gic_affinity_val =
242 gicd_irouter_val_from_mpidr(read_mpidr(), 0U);
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100243 gicd_write_irouter(gicd_base, intr_num,
244 gic_affinity_val);
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100245
246 /* Enable this interrupt */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100247 gicd_set_isenabler(gicd_base, intr_num);
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100248 }
249
250 return ctlr_enable;
251}
252
253/*******************************************************************************
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100254 * Helper function to configure the default attributes of (E)SPIs
Achin Gupta92712a52015-09-03 14:18:02 +0100255 ******************************************************************************/
Daniel Boulby4e83abb2018-05-01 15:15:34 +0100256void gicv3_ppi_sgi_config_defaults(uintptr_t gicr_base)
Achin Gupta92712a52015-09-03 14:18:02 +0100257{
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100258 unsigned int i, ppi_regs_num, regs_num;
Achin Gupta92712a52015-09-03 14:18:02 +0100259
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100260#if GIC_EXT_INTID
261 /* Calculate number of PPI registers */
262 ppi_regs_num = (unsigned int)((gicr_read_typer(gicr_base) >>
263 TYPER_PPI_NUM_SHIFT) & TYPER_PPI_NUM_MASK) + 1;
264 /* All other values except PPInum [0-2] are reserved */
265 if (ppi_regs_num > 3U) {
266 ppi_regs_num = 1U;
267 }
268#else
269 ppi_regs_num = 1U;
270#endif
Achin Gupta92712a52015-09-03 14:18:02 +0100271 /*
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100272 * Disable all SGIs (imp. def.)/(E)PPIs before configuring them.
273 * This is a more scalable approach as it avoids clearing
274 * the enable bits in the GICD_CTLR.
Achin Gupta92712a52015-09-03 14:18:02 +0100275 */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100276 for (i = 0U; i < ppi_regs_num; ++i) {
277 gicr_write_icenabler(gicr_base, i, ~0U);
278 }
279
280 /* Wait for pending writes to GICR_ICENABLER */
Achin Gupta92712a52015-09-03 14:18:02 +0100281 gicr_wait_for_pending_write(gicr_base);
282
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100283 /* 32 interrupt IDs per GICR_IGROUPR register */
284 for (i = 0U; i < ppi_regs_num; ++i) {
285 /* Treat all SGIs/(E)PPIs as G1NS by default */
286 gicr_write_igroupr(gicr_base, i, ~0U);
287 }
Achin Gupta92712a52015-09-03 14:18:02 +0100288
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100289 /* 4 interrupt IDs per GICR_IPRIORITYR register */
290 regs_num = ppi_regs_num << 3;
291 for (i = 0U; i < regs_num; ++i) {
292 /* Setup the default (E)PPI/SGI priorities doing 4 at a time */
293 gicr_write_ipriorityr(gicr_base, i, GICD_IPRIORITYR_DEF_VAL);
294 }
Achin Gupta92712a52015-09-03 14:18:02 +0100295
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100296 /* 16 interrupt IDs per GICR_ICFGR register */
297 regs_num = ppi_regs_num << 1;
298 for (i = (MIN_PPI_ID >> ICFGR_SHIFT); i < regs_num; ++i) {
299 /* Configure all (E)PPIs as level triggered by default */
300 gicr_write_icfgr(gicr_base, i, 0U);
301 }
Achin Gupta92712a52015-09-03 14:18:02 +0100302}
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100303
304/*******************************************************************************
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100305 * Helper function to configure properties of secure G0 and G1S (E)PPIs and SGIs
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100306 ******************************************************************************/
Daniel Boulby4e83abb2018-05-01 15:15:34 +0100307unsigned int gicv3_secure_ppi_sgi_config_props(uintptr_t gicr_base,
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100308 const interrupt_prop_t *interrupt_props,
309 unsigned int interrupt_props_num)
310{
311 unsigned int i;
312 const interrupt_prop_t *current_prop;
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100313 unsigned int ctlr_enable = 0U;
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100314
315 /* Make sure there's a valid property array */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100316 if (interrupt_props_num > 0U) {
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100317 assert(interrupt_props != NULL);
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100318 }
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100319
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100320 for (i = 0U; i < interrupt_props_num; i++) {
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100321 current_prop = &interrupt_props[i];
322
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100323 unsigned int intr_num = current_prop->intr_num;
324
325 /* Skip (E)SPI interrupt */
326 if (!IS_SGI_PPI(intr_num)) {
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100327 continue;
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100328 }
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100329
330 /* Configure this interrupt as a secure interrupt */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100331 gicr_clr_igroupr(gicr_base, intr_num);
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100332
333 /* Configure this interrupt as G0 or a G1S interrupt */
334 assert((current_prop->intr_grp == INTR_GROUP0) ||
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100335 (current_prop->intr_grp == INTR_GROUP1S));
336
Jeenu Viswambharan88d8f452017-11-07 08:38:23 +0000337 if (current_prop->intr_grp == INTR_GROUP1S) {
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100338 gicr_set_igrpmodr(gicr_base, intr_num);
Jeenu Viswambharan88d8f452017-11-07 08:38:23 +0000339 ctlr_enable |= CTLR_ENABLE_G1S_BIT;
340 } else {
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100341 gicr_clr_igrpmodr(gicr_base, intr_num);
Jeenu Viswambharan88d8f452017-11-07 08:38:23 +0000342 ctlr_enable |= CTLR_ENABLE_G0_BIT;
343 }
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100344
345 /* Set the priority of this interrupt */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100346 gicr_set_ipriorityr(gicr_base, intr_num,
347 current_prop->intr_pri);
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100348
349 /*
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100350 * Set interrupt configuration for (E)PPIs.
351 * Configurations for SGIs 0-15 are ignored.
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100352 */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100353 if (intr_num >= MIN_PPI_ID) {
354 gicr_set_icfgr(gicr_base, intr_num,
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100355 current_prop->intr_cfg);
356 }
357
358 /* Enable this interrupt */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100359 gicr_set_isenabler(gicr_base, intr_num);
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100360 }
Jeenu Viswambharan88d8f452017-11-07 08:38:23 +0000361
362 return ctlr_enable;
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100363}
Andre Przywara95581b42020-09-07 14:53:58 +0100364
365/**
366 * gicv3_rdistif_get_number_frames() - determine size of GICv3 GICR region
367 * @gicr_frame: base address of the GICR region to check
368 *
369 * This iterates over the GICR_TYPER registers of multiple GICR frames in
370 * a GICR region, to find the instance which has the LAST bit set. For most
371 * systems this corresponds to the number of cores handled by a redistributor,
372 * but there could be disabled cores among them.
373 * It assumes that each GICR region is fully accessible (till the LAST bit
374 * marks the end of the region).
375 * If a platform has multiple GICR regions, this function would need to be
376 * called multiple times, providing the respective GICR base address each time.
377 *
378 * Return: number of valid GICR frames (at least 1, up to PLATFORM_CORE_COUNT)
379 ******************************************************************************/
380unsigned int gicv3_rdistif_get_number_frames(const uintptr_t gicr_frame)
381{
382 uintptr_t rdistif_base = gicr_frame;
383 unsigned int count;
384
Andre Przywaraf70f4b92021-05-18 15:51:06 +0100385 for (count = 1U; count < PLATFORM_CORE_COUNT; count++) {
386 uint64_t typer_val = gicr_read_typer(rdistif_base);
387
388 if ((typer_val & TYPER_LAST_BIT) != 0U) {
Andre Przywara95581b42020-09-07 14:53:58 +0100389 break;
390 }
Andre Przywaraf70f4b92021-05-18 15:51:06 +0100391 rdistif_base += gicv3_redist_size(typer_val);
Andre Przywara95581b42020-09-07 14:53:58 +0100392 }
393
394 return count;
395}