gic: Fix types
Change-Id: I6a2adef87c20f9279446a54b7e69618fba3d2a25
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
diff --git a/drivers/arm/gic/v3/gicv3_helpers.c b/drivers/arm/gic/v3/gicv3_helpers.c
index 2ea8c72..1953a37 100644
--- a/drivers/arm/gic/v3/gicv3_helpers.c
+++ b/drivers/arm/gic/v3/gicv3_helpers.c
@@ -19,7 +19,8 @@
*/
unsigned int gicd_read_igrpmodr(uintptr_t base, unsigned int id)
{
- unsigned n = id >> IGRPMODR_SHIFT;
+ unsigned int n = id >> IGRPMODR_SHIFT;
+
return mmio_read_32(base + GICD_IGRPMODR + (n << 2));
}
@@ -29,7 +30,8 @@
*/
void gicd_write_igrpmodr(uintptr_t base, unsigned int id, unsigned int val)
{
- unsigned n = id >> IGRPMODR_SHIFT;
+ unsigned int n = id >> IGRPMODR_SHIFT;
+
mmio_write_32(base + GICD_IGRPMODR + (n << 2), val);
}
@@ -39,10 +41,10 @@
*/
unsigned int gicd_get_igrpmodr(uintptr_t base, unsigned int id)
{
- unsigned bit_num = id & ((1 << IGRPMODR_SHIFT) - 1);
+ unsigned int bit_num = id & ((1U << IGRPMODR_SHIFT) - 1U);
unsigned int reg_val = gicd_read_igrpmodr(base, id);
- return (reg_val >> bit_num) & 0x1;
+ return (reg_val >> bit_num) & 0x1U;
}
/*
@@ -51,10 +53,10 @@
*/
void gicd_set_igrpmodr(uintptr_t base, unsigned int id)
{
- unsigned bit_num = id & ((1 << IGRPMODR_SHIFT) - 1);
+ unsigned int bit_num = id & ((1U << IGRPMODR_SHIFT) - 1U);
unsigned int reg_val = gicd_read_igrpmodr(base, id);
- gicd_write_igrpmodr(base, id, reg_val | (1 << bit_num));
+ gicd_write_igrpmodr(base, id, reg_val | (1U << bit_num));
}
/*
@@ -63,10 +65,10 @@
*/
void gicd_clr_igrpmodr(uintptr_t base, unsigned int id)
{
- unsigned bit_num = id & ((1 << IGRPMODR_SHIFT) - 1);
+ unsigned int bit_num = id & ((1U << IGRPMODR_SHIFT) - 1U);
unsigned int reg_val = gicd_read_igrpmodr(base, id);
- gicd_write_igrpmodr(base, id, reg_val & ~(1 << bit_num));
+ gicd_write_igrpmodr(base, id, reg_val & ~(1U << bit_num));
}
/*
@@ -75,7 +77,8 @@
*/
unsigned int gicr_read_ipriorityr(uintptr_t base, unsigned int id)
{
- unsigned n = id >> IPRIORITYR_SHIFT;
+ unsigned int n = id >> IPRIORITYR_SHIFT;
+
return mmio_read_32(base + GICR_IPRIORITYR + (n << 2));
}
@@ -85,7 +88,8 @@
*/
void gicr_write_ipriorityr(uintptr_t base, unsigned int id, unsigned int val)
{
- unsigned n = id >> IPRIORITYR_SHIFT;
+ unsigned int n = id >> IPRIORITYR_SHIFT;
+
mmio_write_32(base + GICR_IPRIORITYR + (n << 2), val);
}
@@ -95,10 +99,10 @@
*/
unsigned int gicr_get_igroupr0(uintptr_t base, unsigned int id)
{
- unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1);
+ unsigned int bit_num = id & ((1U << IGROUPR_SHIFT) - 1U);
unsigned int reg_val = gicr_read_igroupr0(base);
- return (reg_val >> bit_num) & 0x1;
+ return (reg_val >> bit_num) & 0x1U;
}
/*
@@ -107,10 +111,10 @@
*/
void gicr_set_igroupr0(uintptr_t base, unsigned int id)
{
- unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1);
+ unsigned int bit_num = id & ((1U << IGROUPR_SHIFT) - 1U);
unsigned int reg_val = gicr_read_igroupr0(base);
- gicr_write_igroupr0(base, reg_val | (1 << bit_num));
+ gicr_write_igroupr0(base, reg_val | (1U << bit_num));
}
/*
@@ -119,10 +123,10 @@
*/
void gicr_clr_igroupr0(uintptr_t base, unsigned int id)
{
- unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1);
+ unsigned int bit_num = id & ((1U << IGROUPR_SHIFT) - 1U);
unsigned int reg_val = gicr_read_igroupr0(base);
- gicr_write_igroupr0(base, reg_val & ~(1 << bit_num));
+ gicr_write_igroupr0(base, reg_val & ~(1U << bit_num));
}
/*
@@ -131,10 +135,10 @@
*/
unsigned int gicr_get_igrpmodr0(uintptr_t base, unsigned int id)
{
- unsigned bit_num = id & ((1 << IGRPMODR_SHIFT) - 1);
+ unsigned int bit_num = id & ((1U << IGRPMODR_SHIFT) - 1U);
unsigned int reg_val = gicr_read_igrpmodr0(base);
- return (reg_val >> bit_num) & 0x1;
+ return (reg_val >> bit_num) & 0x1U;
}
/*
@@ -143,10 +147,10 @@
*/
void gicr_set_igrpmodr0(uintptr_t base, unsigned int id)
{
- unsigned bit_num = id & ((1 << IGRPMODR_SHIFT) - 1);
+ unsigned int bit_num = id & ((1U << IGRPMODR_SHIFT) - 1U);
unsigned int reg_val = gicr_read_igrpmodr0(base);
- gicr_write_igrpmodr0(base, reg_val | (1 << bit_num));
+ gicr_write_igrpmodr0(base, reg_val | (1U << bit_num));
}
/*
@@ -155,10 +159,10 @@
*/
void gicr_clr_igrpmodr0(uintptr_t base, unsigned int id)
{
- unsigned bit_num = id & ((1 << IGRPMODR_SHIFT) - 1);
+ unsigned int bit_num = id & ((1U << IGRPMODR_SHIFT) - 1U);
unsigned int reg_val = gicr_read_igrpmodr0(base);
- gicr_write_igrpmodr0(base, reg_val & ~(1 << bit_num));
+ gicr_write_igrpmodr0(base, reg_val & ~(1U << bit_num));
}
/*
@@ -167,9 +171,9 @@
*/
void gicr_set_isenabler0(uintptr_t base, unsigned int id)
{
- unsigned bit_num = id & ((1 << ISENABLER_SHIFT) - 1);
+ unsigned int bit_num = id & ((1U << ISENABLER_SHIFT) - 1U);
- gicr_write_isenabler0(base, (1 << bit_num));
+ gicr_write_isenabler0(base, (1U << bit_num));
}
/*
@@ -178,9 +182,9 @@
*/
void gicr_set_icenabler0(uintptr_t base, unsigned int id)
{
- unsigned bit_num = id & ((1 << ICENABLER_SHIFT) - 1);
+ unsigned int bit_num = id & ((1U << ICENABLER_SHIFT) - 1U);
- gicr_write_icenabler0(base, (1 << bit_num));
+ gicr_write_icenabler0(base, (1U << bit_num));
}
/*
@@ -189,10 +193,10 @@
*/
unsigned int gicr_get_isactiver0(uintptr_t base, unsigned int id)
{
- unsigned bit_num = id & ((1 << ISACTIVER_SHIFT) - 1);
+ unsigned int bit_num = id & ((1U << ISACTIVER_SHIFT) - 1U);
unsigned int reg_val = gicr_read_isactiver0(base);
- return (reg_val >> bit_num) & 0x1;
+ return (reg_val >> bit_num) & 0x1U;
}
/*
@@ -201,9 +205,9 @@
*/
void gicr_set_icpendr0(uintptr_t base, unsigned int id)
{
- unsigned bit_num = id & ((1 << ICPENDR_SHIFT) - 1);
+ unsigned int bit_num = id & ((1U << ICPENDR_SHIFT) - 1U);
- gicr_write_icpendr0(base, (1 << bit_num));
+ gicr_write_icpendr0(base, (1U << bit_num));
}
/*
@@ -212,9 +216,9 @@
*/
void gicr_set_ispendr0(uintptr_t base, unsigned int id)
{
- unsigned bit_num = id & ((1 << ISPENDR_SHIFT) - 1);
+ unsigned int bit_num = id & ((1U << ISPENDR_SHIFT) - 1U);
- gicr_write_ispendr0(base, (1 << bit_num));
+ gicr_write_ispendr0(base, (1U << bit_num));
}
/*
@@ -223,7 +227,9 @@
*/
void gicr_set_ipriorityr(uintptr_t base, unsigned int id, unsigned int pri)
{
- mmio_write_8(base + GICR_IPRIORITYR + id, pri & GIC_PRI_MASK);
+ uint8_t val = pri & GIC_PRI_MASK;
+
+ mmio_write_8(base + GICR_IPRIORITYR + id, val);
}
/*
@@ -233,8 +239,8 @@
void gicr_set_icfgr0(uintptr_t base, unsigned int id, unsigned int cfg)
{
/* Interrupt configuration is a 2-bit field */
- unsigned int bit_num = id & ((1 << ICFGR_SHIFT) - 1);
- unsigned int bit_shift = bit_num << 1;
+ unsigned int bit_num = id & ((1U << ICFGR_SHIFT) - 1U);
+ unsigned int bit_shift = bit_num << 1U;
uint32_t reg_val = gicr_read_icfgr0(base);
@@ -252,8 +258,8 @@
void gicr_set_icfgr1(uintptr_t base, unsigned int id, unsigned int cfg)
{
/* Interrupt configuration is a 2-bit field */
- unsigned int bit_num = id & ((1 << ICFGR_SHIFT) - 1);
- unsigned int bit_shift = bit_num << 1;
+ unsigned int bit_num = id & ((1U << ICFGR_SHIFT) - 1U);
+ unsigned int bit_shift = bit_num << 1U;
uint32_t reg_val = gicr_read_icfgr1(base);
@@ -274,13 +280,13 @@
* The WAKER_PS_BIT should be changed to 0
* only when WAKER_CA_BIT is 1.
*/
- assert(gicr_read_waker(gicr_base) & WAKER_CA_BIT);
+ assert((gicr_read_waker(gicr_base) & WAKER_CA_BIT) != 0U);
/* Mark the connected core as awake */
gicr_write_waker(gicr_base, gicr_read_waker(gicr_base) & ~WAKER_PS_BIT);
/* Wait till the WAKER_CA_BIT changes to 0 */
- while (gicr_read_waker(gicr_base) & WAKER_CA_BIT)
+ while ((gicr_read_waker(gicr_base) & WAKER_CA_BIT) != 0U)
;
}
@@ -295,7 +301,7 @@
gicr_write_waker(gicr_base, gicr_read_waker(gicr_base) | WAKER_PS_BIT);
/* Wait till the WAKER_CA_BIT changes to 1 */
- while (!(gicr_read_waker(gicr_base) & WAKER_CA_BIT))
+ while ((gicr_read_waker(gicr_base) & WAKER_CA_BIT) == 0U)
;
}
@@ -312,10 +318,10 @@
{
u_register_t mpidr;
unsigned int proc_num;
- unsigned long long typer_val;
+ uint64_t typer_val;
uintptr_t rdistif_base = gicr_base;
- assert(rdistif_base_addrs);
+ assert(rdistif_base_addrs != NULL);
/*
* Iterate over the Redistributor frames. Store the base address of each
@@ -326,7 +332,7 @@
*/
do {
typer_val = gicr_read_typer(rdistif_base);
- if (mpidr_to_core_pos) {
+ if (mpidr_to_core_pos != NULL) {
mpidr = mpidr_from_gicr_typer(typer_val);
proc_num = mpidr_to_core_pos(mpidr);
} else {
@@ -335,8 +341,8 @@
}
assert(proc_num < rdistif_num);
rdistif_base_addrs[proc_num] = rdistif_base;
- rdistif_base += (1 << GICR_PCPUBASE_SHIFT);
- } while (!(typer_val & TYPER_LAST_BIT));
+ rdistif_base += (1U << GICR_PCPUBASE_SHIFT);
+ } while ((typer_val & TYPER_LAST_BIT) == 0U);
}
/*******************************************************************************
@@ -348,17 +354,17 @@
num_ints = gicd_read_typer(gicd_base);
num_ints &= TYPER_IT_LINES_NO_MASK;
- num_ints = (num_ints + 1) << 5;
+ num_ints = (num_ints + 1U) << 5;
/*
* Treat all SPIs as G1NS by default. The number of interrupts is
* calculated as 32 * (IT_LINES + 1). We do 32 at a time.
*/
- for (index = MIN_SPI_ID; index < num_ints; index += 32)
+ for (index = MIN_SPI_ID; index < num_ints; index += 32U)
gicd_write_igroupr(gicd_base, index, ~0U);
/* Setup the default SPI priorities doing four at a time */
- for (index = MIN_SPI_ID; index < num_ints; index += 4)
+ for (index = MIN_SPI_ID; index < num_ints; index += 4U)
gicd_write_ipriorityr(gicd_base,
index,
GICD_IPRIORITYR_DEF_VAL);
@@ -367,8 +373,8 @@
* Treat all SPIs as level triggered by default, write 16 at
* a time
*/
- for (index = MIN_SPI_ID; index < num_ints; index += 16)
- gicd_write_icfgr(gicd_base, index, 0);
+ for (index = MIN_SPI_ID; index < num_ints; index += 16U)
+ gicd_write_icfgr(gicd_base, index, 0U);
}
#if !ERROR_DEPRECATED
@@ -385,9 +391,10 @@
assert((int_grp == INTR_GROUP1S) || (int_grp == INTR_GROUP0));
/* If `num_ints` is not 0, ensure that `sec_intr_list` is not NULL */
- assert(num_ints ? (uintptr_t)sec_intr_list : 1);
+ if (num_ints != 0U)
+ assert(sec_intr_list != NULL);
- for (index = 0; index < num_ints; index++) {
+ for (index = 0U; index < num_ints; index++) {
irq_num = sec_intr_list[index];
if (irq_num >= MIN_SPI_ID) {
@@ -407,7 +414,7 @@
/* Target SPIs to the primary CPU */
gic_affinity_val =
- gicd_irouter_val_from_mpidr(read_mpidr(), 0);
+ gicd_irouter_val_from_mpidr(read_mpidr(), 0U);
gicd_write_irouter(gicd_base,
irq_num,
gic_affinity_val);
@@ -430,12 +437,13 @@
unsigned int i;
const interrupt_prop_t *current_prop;
unsigned long long gic_affinity_val;
- unsigned int ctlr_enable = 0;
+ unsigned int ctlr_enable = 0U;
/* Make sure there's a valid property array */
- assert(interrupt_props_num > 0 ? interrupt_props != NULL : 1);
+ if (interrupt_props_num > 0U)
+ assert(interrupt_props != NULL);
- for (i = 0; i < interrupt_props_num; i++) {
+ for (i = 0U; i < interrupt_props_num; i++) {
current_prop = &interrupt_props[i];
if (current_prop->intr_num < MIN_SPI_ID)
@@ -464,7 +472,8 @@
current_prop->intr_pri);
/* Target SPIs to the primary CPU */
- gic_affinity_val = gicd_irouter_val_from_mpidr(read_mpidr(), 0);
+ gic_affinity_val =
+ gicd_irouter_val_from_mpidr(read_mpidr(), 0U);
gicd_write_irouter(gicd_base, current_prop->intr_num,
gic_affinity_val);
@@ -487,20 +496,20 @@
* more scalable approach as it avoids clearing the enable bits in the
* GICD_CTLR
*/
- gicr_write_icenabler0(gicr_base, ~0);
+ gicr_write_icenabler0(gicr_base, ~0U);
gicr_wait_for_pending_write(gicr_base);
/* Treat all SGIs/PPIs as G1NS by default. */
gicr_write_igroupr0(gicr_base, ~0U);
/* Setup the default PPI/SGI priorities doing four at a time */
- for (index = 0; index < MIN_SPI_ID; index += 4)
+ for (index = 0U; index < MIN_SPI_ID; index += 4U)
gicr_write_ipriorityr(gicr_base,
index,
GICD_IPRIORITYR_DEF_VAL);
/* Configure all PPIs as level triggered by default */
- gicr_write_icfgr1(gicr_base, 0);
+ gicr_write_icfgr1(gicr_base, 0U);
}
#if !ERROR_DEPRECATED
@@ -516,7 +525,8 @@
assert((int_grp == INTR_GROUP1S) || (int_grp == INTR_GROUP0));
/* If `num_ints` is not 0, ensure that `sec_intr_list` is not NULL */
- assert(num_ints ? (uintptr_t)sec_intr_list : 1);
+ if (num_ints != 0U)
+ assert(sec_intr_list != NULL);
for (index = 0; index < num_ints; index++) {
irq_num = sec_intr_list[index];
@@ -552,12 +562,13 @@
{
unsigned int i;
const interrupt_prop_t *current_prop;
- unsigned int ctlr_enable = 0;
+ unsigned int ctlr_enable = 0U;
/* Make sure there's a valid property array */
- assert(interrupt_props_num > 0 ? interrupt_props != NULL : 1);
+ if (interrupt_props_num > 0U)
+ assert(interrupt_props != NULL);
- for (i = 0; i < interrupt_props_num; i++) {
+ for (i = 0U; i < interrupt_props_num; i++) {
current_prop = &interrupt_props[i];
if (current_prop->intr_num >= MIN_SPI_ID)