blob: 72b87c8b917f96c423278636f2becbe1a137d164 [file] [log] [blame]
Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
johpow01fa59c6f2020-10-02 13:41:11 -05002 * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +00007#ifndef ARCH_HELPERS_H
8#define ARCH_HELPERS_H
Achin Gupta4f6ad662013-10-25 09:08:21 +01009
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +000010#include <cdefs.h>
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +000011#include <stdbool.h>
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010012#include <stdint.h>
Antonio Nino Diaz4b32e622018-08-16 16:52:57 +010013#include <string.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010014
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000015#include <arch.h>
16
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010017/**********************************************************************
18 * Macros which create inline functions to read or write CPU system
19 * registers
20 *********************************************************************/
21
Sandrine Bailleux30c231b2015-01-07 16:36:11 +000022#define _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) \
Masahiro Yamada6292d772018-02-02 21:19:17 +090023static inline u_register_t read_ ## _name(void) \
Sandrine Bailleux30c231b2015-01-07 16:36:11 +000024{ \
Masahiro Yamada6292d772018-02-02 21:19:17 +090025 u_register_t v; \
Sandrine Bailleux30c231b2015-01-07 16:36:11 +000026 __asm__ volatile ("mrs %0, " #_reg_name : "=r" (v)); \
27 return v; \
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010028}
29
Sandrine Bailleux30c231b2015-01-07 16:36:11 +000030#define _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name) \
Masahiro Yamada6292d772018-02-02 21:19:17 +090031static inline void write_ ## _name(u_register_t v) \
Sandrine Bailleux30c231b2015-01-07 16:36:11 +000032{ \
33 __asm__ volatile ("msr " #_reg_name ", %0" : : "r" (v)); \
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010034}
35
Roberto Vargasc51cdb72017-09-18 09:53:25 +010036#define SYSREG_WRITE_CONST(reg_name, v) \
37 __asm__ volatile ("msr " #reg_name ", %0" : : "i" (v))
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010038
39/* Define read function for system register */
40#define DEFINE_SYSREG_READ_FUNC(_name) \
41 _DEFINE_SYSREG_READ_FUNC(_name, _name)
42
43/* Define read & write function for system register */
44#define DEFINE_SYSREG_RW_FUNCS(_name) \
45 _DEFINE_SYSREG_READ_FUNC(_name, _name) \
46 _DEFINE_SYSREG_WRITE_FUNC(_name, _name)
47
48/* Define read & write function for renamed system register */
49#define DEFINE_RENAME_SYSREG_RW_FUNCS(_name, _reg_name) \
50 _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) \
51 _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name)
52
Achin Gupta92712a52015-09-03 14:18:02 +010053/* Define read function for renamed system register */
54#define DEFINE_RENAME_SYSREG_READ_FUNC(_name, _reg_name) \
55 _DEFINE_SYSREG_READ_FUNC(_name, _reg_name)
56
57/* Define write function for renamed system register */
58#define DEFINE_RENAME_SYSREG_WRITE_FUNC(_name, _reg_name) \
59 _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name)
60
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010061/**********************************************************************
62 * Macros to create inline functions for system instructions
63 *********************************************************************/
64
65/* Define function for simple system instruction */
66#define DEFINE_SYSOP_FUNC(_op) \
Juan Castillo2d552402014-06-13 17:05:10 +010067static inline void _op(void) \
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010068{ \
69 __asm__ (#_op); \
70}
71
Alexei Fedorovb8f26e92020-02-06 17:11:03 +000072/* Define function for system instruction with register parameter */
73#define DEFINE_SYSOP_PARAM_FUNC(_op) \
74static inline void _op(uint64_t v) \
75{ \
76 __asm__ (#_op " %0" : : "r" (v)); \
77}
78
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010079/* Define function for system instruction with type specifier */
80#define DEFINE_SYSOP_TYPE_FUNC(_op, _type) \
Juan Castillo2d552402014-06-13 17:05:10 +010081static inline void _op ## _type(void) \
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010082{ \
Andre Przywara5c29cba2020-10-16 18:19:03 +010083 __asm__ (#_op " " #_type : : : "memory"); \
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010084}
85
86/* Define function for system instruction with register parameter */
87#define DEFINE_SYSOP_TYPE_PARAM_FUNC(_op, _type) \
88static inline void _op ## _type(uint64_t v) \
89{ \
90 __asm__ (#_op " " #_type ", %0" : : "r" (v)); \
91}
Achin Gupta4f6ad662013-10-25 09:08:21 +010092
93/*******************************************************************************
94 * TLB maintenance accessor prototypes
95 ******************************************************************************/
Antonio Nino Diaz3f13c352017-02-24 11:39:22 +000096
Soby Mathew16d006b2019-05-03 13:17:56 +010097#if ERRATA_A57_813419 || ERRATA_A76_1286807
Antonio Nino Diaz3f13c352017-02-24 11:39:22 +000098/*
99 * Define function for TLBI instruction with type specifier that implements
Soby Mathew16d006b2019-05-03 13:17:56 +0100100 * the workaround for errata 813419 of Cortex-A57 or errata 1286807 of
101 * Cortex-A76.
Antonio Nino Diaz3f13c352017-02-24 11:39:22 +0000102 */
Soby Mathew16d006b2019-05-03 13:17:56 +0100103#define DEFINE_TLBIOP_ERRATA_TYPE_FUNC(_type)\
Antonio Nino Diaz3f13c352017-02-24 11:39:22 +0000104static inline void tlbi ## _type(void) \
105{ \
106 __asm__("tlbi " #_type "\n" \
107 "dsb ish\n" \
108 "tlbi " #_type); \
109}
110
111/*
112 * Define function for TLBI instruction with register parameter that implements
Soby Mathew16d006b2019-05-03 13:17:56 +0100113 * the workaround for errata 813419 of Cortex-A57 or errata 1286807 of
114 * Cortex-A76.
Antonio Nino Diaz3f13c352017-02-24 11:39:22 +0000115 */
Soby Mathew16d006b2019-05-03 13:17:56 +0100116#define DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(_type) \
Antonio Nino Diaz3f13c352017-02-24 11:39:22 +0000117static inline void tlbi ## _type(uint64_t v) \
118{ \
119 __asm__("tlbi " #_type ", %0\n" \
120 "dsb ish\n" \
121 "tlbi " #_type ", %0" : : "r" (v)); \
122}
123#endif /* ERRATA_A57_813419 */
124
Ambroise Vincentf5fdfbc2019-02-21 14:16:24 +0000125#if ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319
126/*
127 * Define function for DC instruction with register parameter that enables
128 * the workaround for errata 819472, 824069 and 827319 of Cortex-A53.
129 */
130#define DEFINE_DCOP_ERRATA_A53_TYPE_PARAM_FUNC(_name, _type) \
131static inline void dc ## _name(uint64_t v) \
132{ \
133 __asm__("dc " #_type ", %0" : : "r" (v)); \
134}
135#endif /* ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319 */
136
Soby Mathew16d006b2019-05-03 13:17:56 +0100137#if ERRATA_A57_813419
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100138DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1)
139DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1is)
140DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2)
141DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2is)
Soby Mathew16d006b2019-05-03 13:17:56 +0100142DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle3)
143DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle3is)
144DEFINE_SYSOP_TYPE_FUNC(tlbi, vmalle1)
145#elif ERRATA_A76_1286807
146DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle1)
147DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle1is)
148DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle2)
149DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle2is)
150DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle3)
151DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle3is)
152DEFINE_TLBIOP_ERRATA_TYPE_FUNC(vmalle1)
Antonio Nino Diaz3f13c352017-02-24 11:39:22 +0000153#else
Soby Mathew16d006b2019-05-03 13:17:56 +0100154DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1)
155DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1is)
156DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2)
157DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2is)
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100158DEFINE_SYSOP_TYPE_FUNC(tlbi, alle3)
159DEFINE_SYSOP_TYPE_FUNC(tlbi, alle3is)
160DEFINE_SYSOP_TYPE_FUNC(tlbi, vmalle1)
Soby Mathew16d006b2019-05-03 13:17:56 +0100161#endif
Achin Gupta4f6ad662013-10-25 09:08:21 +0100162
Soby Mathew16d006b2019-05-03 13:17:56 +0100163#if ERRATA_A57_813419
Antonio Nino Diazac998032017-02-27 17:23:54 +0000164DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaae1is)
165DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaale1is)
166DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vae2is)
167DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vale2is)
Soby Mathew16d006b2019-05-03 13:17:56 +0100168DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vae3is)
169DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vale3is)
170#elif ERRATA_A76_1286807
171DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vaae1is)
172DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vaale1is)
173DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vae2is)
174DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vale2is)
175DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vae3is)
176DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vale3is)
Antonio Nino Diaz3f13c352017-02-24 11:39:22 +0000177#else
Soby Mathew16d006b2019-05-03 13:17:56 +0100178DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaae1is)
179DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaale1is)
180DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vae2is)
181DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vale2is)
Antonio Nino Diazac998032017-02-27 17:23:54 +0000182DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vae3is)
183DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vale3is)
Antonio Nino Diaz3f13c352017-02-24 11:39:22 +0000184#endif
Antonio Nino Diazac998032017-02-27 17:23:54 +0000185
Achin Gupta4f6ad662013-10-25 09:08:21 +0100186/*******************************************************************************
187 * Cache maintenance accessor prototypes
188 ******************************************************************************/
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100189DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, isw)
190DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cisw)
Ambroise Vincentf5fdfbc2019-02-21 14:16:24 +0000191#if ERRATA_A53_827319
192DEFINE_DCOP_ERRATA_A53_TYPE_PARAM_FUNC(csw, cisw)
193#else
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100194DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, csw)
Ambroise Vincentf5fdfbc2019-02-21 14:16:24 +0000195#endif
196#if ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319
197DEFINE_DCOP_ERRATA_A53_TYPE_PARAM_FUNC(cvac, civac)
198#else
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100199DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cvac)
Ambroise Vincentf5fdfbc2019-02-21 14:16:24 +0000200#endif
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100201DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, ivac)
202DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, civac)
Ambroise Vincentf5fdfbc2019-02-21 14:16:24 +0000203#if ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319
204DEFINE_DCOP_ERRATA_A53_TYPE_PARAM_FUNC(cvau, civac)
205#else
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100206DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cvau)
Ambroise Vincentf5fdfbc2019-02-21 14:16:24 +0000207#endif
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100208DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, zva)
209
Varun Wadekar97625e32015-03-13 14:59:03 +0530210/*******************************************************************************
211 * Address translation accessor prototypes
212 ******************************************************************************/
213DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e1r)
214DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e1w)
215DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e0r)
216DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e0w)
Douglas Raillard77414632018-08-21 12:54:45 +0100217DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s1e1r)
Jeenu Viswambharan1dc771b2017-10-19 09:15:15 +0100218DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s1e2r)
Douglas Raillard77414632018-08-21 12:54:45 +0100219DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s1e3r)
Varun Wadekar97625e32015-03-13 14:59:03 +0530220
Alexei Fedorovb8f26e92020-02-06 17:11:03 +0000221/*******************************************************************************
222 * Strip Pointer Authentication Code
223 ******************************************************************************/
224DEFINE_SYSOP_PARAM_FUNC(xpaci)
225
Antonio Nino Diaze40306b2017-01-13 15:03:07 +0000226void flush_dcache_range(uintptr_t addr, size_t size);
227void clean_dcache_range(uintptr_t addr, size_t size);
228void inv_dcache_range(uintptr_t addr, size_t size);
Masahiro Yamada019b4f82020-04-02 15:35:19 +0900229bool is_dcache_enabled(void);
Antonio Nino Diaze40306b2017-01-13 15:03:07 +0000230
231void dcsw_op_louis(u_register_t op_type);
232void dcsw_op_all(u_register_t op_type);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100233
Antonio Nino Diaz4613d5f2017-10-05 15:19:42 +0100234void disable_mmu_el1(void);
Dan Handleya17fefa2014-05-14 12:38:32 +0100235void disable_mmu_el3(void);
laurenw-arm56f1e3e2021-03-03 14:19:38 -0600236void disable_mpu_el2(void);
Antonio Nino Diaz4613d5f2017-10-05 15:19:42 +0100237void disable_mmu_icache_el1(void);
Dan Handleya17fefa2014-05-14 12:38:32 +0100238void disable_mmu_icache_el3(void);
laurenw-arm56f1e3e2021-03-03 14:19:38 -0600239void disable_mpu_icache_el2(void);
Andrew Thoelke438c63a2014-04-28 12:06:18 +0100240
Achin Gupta4f6ad662013-10-25 09:08:21 +0100241/*******************************************************************************
242 * Misc. accessor prototypes
243 ******************************************************************************/
Achin Gupta4f6ad662013-10-25 09:08:21 +0100244
Roberto Vargasc51cdb72017-09-18 09:53:25 +0100245#define write_daifclr(val) SYSREG_WRITE_CONST(daifclr, val)
246#define write_daifset(val) SYSREG_WRITE_CONST(daifset, val)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100247
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000248DEFINE_SYSREG_RW_FUNCS(par_el1)
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100249DEFINE_SYSREG_READ_FUNC(id_pfr1_el1)
Tomas Pilar6fd816e2020-10-28 15:34:12 +0000250DEFINE_SYSREG_READ_FUNC(id_aa64isar0_el1)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000251DEFINE_SYSREG_READ_FUNC(id_aa64isar1_el1)
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100252DEFINE_SYSREG_READ_FUNC(id_aa64pfr0_el1)
Dimitris Papastamosb091eb92019-02-27 11:46:48 +0000253DEFINE_SYSREG_READ_FUNC(id_aa64pfr1_el1)
dp-armee3457b2017-05-23 09:32:49 +0100254DEFINE_SYSREG_READ_FUNC(id_aa64dfr0_el1)
Varun Wadekard1301a92019-01-23 09:41:28 -0800255DEFINE_SYSREG_READ_FUNC(id_afr0_el1)
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100256DEFINE_SYSREG_READ_FUNC(CurrentEl)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000257DEFINE_SYSREG_READ_FUNC(ctr_el0)
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100258DEFINE_SYSREG_RW_FUNCS(daif)
259DEFINE_SYSREG_RW_FUNCS(spsr_el1)
260DEFINE_SYSREG_RW_FUNCS(spsr_el2)
261DEFINE_SYSREG_RW_FUNCS(spsr_el3)
262DEFINE_SYSREG_RW_FUNCS(elr_el1)
263DEFINE_SYSREG_RW_FUNCS(elr_el2)
264DEFINE_SYSREG_RW_FUNCS(elr_el3)
Venkatesh Yadav Abbarapuf80014d2020-11-27 02:58:24 -0700265DEFINE_SYSREG_RW_FUNCS(mdccsr_el0)
266DEFINE_SYSREG_RW_FUNCS(dbgdtrrx_el0)
267DEFINE_SYSREG_RW_FUNCS(dbgdtrtx_el0)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100268
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100269DEFINE_SYSOP_FUNC(wfi)
270DEFINE_SYSOP_FUNC(wfe)
271DEFINE_SYSOP_FUNC(sev)
272DEFINE_SYSOP_TYPE_FUNC(dsb, sy)
Soby Mathewed995662014-12-30 16:11:42 +0000273DEFINE_SYSOP_TYPE_FUNC(dmb, sy)
Juan Castillo2e86cb12016-01-13 15:01:09 +0000274DEFINE_SYSOP_TYPE_FUNC(dmb, st)
275DEFINE_SYSOP_TYPE_FUNC(dmb, ld)
Soby Mathewed995662014-12-30 16:11:42 +0000276DEFINE_SYSOP_TYPE_FUNC(dsb, ish)
Dimitris Papastamos5bdbb472017-10-13 12:06:06 +0100277DEFINE_SYSOP_TYPE_FUNC(dsb, nsh)
Antonio Nino Diazac998032017-02-27 17:23:54 +0000278DEFINE_SYSOP_TYPE_FUNC(dsb, ishst)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000279DEFINE_SYSOP_TYPE_FUNC(dmb, oshld)
280DEFINE_SYSOP_TYPE_FUNC(dmb, oshst)
281DEFINE_SYSOP_TYPE_FUNC(dmb, osh)
282DEFINE_SYSOP_TYPE_FUNC(dmb, nshld)
283DEFINE_SYSOP_TYPE_FUNC(dmb, nshst)
284DEFINE_SYSOP_TYPE_FUNC(dmb, nsh)
285DEFINE_SYSOP_TYPE_FUNC(dmb, ishld)
Jeenu Viswambharan62505072017-09-22 08:32:09 +0100286DEFINE_SYSOP_TYPE_FUNC(dmb, ishst)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000287DEFINE_SYSOP_TYPE_FUNC(dmb, ish)
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100288DEFINE_SYSOP_FUNC(isb)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100289
Antonio Nino Diazb4e3e4b2018-11-23 15:04:01 +0000290static inline void enable_irq(void)
291{
292 /*
293 * The compiler memory barrier will prevent the compiler from
294 * scheduling non-volatile memory access after the write to the
295 * register.
296 *
297 * This could happen if some initialization code issues non-volatile
298 * accesses to an area used by an interrupt handler, in the assumption
299 * that it is safe as the interrupts are disabled at the time it does
300 * that (according to program order). However, non-volatile accesses
301 * are not necessarily in program order relatively with volatile inline
302 * assembly statements (and volatile accesses).
303 */
304 COMPILER_BARRIER();
305 write_daifclr(DAIF_IRQ_BIT);
306 isb();
307}
308
309static inline void enable_fiq(void)
310{
311 COMPILER_BARRIER();
312 write_daifclr(DAIF_FIQ_BIT);
313 isb();
314}
315
316static inline void enable_serror(void)
317{
318 COMPILER_BARRIER();
319 write_daifclr(DAIF_ABT_BIT);
320 isb();
321}
322
323static inline void enable_debug_exceptions(void)
324{
325 COMPILER_BARRIER();
326 write_daifclr(DAIF_DBG_BIT);
327 isb();
328}
329
330static inline void disable_irq(void)
331{
332 COMPILER_BARRIER();
333 write_daifset(DAIF_IRQ_BIT);
334 isb();
335}
336
337static inline void disable_fiq(void)
338{
339 COMPILER_BARRIER();
340 write_daifset(DAIF_FIQ_BIT);
341 isb();
342}
343
344static inline void disable_serror(void)
345{
346 COMPILER_BARRIER();
347 write_daifset(DAIF_ABT_BIT);
348 isb();
349}
350
351static inline void disable_debug_exceptions(void)
352{
353 COMPILER_BARRIER();
354 write_daifset(DAIF_DBG_BIT);
355 isb();
356}
357
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100358void __dead2 smc(uint64_t x0, uint64_t x1, uint64_t x2, uint64_t x3,
359 uint64_t x4, uint64_t x5, uint64_t x6, uint64_t x7);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100360
361/*******************************************************************************
362 * System register accessor prototypes
363 ******************************************************************************/
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100364DEFINE_SYSREG_READ_FUNC(midr_el1)
365DEFINE_SYSREG_READ_FUNC(mpidr_el1)
Antonio Nino Diazd1beee22016-12-13 15:28:54 +0000366DEFINE_SYSREG_READ_FUNC(id_aa64mmfr0_el1)
johpow013e24c162020-04-22 14:05:13 -0500367DEFINE_SYSREG_READ_FUNC(id_aa64mmfr1_el1)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100368
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100369DEFINE_SYSREG_RW_FUNCS(scr_el3)
370DEFINE_SYSREG_RW_FUNCS(hcr_el2)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100371
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100372DEFINE_SYSREG_RW_FUNCS(vbar_el1)
373DEFINE_SYSREG_RW_FUNCS(vbar_el2)
374DEFINE_SYSREG_RW_FUNCS(vbar_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100375
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100376DEFINE_SYSREG_RW_FUNCS(sctlr_el1)
377DEFINE_SYSREG_RW_FUNCS(sctlr_el2)
378DEFINE_SYSREG_RW_FUNCS(sctlr_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100379
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100380DEFINE_SYSREG_RW_FUNCS(actlr_el1)
381DEFINE_SYSREG_RW_FUNCS(actlr_el2)
382DEFINE_SYSREG_RW_FUNCS(actlr_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100383
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100384DEFINE_SYSREG_RW_FUNCS(esr_el1)
385DEFINE_SYSREG_RW_FUNCS(esr_el2)
386DEFINE_SYSREG_RW_FUNCS(esr_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100387
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100388DEFINE_SYSREG_RW_FUNCS(afsr0_el1)
389DEFINE_SYSREG_RW_FUNCS(afsr0_el2)
390DEFINE_SYSREG_RW_FUNCS(afsr0_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100391
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100392DEFINE_SYSREG_RW_FUNCS(afsr1_el1)
393DEFINE_SYSREG_RW_FUNCS(afsr1_el2)
394DEFINE_SYSREG_RW_FUNCS(afsr1_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100395
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100396DEFINE_SYSREG_RW_FUNCS(far_el1)
397DEFINE_SYSREG_RW_FUNCS(far_el2)
398DEFINE_SYSREG_RW_FUNCS(far_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100399
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100400DEFINE_SYSREG_RW_FUNCS(mair_el1)
401DEFINE_SYSREG_RW_FUNCS(mair_el2)
402DEFINE_SYSREG_RW_FUNCS(mair_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100403
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100404DEFINE_SYSREG_RW_FUNCS(amair_el1)
405DEFINE_SYSREG_RW_FUNCS(amair_el2)
406DEFINE_SYSREG_RW_FUNCS(amair_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100407
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100408DEFINE_SYSREG_READ_FUNC(rvbar_el1)
409DEFINE_SYSREG_READ_FUNC(rvbar_el2)
410DEFINE_SYSREG_READ_FUNC(rvbar_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100411
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100412DEFINE_SYSREG_RW_FUNCS(rmr_el1)
413DEFINE_SYSREG_RW_FUNCS(rmr_el2)
414DEFINE_SYSREG_RW_FUNCS(rmr_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100415
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100416DEFINE_SYSREG_RW_FUNCS(tcr_el1)
417DEFINE_SYSREG_RW_FUNCS(tcr_el2)
418DEFINE_SYSREG_RW_FUNCS(tcr_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100419
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100420DEFINE_SYSREG_RW_FUNCS(ttbr0_el1)
421DEFINE_SYSREG_RW_FUNCS(ttbr0_el2)
422DEFINE_SYSREG_RW_FUNCS(ttbr0_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100423
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100424DEFINE_SYSREG_RW_FUNCS(ttbr1_el1)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100425
Sandrine Bailleux8b0eafe2015-11-25 17:00:44 +0000426DEFINE_SYSREG_RW_FUNCS(vttbr_el2)
427
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100428DEFINE_SYSREG_RW_FUNCS(cptr_el2)
429DEFINE_SYSREG_RW_FUNCS(cptr_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100430
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100431DEFINE_SYSREG_RW_FUNCS(cpacr_el1)
432DEFINE_SYSREG_RW_FUNCS(cntfrq_el0)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000433DEFINE_SYSREG_RW_FUNCS(cnthp_ctl_el2)
434DEFINE_SYSREG_RW_FUNCS(cnthp_tval_el2)
435DEFINE_SYSREG_RW_FUNCS(cnthp_cval_el2)
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100436DEFINE_SYSREG_RW_FUNCS(cntps_ctl_el1)
437DEFINE_SYSREG_RW_FUNCS(cntps_tval_el1)
438DEFINE_SYSREG_RW_FUNCS(cntps_cval_el1)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000439DEFINE_SYSREG_RW_FUNCS(cntp_ctl_el0)
440DEFINE_SYSREG_RW_FUNCS(cntp_tval_el0)
441DEFINE_SYSREG_RW_FUNCS(cntp_cval_el0)
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100442DEFINE_SYSREG_READ_FUNC(cntpct_el0)
443DEFINE_SYSREG_RW_FUNCS(cnthctl_el2)
Soby Mathew5e5c2072014-04-07 15:28:55 +0100444
Antonio Nino Diazdc4ed3d2018-11-23 13:54:00 +0000445#define get_cntp_ctl_enable(x) (((x) >> CNTP_CTL_ENABLE_SHIFT) & \
446 CNTP_CTL_ENABLE_MASK)
447#define get_cntp_ctl_imask(x) (((x) >> CNTP_CTL_IMASK_SHIFT) & \
448 CNTP_CTL_IMASK_MASK)
449#define get_cntp_ctl_istatus(x) (((x) >> CNTP_CTL_ISTATUS_SHIFT) & \
450 CNTP_CTL_ISTATUS_MASK)
451
452#define set_cntp_ctl_enable(x) ((x) |= (U(1) << CNTP_CTL_ENABLE_SHIFT))
453#define set_cntp_ctl_imask(x) ((x) |= (U(1) << CNTP_CTL_IMASK_SHIFT))
454
455#define clr_cntp_ctl_enable(x) ((x) &= ~(U(1) << CNTP_CTL_ENABLE_SHIFT))
456#define clr_cntp_ctl_imask(x) ((x) &= ~(U(1) << CNTP_CTL_IMASK_SHIFT))
457
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100458DEFINE_SYSREG_RW_FUNCS(tpidr_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100459
Soby Mathewfeddfcf2014-08-29 14:41:58 +0100460DEFINE_SYSREG_RW_FUNCS(cntvoff_el2)
461
Andrew Thoelke4e126072014-06-04 21:10:52 +0100462DEFINE_SYSREG_RW_FUNCS(vpidr_el2)
463DEFINE_SYSREG_RW_FUNCS(vmpidr_el2)
464
Soby Mathew26fb90e2015-01-06 21:36:55 +0000465DEFINE_SYSREG_READ_FUNC(isr_el1)
466
David Cunado5f55e282016-10-31 17:37:34 +0000467DEFINE_SYSREG_RW_FUNCS(mdcr_el2)
Dimitris Papastamos5bdbb472017-10-13 12:06:06 +0100468DEFINE_SYSREG_RW_FUNCS(mdcr_el3)
David Cunadoc14b08e2016-11-25 00:21:59 +0000469DEFINE_SYSREG_RW_FUNCS(hstr_el2)
David Cunado4168f2f2017-10-02 17:41:39 +0100470DEFINE_SYSREG_RW_FUNCS(pmcr_el0)
David Cunado5f55e282016-10-31 17:37:34 +0000471
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000472/* GICv3 System Registers */
473
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100474DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el1, ICC_SRE_EL1)
475DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el2, ICC_SRE_EL2)
476DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el3, ICC_SRE_EL3)
477DEFINE_RENAME_SYSREG_RW_FUNCS(icc_pmr_el1, ICC_PMR_EL1)
Jeenu Viswambharanb1e957e2017-09-22 08:32:09 +0100478DEFINE_RENAME_SYSREG_READ_FUNC(icc_rpr_el1, ICC_RPR_EL1)
Achin Gupta92712a52015-09-03 14:18:02 +0100479DEFINE_RENAME_SYSREG_RW_FUNCS(icc_igrpen1_el3, ICC_IGRPEN1_EL3)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000480DEFINE_RENAME_SYSREG_RW_FUNCS(icc_igrpen1_el1, ICC_IGRPEN1_EL1)
Achin Gupta92712a52015-09-03 14:18:02 +0100481DEFINE_RENAME_SYSREG_RW_FUNCS(icc_igrpen0_el1, ICC_IGRPEN0_EL1)
482DEFINE_RENAME_SYSREG_READ_FUNC(icc_hppir0_el1, ICC_HPPIR0_EL1)
483DEFINE_RENAME_SYSREG_READ_FUNC(icc_hppir1_el1, ICC_HPPIR1_EL1)
484DEFINE_RENAME_SYSREG_READ_FUNC(icc_iar0_el1, ICC_IAR0_EL1)
485DEFINE_RENAME_SYSREG_READ_FUNC(icc_iar1_el1, ICC_IAR1_EL1)
486DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_eoir0_el1, ICC_EOIR0_EL1)
487DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_eoir1_el1, ICC_EOIR1_EL1)
Jeenu Viswambharanab14e9b2017-09-22 08:32:09 +0100488DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_sgi0r_el1, ICC_SGI0R_EL1)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000489DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sgi1r, ICC_SGI1R)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100490
Alexei Fedorov7e6306b2020-07-14 08:17:56 +0100491DEFINE_RENAME_SYSREG_READ_FUNC(amcfgr_el0, AMCFGR_EL0)
492DEFINE_RENAME_SYSREG_READ_FUNC(amcgcr_el0, AMCGCR_EL0)
johpow01fa59c6f2020-10-02 13:41:11 -0500493DEFINE_RENAME_SYSREG_READ_FUNC(amcg1idr_el0, AMCG1IDR_EL0)
494DEFINE_RENAME_SYSREG_RW_FUNCS(amcr_el0, AMCR_EL0)
Dimitris Papastamose08005a2017-10-12 13:02:29 +0100495DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenclr0_el0, AMCNTENCLR0_EL0)
496DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenset0_el0, AMCNTENSET0_EL0)
497DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenclr1_el0, AMCNTENCLR1_EL0)
498DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenset1_el0, AMCNTENSET1_EL0)
499
Jeenu Viswambharan2da918c2018-07-31 16:13:33 +0100500DEFINE_RENAME_SYSREG_READ_FUNC(mpamidr_el1, MPAMIDR_EL1)
501DEFINE_RENAME_SYSREG_RW_FUNCS(mpam3_el3, MPAM3_EL3)
502DEFINE_RENAME_SYSREG_RW_FUNCS(mpam2_el2, MPAM2_EL2)
503DEFINE_RENAME_SYSREG_RW_FUNCS(mpamhcr_el2, MPAMHCR_EL2)
504
Dimitris Papastamos5bdbb472017-10-13 12:06:06 +0100505DEFINE_RENAME_SYSREG_RW_FUNCS(pmblimitr_el1, PMBLIMITR_EL1)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100506
David Cunadoce88eee2017-10-20 11:30:57 +0100507DEFINE_RENAME_SYSREG_WRITE_FUNC(zcr_el3, ZCR_EL3)
508DEFINE_RENAME_SYSREG_WRITE_FUNC(zcr_el2, ZCR_EL2)
509
Jeenu Viswambharan19f6cf22017-12-07 08:43:05 +0000510DEFINE_RENAME_SYSREG_READ_FUNC(erridr_el1, ERRIDR_EL1)
511DEFINE_RENAME_SYSREG_WRITE_FUNC(errselr_el1, ERRSELR_EL1)
512
513DEFINE_RENAME_SYSREG_READ_FUNC(erxfr_el1, ERXFR_EL1)
514DEFINE_RENAME_SYSREG_RW_FUNCS(erxctlr_el1, ERXCTLR_EL1)
515DEFINE_RENAME_SYSREG_RW_FUNCS(erxstatus_el1, ERXSTATUS_EL1)
516DEFINE_RENAME_SYSREG_READ_FUNC(erxaddr_el1, ERXADDR_EL1)
517DEFINE_RENAME_SYSREG_READ_FUNC(erxmisc0_el1, ERXMISC0_EL1)
518DEFINE_RENAME_SYSREG_READ_FUNC(erxmisc1_el1, ERXMISC1_EL1)
519
Antonio Nino Diazc326c342019-01-11 11:20:10 +0000520/* Armv8.2 Registers */
521DEFINE_RENAME_SYSREG_READ_FUNC(id_aa64mmfr2_el1, ID_AA64MMFR2_EL1)
522
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000523/* Armv8.3 Pointer Authentication Registers */
Antonio Nino Diaz25cda672019-02-19 11:53:51 +0000524DEFINE_RENAME_SYSREG_RW_FUNCS(apiakeyhi_el1, APIAKeyHi_EL1)
525DEFINE_RENAME_SYSREG_RW_FUNCS(apiakeylo_el1, APIAKeyLo_EL1)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000526
Justin Chadwell1c7c13a2019-07-18 14:25:33 +0100527/* Armv8.5 MTE Registers */
528DEFINE_RENAME_SYSREG_RW_FUNCS(tfsre0_el1, TFSRE0_EL1)
529DEFINE_RENAME_SYSREG_RW_FUNCS(tfsr_el1, TFSR_EL1)
530DEFINE_RENAME_SYSREG_RW_FUNCS(rgsr_el1, RGSR_EL1)
531DEFINE_RENAME_SYSREG_RW_FUNCS(gcr_el1, GCR_EL1)
532
Tomas Pilar6fd816e2020-10-28 15:34:12 +0000533/* Armv8.5 FEAT_RNG Registers */
534DEFINE_SYSREG_READ_FUNC(rndr)
535DEFINE_SYSREG_READ_FUNC(rndrrs)
536
johpow01f91e59f2021-08-04 19:38:18 -0500537/* FEAT_HCX Register */
538DEFINE_RENAME_SYSREG_RW_FUNCS(hcrx_el2, HCRX_EL2)
539
Madhukar Pappireddy90d65322019-10-30 14:24:39 -0500540/* DynamIQ Shared Unit power management */
541DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpwrdn_el1, CLUSTERPWRDN_EL1)
542
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100543#define IS_IN_EL(x) \
544 (GET_EL(read_CurrentEl()) == MODE_EL##x)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100545
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100546#define IS_IN_EL1() IS_IN_EL(1)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000547#define IS_IN_EL2() IS_IN_EL(2)
Douglas Raillard77414632018-08-21 12:54:45 +0100548#define IS_IN_EL3() IS_IN_EL(3)
549
550static inline unsigned int get_current_el(void)
551{
552 return GET_EL(read_CurrentEl());
553}
Achin Gupta4f6ad662013-10-25 09:08:21 +0100554
Masahiro Yamada8a6e9612020-03-26 13:18:48 +0900555static inline unsigned int get_current_el_maybe_constant(void)
556{
557#if defined(IMAGE_AT_EL1)
558 return 1;
559#elif defined(IMAGE_AT_EL2)
560 return 2; /* no use-case in TF-A */
561#elif defined(IMAGE_AT_EL3)
562 return 3;
563#else
564 /*
565 * If we do not know which exception level this is being built for
566 * (e.g. built for library), fall back to run-time detection.
567 */
568 return get_current_el();
569#endif
570}
571
Jeenu Viswambharan2a9b8822017-02-21 14:40:44 +0000572/*
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000573 * Check if an EL is implemented from AA64PFR0 register fields.
Jeenu Viswambharan2a9b8822017-02-21 14:40:44 +0000574 */
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000575static inline uint64_t el_implemented(unsigned int el)
576{
577 if (el > 3U) {
578 return EL_IMPL_NONE;
579 } else {
580 unsigned int shift = ID_AA64PFR0_EL1_SHIFT * el;
581
582 return (read_id_aa64pfr0_el1() >> shift) & ID_AA64PFR0_ELX_MASK;
583 }
584}
585
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100586/* Previously defined accesor functions with incomplete register names */
Achin Gupta4f6ad662013-10-25 09:08:21 +0100587
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100588#define read_current_el() read_CurrentEl()
Achin Gupta4f6ad662013-10-25 09:08:21 +0100589
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100590#define dsb() dsbsy()
Achin Gupta4f6ad662013-10-25 09:08:21 +0100591
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100592#define read_midr() read_midr_el1()
Achin Gupta4f6ad662013-10-25 09:08:21 +0100593
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100594#define read_mpidr() read_mpidr_el1()
Achin Gupta4f6ad662013-10-25 09:08:21 +0100595
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100596#define read_scr() read_scr_el3()
597#define write_scr(_v) write_scr_el3(_v)
Soby Mathew5e5c2072014-04-07 15:28:55 +0100598
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100599#define read_hcr() read_hcr_el2()
600#define write_hcr(_v) write_hcr_el2(_v)
Sandrine Bailleux25232af2014-05-09 11:23:11 +0100601
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100602#define read_cpacr() read_cpacr_el1()
603#define write_cpacr(_v) write_cpacr_el1(_v)
Soby Mathew5e5c2072014-04-07 15:28:55 +0100604
Madhukar Pappireddy90d65322019-10-30 14:24:39 -0500605#define read_clusterpwrdn() read_clusterpwrdn_el1()
606#define write_clusterpwrdn(_v) write_clusterpwrdn_el1(_v)
607
Manish V Badarkhebde5c952020-07-14 14:43:12 +0100608#if ERRATA_SPECULATIVE_AT
609/*
610 * Assuming SCTLR.M bit is already enabled
611 * 1. Enable page table walk by clearing TCR_EL1.EPDx bits
612 * 2. Execute AT instruction for lower EL1/0
613 * 3. Disable page table walk by setting TCR_EL1.EPDx bits
614 */
615#define AT(_at_inst, _va) \
616{ \
617 assert((read_sctlr_el1() & SCTLR_M_BIT) != 0ULL); \
618 write_tcr_el1(read_tcr_el1() & ~(TCR_EPD0_BIT | TCR_EPD1_BIT)); \
619 isb(); \
620 _at_inst(_va); \
621 write_tcr_el1(read_tcr_el1() | (TCR_EPD0_BIT | TCR_EPD1_BIT)); \
622 isb(); \
623}
624#else
625#define AT(_at_inst, _va) _at_inst(_va);
626#endif
627
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000628#endif /* ARCH_HELPERS_H */