blob: 8b3d53a480179dce00e8583eb52f28571b9b343b [file] [log] [blame]
Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Jeenu Viswambharan19f6cf22017-12-07 08:43:05 +00002 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +00007#ifndef ARCH_HELPERS_H
8#define ARCH_HELPERS_H
Achin Gupta4f6ad662013-10-25 09:08:21 +01009
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +000010#include <arch.h>
11#include <cdefs.h>
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +000012#include <stdbool.h>
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010013#include <stdint.h>
Antonio Nino Diaz4b32e622018-08-16 16:52:57 +010014#include <string.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010015
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010016/**********************************************************************
17 * Macros which create inline functions to read or write CPU system
18 * registers
19 *********************************************************************/
20
Sandrine Bailleux30c231b2015-01-07 16:36:11 +000021#define _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) \
Masahiro Yamada6292d772018-02-02 21:19:17 +090022static inline u_register_t read_ ## _name(void) \
Sandrine Bailleux30c231b2015-01-07 16:36:11 +000023{ \
Masahiro Yamada6292d772018-02-02 21:19:17 +090024 u_register_t v; \
Sandrine Bailleux30c231b2015-01-07 16:36:11 +000025 __asm__ volatile ("mrs %0, " #_reg_name : "=r" (v)); \
26 return v; \
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010027}
28
Sandrine Bailleux30c231b2015-01-07 16:36:11 +000029#define _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name) \
Masahiro Yamada6292d772018-02-02 21:19:17 +090030static inline void write_ ## _name(u_register_t v) \
Sandrine Bailleux30c231b2015-01-07 16:36:11 +000031{ \
32 __asm__ volatile ("msr " #_reg_name ", %0" : : "r" (v)); \
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010033}
34
Roberto Vargasc51cdb72017-09-18 09:53:25 +010035#define SYSREG_WRITE_CONST(reg_name, v) \
36 __asm__ volatile ("msr " #reg_name ", %0" : : "i" (v))
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010037
38/* Define read function for system register */
39#define DEFINE_SYSREG_READ_FUNC(_name) \
40 _DEFINE_SYSREG_READ_FUNC(_name, _name)
41
42/* Define read & write function for system register */
43#define DEFINE_SYSREG_RW_FUNCS(_name) \
44 _DEFINE_SYSREG_READ_FUNC(_name, _name) \
45 _DEFINE_SYSREG_WRITE_FUNC(_name, _name)
46
47/* Define read & write function for renamed system register */
48#define DEFINE_RENAME_SYSREG_RW_FUNCS(_name, _reg_name) \
49 _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) \
50 _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name)
51
Achin Gupta92712a52015-09-03 14:18:02 +010052/* Define read function for renamed system register */
53#define DEFINE_RENAME_SYSREG_READ_FUNC(_name, _reg_name) \
54 _DEFINE_SYSREG_READ_FUNC(_name, _reg_name)
55
56/* Define write function for renamed system register */
57#define DEFINE_RENAME_SYSREG_WRITE_FUNC(_name, _reg_name) \
58 _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name)
59
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010060/**********************************************************************
61 * Macros to create inline functions for system instructions
62 *********************************************************************/
63
64/* Define function for simple system instruction */
65#define DEFINE_SYSOP_FUNC(_op) \
Juan Castillo2d552402014-06-13 17:05:10 +010066static inline void _op(void) \
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010067{ \
68 __asm__ (#_op); \
69}
70
71/* Define function for system instruction with type specifier */
72#define DEFINE_SYSOP_TYPE_FUNC(_op, _type) \
Juan Castillo2d552402014-06-13 17:05:10 +010073static inline void _op ## _type(void) \
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010074{ \
75 __asm__ (#_op " " #_type); \
76}
77
78/* Define function for system instruction with register parameter */
79#define DEFINE_SYSOP_TYPE_PARAM_FUNC(_op, _type) \
80static inline void _op ## _type(uint64_t v) \
81{ \
82 __asm__ (#_op " " #_type ", %0" : : "r" (v)); \
83}
Achin Gupta4f6ad662013-10-25 09:08:21 +010084
85/*******************************************************************************
86 * TLB maintenance accessor prototypes
87 ******************************************************************************/
Antonio Nino Diaz3f13c352017-02-24 11:39:22 +000088
89#if ERRATA_A57_813419
90/*
91 * Define function for TLBI instruction with type specifier that implements
92 * the workaround for errata 813419 of Cortex-A57.
93 */
94#define DEFINE_TLBIOP_ERRATA_A57_813419_TYPE_FUNC(_type)\
95static inline void tlbi ## _type(void) \
96{ \
97 __asm__("tlbi " #_type "\n" \
98 "dsb ish\n" \
99 "tlbi " #_type); \
100}
101
102/*
103 * Define function for TLBI instruction with register parameter that implements
104 * the workaround for errata 813419 of Cortex-A57.
105 */
106#define DEFINE_TLBIOP_ERRATA_A57_813419_TYPE_PARAM_FUNC(_type) \
107static inline void tlbi ## _type(uint64_t v) \
108{ \
109 __asm__("tlbi " #_type ", %0\n" \
110 "dsb ish\n" \
111 "tlbi " #_type ", %0" : : "r" (v)); \
112}
113#endif /* ERRATA_A57_813419 */
114
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100115DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1)
116DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1is)
117DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2)
118DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2is)
Antonio Nino Diaz3f13c352017-02-24 11:39:22 +0000119#if ERRATA_A57_813419
120DEFINE_TLBIOP_ERRATA_A57_813419_TYPE_FUNC(alle3)
121DEFINE_TLBIOP_ERRATA_A57_813419_TYPE_FUNC(alle3is)
122#else
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100123DEFINE_SYSOP_TYPE_FUNC(tlbi, alle3)
124DEFINE_SYSOP_TYPE_FUNC(tlbi, alle3is)
Antonio Nino Diaz3f13c352017-02-24 11:39:22 +0000125#endif
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100126DEFINE_SYSOP_TYPE_FUNC(tlbi, vmalle1)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100127
Antonio Nino Diazac998032017-02-27 17:23:54 +0000128DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaae1is)
129DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaale1is)
130DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vae2is)
131DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vale2is)
Antonio Nino Diaz3f13c352017-02-24 11:39:22 +0000132#if ERRATA_A57_813419
133DEFINE_TLBIOP_ERRATA_A57_813419_TYPE_PARAM_FUNC(vae3is)
134DEFINE_TLBIOP_ERRATA_A57_813419_TYPE_PARAM_FUNC(vale3is)
135#else
Antonio Nino Diazac998032017-02-27 17:23:54 +0000136DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vae3is)
137DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vale3is)
Antonio Nino Diaz3f13c352017-02-24 11:39:22 +0000138#endif
Antonio Nino Diazac998032017-02-27 17:23:54 +0000139
Achin Gupta4f6ad662013-10-25 09:08:21 +0100140/*******************************************************************************
141 * Cache maintenance accessor prototypes
142 ******************************************************************************/
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100143DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, isw)
144DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cisw)
145DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, csw)
146DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cvac)
147DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, ivac)
148DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, civac)
149DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cvau)
150DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, zva)
151
Varun Wadekar97625e32015-03-13 14:59:03 +0530152/*******************************************************************************
153 * Address translation accessor prototypes
154 ******************************************************************************/
155DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e1r)
156DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e1w)
157DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e0r)
158DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e0w)
Douglas Raillard77414632018-08-21 12:54:45 +0100159DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s1e1r)
Jeenu Viswambharan1dc771b2017-10-19 09:15:15 +0100160DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s1e2r)
Douglas Raillard77414632018-08-21 12:54:45 +0100161DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s1e3r)
Varun Wadekar97625e32015-03-13 14:59:03 +0530162
Antonio Nino Diaze40306b2017-01-13 15:03:07 +0000163void flush_dcache_range(uintptr_t addr, size_t size);
164void clean_dcache_range(uintptr_t addr, size_t size);
165void inv_dcache_range(uintptr_t addr, size_t size);
166
167void dcsw_op_louis(u_register_t op_type);
168void dcsw_op_all(u_register_t op_type);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100169
Antonio Nino Diaz4613d5f2017-10-05 15:19:42 +0100170void disable_mmu_el1(void);
Dan Handleya17fefa2014-05-14 12:38:32 +0100171void disable_mmu_el3(void);
Antonio Nino Diaz4613d5f2017-10-05 15:19:42 +0100172void disable_mmu_icache_el1(void);
Dan Handleya17fefa2014-05-14 12:38:32 +0100173void disable_mmu_icache_el3(void);
Andrew Thoelke438c63a2014-04-28 12:06:18 +0100174
Achin Gupta4f6ad662013-10-25 09:08:21 +0100175/*******************************************************************************
176 * Misc. accessor prototypes
177 ******************************************************************************/
Achin Gupta4f6ad662013-10-25 09:08:21 +0100178
Roberto Vargasc51cdb72017-09-18 09:53:25 +0100179#define write_daifclr(val) SYSREG_WRITE_CONST(daifclr, val)
180#define write_daifset(val) SYSREG_WRITE_CONST(daifset, val)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100181
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000182DEFINE_SYSREG_RW_FUNCS(par_el1)
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100183DEFINE_SYSREG_READ_FUNC(id_pfr1_el1)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000184DEFINE_SYSREG_READ_FUNC(id_aa64isar1_el1)
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100185DEFINE_SYSREG_READ_FUNC(id_aa64pfr0_el1)
dp-armee3457b2017-05-23 09:32:49 +0100186DEFINE_SYSREG_READ_FUNC(id_aa64dfr0_el1)
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100187DEFINE_SYSREG_READ_FUNC(CurrentEl)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000188DEFINE_SYSREG_READ_FUNC(ctr_el0)
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100189DEFINE_SYSREG_RW_FUNCS(daif)
190DEFINE_SYSREG_RW_FUNCS(spsr_el1)
191DEFINE_SYSREG_RW_FUNCS(spsr_el2)
192DEFINE_SYSREG_RW_FUNCS(spsr_el3)
193DEFINE_SYSREG_RW_FUNCS(elr_el1)
194DEFINE_SYSREG_RW_FUNCS(elr_el2)
195DEFINE_SYSREG_RW_FUNCS(elr_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100196
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100197DEFINE_SYSOP_FUNC(wfi)
198DEFINE_SYSOP_FUNC(wfe)
199DEFINE_SYSOP_FUNC(sev)
200DEFINE_SYSOP_TYPE_FUNC(dsb, sy)
Soby Mathewed995662014-12-30 16:11:42 +0000201DEFINE_SYSOP_TYPE_FUNC(dmb, sy)
Juan Castillo2e86cb12016-01-13 15:01:09 +0000202DEFINE_SYSOP_TYPE_FUNC(dmb, st)
203DEFINE_SYSOP_TYPE_FUNC(dmb, ld)
Soby Mathewed995662014-12-30 16:11:42 +0000204DEFINE_SYSOP_TYPE_FUNC(dsb, ish)
Dimitris Papastamos5bdbb472017-10-13 12:06:06 +0100205DEFINE_SYSOP_TYPE_FUNC(dsb, nsh)
Antonio Nino Diazac998032017-02-27 17:23:54 +0000206DEFINE_SYSOP_TYPE_FUNC(dsb, ishst)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000207DEFINE_SYSOP_TYPE_FUNC(dmb, oshld)
208DEFINE_SYSOP_TYPE_FUNC(dmb, oshst)
209DEFINE_SYSOP_TYPE_FUNC(dmb, osh)
210DEFINE_SYSOP_TYPE_FUNC(dmb, nshld)
211DEFINE_SYSOP_TYPE_FUNC(dmb, nshst)
212DEFINE_SYSOP_TYPE_FUNC(dmb, nsh)
213DEFINE_SYSOP_TYPE_FUNC(dmb, ishld)
Jeenu Viswambharan62505072017-09-22 08:32:09 +0100214DEFINE_SYSOP_TYPE_FUNC(dmb, ishst)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000215DEFINE_SYSOP_TYPE_FUNC(dmb, ish)
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100216DEFINE_SYSOP_FUNC(isb)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100217
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100218uint32_t get_afflvl_shift(uint32_t);
219uint32_t mpidr_mask_lower_afflvls(uint64_t, uint32_t);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100220
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100221void __dead2 eret(uint64_t x0, uint64_t x1, uint64_t x2, uint64_t x3,
222 uint64_t x4, uint64_t x5, uint64_t x6, uint64_t x7);
223void __dead2 smc(uint64_t x0, uint64_t x1, uint64_t x2, uint64_t x3,
224 uint64_t x4, uint64_t x5, uint64_t x6, uint64_t x7);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100225
226/*******************************************************************************
227 * System register accessor prototypes
228 ******************************************************************************/
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100229DEFINE_SYSREG_READ_FUNC(midr_el1)
230DEFINE_SYSREG_READ_FUNC(mpidr_el1)
Antonio Nino Diazd1beee22016-12-13 15:28:54 +0000231DEFINE_SYSREG_READ_FUNC(id_aa64mmfr0_el1)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100232
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100233DEFINE_SYSREG_RW_FUNCS(scr_el3)
234DEFINE_SYSREG_RW_FUNCS(hcr_el2)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100235
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100236DEFINE_SYSREG_RW_FUNCS(vbar_el1)
237DEFINE_SYSREG_RW_FUNCS(vbar_el2)
238DEFINE_SYSREG_RW_FUNCS(vbar_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100239
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100240DEFINE_SYSREG_RW_FUNCS(sctlr_el1)
241DEFINE_SYSREG_RW_FUNCS(sctlr_el2)
242DEFINE_SYSREG_RW_FUNCS(sctlr_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100243
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100244DEFINE_SYSREG_RW_FUNCS(actlr_el1)
245DEFINE_SYSREG_RW_FUNCS(actlr_el2)
246DEFINE_SYSREG_RW_FUNCS(actlr_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100247
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100248DEFINE_SYSREG_RW_FUNCS(esr_el1)
249DEFINE_SYSREG_RW_FUNCS(esr_el2)
250DEFINE_SYSREG_RW_FUNCS(esr_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100251
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100252DEFINE_SYSREG_RW_FUNCS(afsr0_el1)
253DEFINE_SYSREG_RW_FUNCS(afsr0_el2)
254DEFINE_SYSREG_RW_FUNCS(afsr0_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100255
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100256DEFINE_SYSREG_RW_FUNCS(afsr1_el1)
257DEFINE_SYSREG_RW_FUNCS(afsr1_el2)
258DEFINE_SYSREG_RW_FUNCS(afsr1_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100259
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100260DEFINE_SYSREG_RW_FUNCS(far_el1)
261DEFINE_SYSREG_RW_FUNCS(far_el2)
262DEFINE_SYSREG_RW_FUNCS(far_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100263
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100264DEFINE_SYSREG_RW_FUNCS(mair_el1)
265DEFINE_SYSREG_RW_FUNCS(mair_el2)
266DEFINE_SYSREG_RW_FUNCS(mair_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100267
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100268DEFINE_SYSREG_RW_FUNCS(amair_el1)
269DEFINE_SYSREG_RW_FUNCS(amair_el2)
270DEFINE_SYSREG_RW_FUNCS(amair_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100271
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100272DEFINE_SYSREG_READ_FUNC(rvbar_el1)
273DEFINE_SYSREG_READ_FUNC(rvbar_el2)
274DEFINE_SYSREG_READ_FUNC(rvbar_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100275
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100276DEFINE_SYSREG_RW_FUNCS(rmr_el1)
277DEFINE_SYSREG_RW_FUNCS(rmr_el2)
278DEFINE_SYSREG_RW_FUNCS(rmr_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100279
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100280DEFINE_SYSREG_RW_FUNCS(tcr_el1)
281DEFINE_SYSREG_RW_FUNCS(tcr_el2)
282DEFINE_SYSREG_RW_FUNCS(tcr_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100283
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100284DEFINE_SYSREG_RW_FUNCS(ttbr0_el1)
285DEFINE_SYSREG_RW_FUNCS(ttbr0_el2)
286DEFINE_SYSREG_RW_FUNCS(ttbr0_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100287
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100288DEFINE_SYSREG_RW_FUNCS(ttbr1_el1)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100289
Sandrine Bailleux8b0eafe2015-11-25 17:00:44 +0000290DEFINE_SYSREG_RW_FUNCS(vttbr_el2)
291
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100292DEFINE_SYSREG_RW_FUNCS(cptr_el2)
293DEFINE_SYSREG_RW_FUNCS(cptr_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100294
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100295DEFINE_SYSREG_RW_FUNCS(cpacr_el1)
296DEFINE_SYSREG_RW_FUNCS(cntfrq_el0)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000297DEFINE_SYSREG_RW_FUNCS(cnthp_ctl_el2)
298DEFINE_SYSREG_RW_FUNCS(cnthp_tval_el2)
299DEFINE_SYSREG_RW_FUNCS(cnthp_cval_el2)
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100300DEFINE_SYSREG_RW_FUNCS(cntps_ctl_el1)
301DEFINE_SYSREG_RW_FUNCS(cntps_tval_el1)
302DEFINE_SYSREG_RW_FUNCS(cntps_cval_el1)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000303DEFINE_SYSREG_RW_FUNCS(cntp_ctl_el0)
304DEFINE_SYSREG_RW_FUNCS(cntp_tval_el0)
305DEFINE_SYSREG_RW_FUNCS(cntp_cval_el0)
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100306DEFINE_SYSREG_READ_FUNC(cntpct_el0)
307DEFINE_SYSREG_RW_FUNCS(cnthctl_el2)
Soby Mathew5e5c2072014-04-07 15:28:55 +0100308
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100309DEFINE_SYSREG_RW_FUNCS(tpidr_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100310
Soby Mathewfeddfcf2014-08-29 14:41:58 +0100311DEFINE_SYSREG_RW_FUNCS(cntvoff_el2)
312
Andrew Thoelke4e126072014-06-04 21:10:52 +0100313DEFINE_SYSREG_RW_FUNCS(vpidr_el2)
314DEFINE_SYSREG_RW_FUNCS(vmpidr_el2)
315
Soby Mathew26fb90e2015-01-06 21:36:55 +0000316DEFINE_SYSREG_READ_FUNC(isr_el1)
317
David Cunado5f55e282016-10-31 17:37:34 +0000318DEFINE_SYSREG_RW_FUNCS(mdcr_el2)
Dimitris Papastamos5bdbb472017-10-13 12:06:06 +0100319DEFINE_SYSREG_RW_FUNCS(mdcr_el3)
David Cunadoc14b08e2016-11-25 00:21:59 +0000320DEFINE_SYSREG_RW_FUNCS(hstr_el2)
David Cunado4168f2f2017-10-02 17:41:39 +0100321DEFINE_SYSREG_RW_FUNCS(pmcr_el0)
David Cunado5f55e282016-10-31 17:37:34 +0000322
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000323/* GICv3 System Registers */
324
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100325DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el1, ICC_SRE_EL1)
326DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el2, ICC_SRE_EL2)
327DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el3, ICC_SRE_EL3)
328DEFINE_RENAME_SYSREG_RW_FUNCS(icc_pmr_el1, ICC_PMR_EL1)
Jeenu Viswambharanb1e957e2017-09-22 08:32:09 +0100329DEFINE_RENAME_SYSREG_READ_FUNC(icc_rpr_el1, ICC_RPR_EL1)
Achin Gupta92712a52015-09-03 14:18:02 +0100330DEFINE_RENAME_SYSREG_RW_FUNCS(icc_igrpen1_el3, ICC_IGRPEN1_EL3)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000331DEFINE_RENAME_SYSREG_RW_FUNCS(icc_igrpen1_el1, ICC_IGRPEN1_EL1)
Achin Gupta92712a52015-09-03 14:18:02 +0100332DEFINE_RENAME_SYSREG_RW_FUNCS(icc_igrpen0_el1, ICC_IGRPEN0_EL1)
333DEFINE_RENAME_SYSREG_READ_FUNC(icc_hppir0_el1, ICC_HPPIR0_EL1)
334DEFINE_RENAME_SYSREG_READ_FUNC(icc_hppir1_el1, ICC_HPPIR1_EL1)
335DEFINE_RENAME_SYSREG_READ_FUNC(icc_iar0_el1, ICC_IAR0_EL1)
336DEFINE_RENAME_SYSREG_READ_FUNC(icc_iar1_el1, ICC_IAR1_EL1)
337DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_eoir0_el1, ICC_EOIR0_EL1)
338DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_eoir1_el1, ICC_EOIR1_EL1)
Jeenu Viswambharanab14e9b2017-09-22 08:32:09 +0100339DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_sgi0r_el1, ICC_SGI0R_EL1)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000340DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sgi1r, ICC_SGI1R)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100341
Dimitris Papastamos525c37a2017-11-13 09:49:45 +0000342DEFINE_RENAME_SYSREG_RW_FUNCS(amcgcr_el0, AMCGCR_EL0)
Dimitris Papastamose08005a2017-10-12 13:02:29 +0100343DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenclr0_el0, AMCNTENCLR0_EL0)
344DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenset0_el0, AMCNTENSET0_EL0)
345DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenclr1_el0, AMCNTENCLR1_EL0)
346DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenset1_el0, AMCNTENSET1_EL0)
347
Jeenu Viswambharan2da918c2018-07-31 16:13:33 +0100348DEFINE_RENAME_SYSREG_READ_FUNC(mpamidr_el1, MPAMIDR_EL1)
349DEFINE_RENAME_SYSREG_RW_FUNCS(mpam3_el3, MPAM3_EL3)
350DEFINE_RENAME_SYSREG_RW_FUNCS(mpam2_el2, MPAM2_EL2)
351DEFINE_RENAME_SYSREG_RW_FUNCS(mpamhcr_el2, MPAMHCR_EL2)
352
Dimitris Papastamos5bdbb472017-10-13 12:06:06 +0100353DEFINE_RENAME_SYSREG_RW_FUNCS(pmblimitr_el1, PMBLIMITR_EL1)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100354
David Cunadoce88eee2017-10-20 11:30:57 +0100355DEFINE_RENAME_SYSREG_WRITE_FUNC(zcr_el3, ZCR_EL3)
356DEFINE_RENAME_SYSREG_WRITE_FUNC(zcr_el2, ZCR_EL2)
357
Jeenu Viswambharan19f6cf22017-12-07 08:43:05 +0000358DEFINE_RENAME_SYSREG_READ_FUNC(erridr_el1, ERRIDR_EL1)
359DEFINE_RENAME_SYSREG_WRITE_FUNC(errselr_el1, ERRSELR_EL1)
360
361DEFINE_RENAME_SYSREG_READ_FUNC(erxfr_el1, ERXFR_EL1)
362DEFINE_RENAME_SYSREG_RW_FUNCS(erxctlr_el1, ERXCTLR_EL1)
363DEFINE_RENAME_SYSREG_RW_FUNCS(erxstatus_el1, ERXSTATUS_EL1)
364DEFINE_RENAME_SYSREG_READ_FUNC(erxaddr_el1, ERXADDR_EL1)
365DEFINE_RENAME_SYSREG_READ_FUNC(erxmisc0_el1, ERXMISC0_EL1)
366DEFINE_RENAME_SYSREG_READ_FUNC(erxmisc1_el1, ERXMISC1_EL1)
367
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000368/* Armv8.3 Pointer Authentication Registers */
369DEFINE_RENAME_SYSREG_RW_FUNCS(apgakeylo_el1, APGAKeyLo_EL1)
370
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100371#define IS_IN_EL(x) \
372 (GET_EL(read_CurrentEl()) == MODE_EL##x)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100373
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100374#define IS_IN_EL1() IS_IN_EL(1)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000375#define IS_IN_EL2() IS_IN_EL(2)
Douglas Raillard77414632018-08-21 12:54:45 +0100376#define IS_IN_EL3() IS_IN_EL(3)
377
378static inline unsigned int get_current_el(void)
379{
380 return GET_EL(read_CurrentEl());
381}
Achin Gupta4f6ad662013-10-25 09:08:21 +0100382
Jeenu Viswambharan2a9b8822017-02-21 14:40:44 +0000383/*
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000384 * Check if an EL is implemented from AA64PFR0 register fields.
Jeenu Viswambharan2a9b8822017-02-21 14:40:44 +0000385 */
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000386static inline uint64_t el_implemented(unsigned int el)
387{
388 if (el > 3U) {
389 return EL_IMPL_NONE;
390 } else {
391 unsigned int shift = ID_AA64PFR0_EL1_SHIFT * el;
392
393 return (read_id_aa64pfr0_el1() >> shift) & ID_AA64PFR0_ELX_MASK;
394 }
395}
396
397#if !ERROR_DEPRECATED
398#define EL_IMPLEMENTED(_el) el_implemented(_el)
399#endif
Jeenu Viswambharan2a9b8822017-02-21 14:40:44 +0000400
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100401/* Previously defined accesor functions with incomplete register names */
Achin Gupta4f6ad662013-10-25 09:08:21 +0100402
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100403#define read_current_el() read_CurrentEl()
Achin Gupta4f6ad662013-10-25 09:08:21 +0100404
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100405#define dsb() dsbsy()
Achin Gupta4f6ad662013-10-25 09:08:21 +0100406
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100407#define read_midr() read_midr_el1()
Achin Gupta4f6ad662013-10-25 09:08:21 +0100408
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100409#define read_mpidr() read_mpidr_el1()
Achin Gupta4f6ad662013-10-25 09:08:21 +0100410
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100411#define read_scr() read_scr_el3()
412#define write_scr(_v) write_scr_el3(_v)
Soby Mathew5e5c2072014-04-07 15:28:55 +0100413
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100414#define read_hcr() read_hcr_el2()
415#define write_hcr(_v) write_hcr_el2(_v)
Sandrine Bailleux25232af2014-05-09 11:23:11 +0100416
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100417#define read_cpacr() read_cpacr_el1()
418#define write_cpacr(_v) write_cpacr_el1(_v)
Soby Mathew5e5c2072014-04-07 15:28:55 +0100419
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000420#endif /* ARCH_HELPERS_H */